Abstract: Disclosed embodiments are related to techniques for powering compute platforms in low temperature environments. Embodiments include a preheating stage that is added to a power up sequence. The preheating stage may include a force-on stage and a force-offstage. During the force-on stage, all power rails of target components are forced to an ON state so that the target components consume current. When a target operating temperature is reached, the power rails of the target components are turned off, which causes the target components to revert back to their initial (pre-boot) state allowing the normal boot process to take place. Since the target components are now heated up, the boot process can execute faster than when the target components were cold. Other embodiments may be described and/or claimed.

Abstract: According to a magnetic disk apparatus of one embodiment, threshold voltages of memory cell transistors of a flash memory are set to a first section for a first value or to a second section for a second value. The second section is on a lower voltage side than the first section. The controller performs bit inversion of second data held in a volatile memory and writes the second data onto the flash memory when a power loss occurs while the second data corresponds to third data in which a number of the first values is larger than that of the second values. The controller writes the second data onto the flash memory without bit inversion when a power loss occurs while the second data corresponds to fourth data. The fourth data is data in which a number of the first values is smaller than that of the second values.

Abstract: A method for addressing power outage of an arithmetic logic apparatus including an arithmetic logic part, a power supply port to which power is externally supplied, and a battery, the arithmetic logic part including a primary system device and a secondary system device, the method includes detection processing of detecting disruption of power in the power supply port, supplying processing of supplying power from the battery to the arithmetic logic part when the disruption is detected in the detection processing, end processing of performing processing of ending the secondary system device to reduce power consumption of the secondary system device when the supplying processing is performed, and backup processing of performing data backup using the primary system device upon completion of the end processing.

Abstract: Systems and methods are disclosed for harvesting electrical energy from mechanical components of hard disk drives (HDDs) in a data storage system and propagating the electrical energy to devices outside of the HDDs. A power distribution board (PDB) may be coupled to a plurality of HDDs and used to detect a voltage drop on a connection between the PDB and the HDDs indicative of a power loss condition, and, in response, enable the flow of electrical energy from the HDDs to the PDB. The electrical energy from the HDDs may be converted for use by the PDB and/or distribution to other components of the data storage system.

Abstract: A power management device and a management method thereof are provided. The power management device includes a switch, a detection circuit and a controller. The switch receives an external power. The detection circuit receives an internal power and at least one operation power. The detection circuit determines whether at least one of the internal power and the operation power is in a preset specification range or not to generate a protection activate signal. The controller sets a protection flag according to the protection activate signal, and generates a control signal according to the protection flag by executing an application program. The controller transmits the control signal to turn off the switch.

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a first memory region and a second memory region. The controller stores, into the second memory region, copied data of original data stored in the first memory region and an address of the first memory region while storing, into the first memory region, an address of the second memory region, when detecting occurrence of a critical event.

Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status.

Abstract: An improved method and system for controlling the powering-on of an electronic device when initially the internal temperature is below a safe threshold. The method and system can preheat the electronic device until it is at a safe temperature in which to safely power-on the electronic device. Alternatively or in addition, the method and system can alert a user if the temperature is below a threshold and proceed to power-on when the temperature is above the threshold.

Abstract: A computation graph of a machine learning model is accessed from memory and a constraint solver is used to compute a partition of the computation graph into ordered stages of an execution pipeline. In use, when inference or training of the machine learning model takes place by executing the pipeline, execution cost of the stages are balanced according to the computed partition.

Abstract: A reconfigurable data processor includes an array of configurable units. The array includes a two or more sub-arrays of configurable units, and sub-arrays of configurable units in the plurality of sub-arrays of configurable units are configurable to separately execute different programs. The reconfigurable data processor also includes a force-quit controller connected to the array. The force-quit controller can stop execution of a particular program on a particular sub-array of configurable units and reset the particular sub-array of configurable units, while remaining sub-arrays of configurable units continue execution of their respective programs.

Abstract: A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vmin for energy-efficiency. Such Vmin values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest Vmin. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest Vmin. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Disclosed methods and system feature or perform operations including monitoring, within an operating system (OS) environment of an information handling system, telemetry data indicative of values for one or more hardware status parameters and generating any of one or more anomaly alerts responsive to identifying any of one or more anomalous conditions. Responsive to detecting an anomaly alert, an OS-context configuration may be determined based on the hardware status parameters monitored during a timebox associated with the anomaly alert. Responsive to detecting a reset of the information handling system, preboot operations may be performed wherein the pre-boot operations may include configuring the information handling system in accordance with the OS-context configuration and performing one or more hardware diagnostic routines while the information handling system is configured in accordance with the OS-context configuration.

Abstract: A method and a device for low-power acceleration detection in a stationary vehicle are provided. The method includes putting a telematics device into a sleep mode, performing a plurality of micro wakeups during which a plurality of accelerometer readings are captured. The method further includes sending the plurality of accelerometer readings over a network interface to a telematics server. The telematics device which carries out the method has a controller, memory, and network interface. An accident impact profile may be recorded during the micro wakeups and sent during a regular wakeup duration for analysis by the telematics server.

Abstract: A method for indexing virtual machine version snapshots in a virtualization environment commences upon receiving a request (e.g., from an administrator or agent) to initiate a virtual machine version snapshot operation on a subject virtual machine. Processes within or controlled by the subject virtual machine are requested to temporarily suspend transactions and file I/O. When the processes that have been requested to temporarily suspend transactions and file I/O acknowledge quiescence, the method continues by generating a virtual machine version snapshot data structure. An entry in an index is formed from the virtual machine version snapshot data structure. Multiple instances of virtual machine version snapshot data structures can be stored in the index, and the index can be queried to determine the state that a virtual machine had at any of the snapshotted moments in time.

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

Abstract: A power transmitter for wireless power transfer includes a sensing system, a feedback mechanism and a control and communications unit includes a controller configured to receive object detection data from the sensing system, if a power receiver is detected, reset an alert timer, if the power receiver has been detected and a disconnect is detected, determine if an alert timer value is greater than an alert threshold, if a disconnect is detected and the alert timer value is greater than the alert threshold, instruct the feedback mechanism to output an alert. The power transmitter further includes an inverter circuit configured to receive a direct current (DC) power and convert the input power to a power signal and a coil configured to transmit the power signal to a power receiver, the coil formed of wound Litz wire and including at least one layer, the coil defining, at least, a top face.

Abstract: Apparatuses, methods, systems, and program products are disclosed to determine when a portable electronic device is moved within an enclosed space. A processor and memory may control a sensor may store code executable by the processor to measure a parameter at an inlet of the computing device. The parameter may include an airflow rate, an air temperature at the inlet, and/or a current supply to a fan of the computing device. The processor may execute code to determine when the parameter at the inlet reaches a threshold. When the processor determines that the measured parameter has reached the threshold, a signal from the sensor to the processor and/or from the processor to an operator may be sent, indicating that the threshold has been reached.

Abstract: A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.

Abstract: The present disclosure provides a method of synchronizing an online game, and a server device, that do not require centralized information management, reduce the processing burden on each device during online communication, and allow for continuation of processing in an offline environment. A method, according to the present disclosure, of synchronizing an online game that allows for transmission and reception of information related to game processing between a first client terminal and a second client terminal via a server includes: receiving, from the first client terminal connected online, first information related to game processing on the first client terminal; determining whether the first information is information that determines a game status; and storing the first information on the server and transmitting the first information to the second client terminal when the first information is determined to be information that determines the game status.

Abstract: A plurality of external power (“EP”) sources can be controlled with a single EP switch. A plurality of EP states can be determined, each EP state of the plurality of EP states being associated with one EP source from the plurality of EP sources. A highest EP state of the plurality of EP states can be determined. An EP indicator of the EP switch can be controlled based on the highest EP state.

Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

Abstract: An electronic device is provided.

Abstract: Apparatuses and methods for preventing accidental-shutdown in a robot-assisted surgical device are disclosed. An exemplary control apparatus includes an on/off key configured to trigger a start action or a shutdown action, an on/off control module configured to detect the shutdown action of the on/off key and obtain a shutdown intention through man-machine interaction, and an on/off hardware circuit configured to detect the start action and send a signal to a power supply. The on/off hardware circuit is configured to detect the shutdown action of the on/off key and a shutdown control signal sent by the on/off control module and send a signal to cut off the power supply. The control apparatus can reduce the probability of accidental shutdown caused by system software and hardware failure or man-made mis-operation and improve the operating reliability of the robot-assisted surgical device without significantly increasing cost.

Abstract: A transaction card with a luminous display includes a card body, an electronic control module, a light emitting module and a light guide module. The card body is provided with a light-transparent frame part around; the electronic control module is provided in the card body; the light emitting module is provided in the card body and electrically connected to the electronic control module; the light guide module is provided in the card body and corresponds to the light emitting module, the light guide module guides a light source of the light emitting module to the light-transparent frame part of the card body.

Abstract: Techniques are provided for improved restart of a system. In an example, a system can alternate storing a status register value or state to two or more non-volatile memory locations. Upon a power interruption and restart, the value of the status register can be restored to a state very close to or commensurate with a last occurring state even if a write operation to one of the non-volatile memory locations resulted an inaccurate saving of that state of the status register.

Abstract: Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.

Abstract: According to a first aspect, an industrial personal computer (IRC) (100) is provided. The IPC comprises: •a first housing module (10) having a first electronic component, an internal electric power supply device and a first electric connection portion; and •a second housing module (20?) having a second electronic component and a second electric connection portion, the first and the second housing modules being stacked along a stacking direction (SD), wherein the first and second connection portions form a connection bus along the stacking direction at least for transmitting electric power between the first and second housing modules; wherein •the second electronic component is an uninterruptible power supply (UPS) device (21); and •the IRC further comprising a power management controller (28).

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

Abstract: A method includes receiving signaling indicative of performance of a shutdown operation involving a memory device to a controller resident on the memory device; initiating a power off sequence in response to the received signaling, wherein the power off sequence includes execution of instructions corresponding to a plurality of routines; and writing data comprising respective shutdown signatures associated with execution of the plurality of routines to a media associated with the memory device upon completion of each of one or more of the plurality of routines, wherein the media is bit-addressable or byte-addressable.

Abstract: Techniques are provided for persistent memory file system reconciliation. As part of the persistent memory file system reconciliation, high level file system metadata associated with a persistent memory file system of persistent memory is reconciled. Client access to the persistent memory file system is inaccessible until reconciliation of the high level file system metadata has completed. A first scanner is executed to traverse pages of the persistent memory in order to fix local inconsistencies associated with the pages. A local inconsistency of a first set of metadata or data of a page is fixed using a second set of metadata or data of the page. The first scanner is executed asynchronously in parallel with processing client I/O directed to the persistent memory file system.

Abstract: The disclosure provides a power management method and a power management device. The method includes: reading a specific memory which includes a plurality of error data records; selecting a specific data record based on a usage status indicator of each error data record; sequentially sending an enable signal to each hardware device; in response to determining that an enable successful response corresponding to the enable signal is not received from a specific hardware device, or a boot alarm is received, at least obtaining a low pin count value and a power management status; recording the low pin count value and the power management status in the specific data record, and accordingly updating the usage status indicator of the specific data record.

Abstract: A badge holding system, a holder for a user identification badge and an associated method are provided in order to provide an alert in response to the identification of one or more objects proximate the holder of the badge holding system. In relation to a holder, the holder includes a housing to receive and hold the user identification badge and a controller carried by the housing. The holder also includes a proximity identification system carried by the housing to identify one or more objects proximate the holder. The proximity identification system also provides information to the controller regarding the one or more objects that have been identified. The holder further includes an alerting output device carried by the housing and responsive to the controller. The alerting output device provides an alert in response to identification of one or more objects proximate the holder.

Abstract: An apparatus comprising: a drive carrier assembly (DCA) including; an energy storage device having at least a portion thereof encased by a housing; and a printed circuit assembly to detect a power failure of a host computing device, wherein the printed circuit assembly has a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Abstract: Compressing data in dependence upon characteristics of a storage system, including: receiving an amount of processing resources available in the storage system; receiving an amount of space available in the storage system; and selecting, in dependence upon the priority for conserving the amount of processing resources and the amount of space, a data compression algorithm to utilize to compress the data.

Abstract: A host port is enabled for security. In response to a determination by the host port that authentication or security association negotiation with a storage port cannot be completed successfully, the host port determines whether an audit mode indicator has been enabled in a login response from the storage port. The host port preserves input/output (I/O) access to the storage port based on determining whether the audit mode indicator has been enabled in the login response from the storage port.

Abstract: In some examples, a trust controller generates a first value and send the first value to a target controller of a subsystem, and generates a first verification value based on the first value and a known good code image for the target controller. The trust controller receives a second verification value from the target controller, the second verification value based on the first value and a code image to be executed at the target controller. The trust controller determines whether the code image to be executed at the target controller is compromised based on the first verification value and the second verification value.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.

Abstract: Techniques a provided for performing multi-system operations in which changes are asynchronously committed in multiple systems. Metadata about the multi-system operation is injected into the commit logs of one system involved in a multi-system operation. An event stream is generated based on the commit logs of the one system, and is used to drive the operations that one or more other systems need to perform as part of the multi-system operation. A reconciliation system reads the logs of all systems involved in the multi-system operation and determines whether the multi-system operation completed successfully. Techniques are also provided for using machine learning to generate models of normal execution of different types of operations, detect anomalies, pre-emptively send expectation messages, and automatically suggest and/or apply fixes.

Abstract: A storage device includes a non-volatile memory including a plurality of memory blocks and a storage controller configured to control a read operation of the non-volatile memory. The storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and power-on time information indicating a power-on time point at which the storage device is powered on, when the storage device is switched from a power-off state to a power-on state. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.

Abstract: A device and method dynamically optimize processing of a storage command within a storage system. The device and method execute a rule based on predetermined criteria and internal operation parameters of the storage system. An extended application program interface within the storage system provides internal operation parameters for use in execution of the rule. Based on execution of the rule, the storage system controls processing of the storage command.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: In some implementations, a print device may possess a processor, print device memory, and a print queue manager. The print queue manager is to add a print job to a print queue having a plurality of print jobs to be printed. The print job corresponds to a print request received from a user for printing a digital document. The print queue manager further determines occurrence of a first trigger event for creating a print job backup. The first trigger event includes a print job deferment input. The print queue manager may further obtain print data corresponding to an unprocessed print job identified for print job backup based on the occurrence of the first trigger event and save the print data corresponding to the identified unprocessed print job in the print device memory to create the print job backup.

Abstract: A diagnostic apparatus includes a first acquiring unit that acquires sound information, a second acquiring unit that acquires operation information indicating a component in operation among a plurality of components of an analysis target apparatus, and a display unit that, when the acquired sound information is reproduced, displays operating states of the plurality of components at the time point when the reproduced sound is acquired, using the operation information.

Abstract: A power storage adapter may use a method for power delivery based on temperature and other factors. In particular, when electrical power is being supplied to a portable information handling system, a temperature of the power storage adapter may increase. Power storage adapter may reduce the electrical power being supplied to the portable information handling system based on the temperature to prevent the power storage adapter from potentially overheating.

Abstract: A system and method for seamlessly and automatically handling outdated resources in a cloud and/or performing a multiple-version upgrade within the cloud with little visibility of interim operations to end users are presented. Mechanisms ensure that outdated resources do not communicate with the rest of the cloud (for example, via distributed data models and Application Programming Interfaces (APIs) before they are upgraded to a target software level. A multiple-version upgrade is implemented in the cloud by a single upgrade operation, by which internal paths for upgrading through various interim versions of software are concealed from end users of the cloud.

Abstract: A mechanism is provided for improving error data collection in a storage network component. Each time an associated error code generated by a device coupled to the storage network component occurs, each error counter in a set of error counters associated with the error code generated by the device in the storage network component is incremented and the error is legged in an error log area associated with the device in the storage network component. Responsive to one or more clip levels in a set of clip levels being met, a notification associated with the one or more clip levels that are met is triggered thereby causing the error associated with the device to be addressed. The set of clip levels is associated with the error log area and each error counter in the set of error counters associated with the error code generated by the device.

Abstract: Systems and methods for agentless remediation and recovery. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a Central Processing Unit (CPU); a Basic Input/Output System (BIOS) coupled to the CPU; a logic controller coupled to the CPU; and a memory coupled to the logic controller, the memory having program instructions stored thereon that, upon execution by the logic controller, cause the IHS to: during a first stage, check an operational state of a plurality of hardware components within the IHS in the absence of any involvement by the CPU or the BIOS; and during a second stage following the first stage, identify a failed hardware component amongst the plurality of hardware components in the absence of any involvement by the CPU or the BIOS.