Safe Shutdown Patents (Class 714/24)
  • Patent number: 9015535
    Abstract: An information processing apparatus that executes an operating system, the apparatus including a panic process unit configured to stop the operating system when the operating system has detected an error, a mapping process unit configured to assign, to the operating system stopped by the panic process unit, a second memory area which is other than a first memory area being used by a kernel of the operating system before stop or by a hypervisor that controls the operating system before stop of the operating system, a reactivation process unit configured to reactivate the operating system by using the second memory area as a usage area, and a memory dump process unit configured to read data in the first memory area, and to write the data to a dump file after the operating system is reactivated.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kondou, Kenji Okano
  • Publication number: 20150095702
    Abstract: Various techniques for managing a system reset of a computing system to maintain error data are described herein. In one example, a computing system configured for managing a system reset to maintain error data comprises a memory buffer device to receive a transaction from a system processor and to notify the system processor of an error in performing the transaction to volatile memory. In some examples, the system processor is configured to initiate a system reset of the computing system in response to the error, the system reset comprising a reset of the memory buffer device. Furthermore, the computing system includes an integrated circuit to block the reset of the memory buffer device to maintain error data in the volatile memory.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventor: James Woodward
  • Patent number: 8990630
    Abstract: A server having a plurality of system boards, comprising: a panic processing unit configured to stop (panic) the server; a system board information storage unit configured to store information to identify a system board having a memory used by a kernel; a system board detaching processing unit configured to detach the system board having the memory used by the kernel before server stoppage; and a reboot processing unit configured to reboot the server using system boards other than the separated system board among the plurality of system boards, after detaching the system board having the memory used by the kernel.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kondo, Ryo Tabei, Kenji Gotsubo
  • Patent number: 8954801
    Abstract: Disclosed is a microcomputer such that even when a program cannot be executed in a CPU of the microcomputer due to an external noise, an unstable power-supply voltage, and other causes, and an fatal error such as runaway occurs, returning to the original state is possible within an extremely short time while preferably avoiding initialization of the entire system. During execution of normal software processing, an interrupt signal and a reset signal are output at an arbitrary time, and if it is determined that a CPU of a microcomputer gets into a runaway state, data which has been stored in a RAM as recovery information is read out, and the CPU is recovered to the state before the runaway. Because such recovery from a fatal error occurs within a short time, software which is being executed can continue its processing as if the fatal error had not occurred.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: February 10, 2015
    Assignee: L E Tech Co., Ltd.
    Inventor: Isao Tatsuno
  • Patent number: 8954800
    Abstract: Systems, methods, and machine-readable media for initiating a recovery mode to execute a recovery mode procedure is discussed. The system may include a main processor, an embedded controller, timer circuitry, and recovery circuitry. The recovery circuitry may be configured to receive an indication to execute a recovery mode procedure and, in response to receiving the indication to execute the recovery mode procedure, to trigger a first time period and a second time period. The timer circuitry may be configured to shut off the embedded controller for the first time period, wherein when the first time period expires, the embedded controller is further configured to boot from embedded controller recovery code and shut off the main processor for the second time period, wherein when the second time period expires, the main processor may be configured to boot from main processor recovery code and execute the recovery mode procedure.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: February 10, 2015
    Assignee: Google Inc.
    Inventors: Randall R. Spangler, Christopher Thomas Lyon
  • Patent number: 8954798
    Abstract: Embodiments of the present invention provide backup and restoration functions for a storage device of a PCI-Express (PCI-e) type that support a low-speed data processing speed for a host. Specifically, embodiments of this invention provide backup and restoration functions for one or more (i.e., a set of) semiconductor storage devices (SSDs). In general, the present invention provides an alarm unit and a secondary power supply coupled to a backup controller. The backup controller is coupled to a backup storage device. When a primary power supply is deactivated (e.g., fails), an alarm unit and the secondary power supply is activated. In response to this activation, the backup controller will backup any data stored on any SSDs of the storage system (as well as any data stored in main memory of the storage system or in main memory of any host server connected thereto).
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: February 10, 2015
    Assignee: Taejin Info Tech Co., Ltd.
    Inventor: Byungcheol Cho
  • Patent number: 8947813
    Abstract: Approaches for an emergency power off (EPO) power island, for saving critical data to non-volatile memory in the event of an EPO condition, for use in a hard-disk drive (HDD) storage device. The EPO power island includes a controller for detecting an EPO condition. A voltage regulator supplies power from spindle motor back EMF only to the EPO power island and to the non-volatile memory. Thus, the remainder of the hard drive controller (HDC) is isolated from the EPO power island so that it will not corrupt the data as the HDC's power supply is decaying. Using the power provided by the voltage regulator, the EPO power island transfers critical data from a memory internal to the island to a non-volatile memory external to the island, such as to a flash memory chip.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 3, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Sridhar Chatradhi, Rajesh Koul, Ryan Matthew Schulz, Anthony Edwin Welter
  • Patent number: 8924785
    Abstract: A method includes, in a host that stores data in a storage device, detecting an event that is indicative, statistically and not deterministically, of an imminent power shutdown in the host. A notification is sent to the storage device responsively to the detected event, so as to cause the storage device to initiate preparatory action for the imminent power shutdown.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Avraham Poza Meir, Shai Ojalvo, Moshe Neerman
  • Publication number: 20140359356
    Abstract: A storage unit stores information indicating the priority level of each of a plurality of virtual machines. When causing the plurality of virtual machines to perform their shutdown processes in parallel, a control unit selects a first virtual machine from the plurality of virtual machines with reference to the storage unit. In addition, the control unit selects a second virtual machine from virtual machines with lower priority level than the first virtual machine with reference to the storage unit. The control unit then reduces the amount of resources allocated to the selected second virtual machine and increases the amount of resources allocated to the first virtual machine using resources equivalent to the reduced amount of resources.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Inventor: Shigeto AOKI
  • Publication number: 20140344620
    Abstract: The present invention relates to the field of computers and communications, and discloses a shutdown method, a startup method, and a communication terminal. The startup method includes: receiving a startup signal, where the startup signal is used to trigger a terminal to perform a startup; supplying power to components of the terminal; starting the terminal according to a first startup mode; and if the startup according to the first startup mode fails, performing a startup according to a second startup mode. The technical solution is applied to help to increase the startup speed when the terminal is powered on and started.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 20, 2014
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Tao MA, Jingjing YU
  • Patent number: 8819368
    Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
    Type: Grant
    Filed: May 28, 2012
    Date of Patent: August 26, 2014
    Assignee: AgigA Tech Inc.
    Inventor: Ronald H Sartore
  • Patent number: 8812802
    Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
    Type: Grant
    Filed: May 28, 2012
    Date of Patent: August 19, 2014
    Assignee: AgigA Tech, Inc.
    Inventor: Ronald H Sartore
  • Patent number: 8812908
    Abstract: Techniques for providing fast, non-write-cycle-limited persistent memory within secure containers, while maintaining the security of the secure containers, are described herein. The secure containers may reside within respective computing devices (e.g., desktop computers, laptop computers, etc.) and may include both volatile storage (e.g., Random Access Memory (RAM), etc.) and non-volatile storage (NVRAM, etc.). In addition, the secure containers may couple to auxiliary power supplies that are located externally thereto and that power the secure containers at least temporarily in the event of a power failure. These auxiliary power supplies may be implemented as short-term power sources, such as capacitors, batteries, or any other suitable power supplies.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 19, 2014
    Assignee: Microsoft Corporation
    Inventors: John R. Douceur, Jacob R. Lorch
  • Patent number: 8806279
    Abstract: A booting method and an apparatus thereof for debugging in a portable terminal are provided. The method includes, when a booting event occurs, stacking a boot loader in a preset boot loader region of a Random Access Memory (RAM), and executing, and stacking an Operating System (OS) in a preset OS region of the RAM, wherein the boot loader region and the OS region of the RAM are set such that they do not overlap each other.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Jun Lee, Soo-Ho Noh, Young-Kyu Seo
  • Publication number: 20140181583
    Abstract: A method for protecting against fan failure in a server uses a storage unit and a plurality of fans in the server. The method includes the following steps. A rotation speed of each of the plurality of fans is detected. A continuous working time period of each fan is timed. The rotation speed reading and the continuous working time period reading of each fan is compared with predefined rotation speed values and predefined continuous working time periods stored in the storage unit. The results of comparisons are made. A countdown is started when any of the results of comparison falls into one of predefined failure conditions for the fans. Unless a renew or other countdown-amending signal is received, the server is counted down to zero and then shut down. A server equipped to be able to carry out the protecting method is also provided.
    Type: Application
    Filed: December 26, 2013
    Publication date: June 26, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIN-FU WANG, KUAN-HSIANG CHAO
  • Patent number: 8719632
    Abstract: A method and a storage system are provided for implementing indirection tables for persistent media or disk drives with enhanced emergency power outage (EPO) protection for the indirection data, such as shingled perpendicular magnetic recording (SMR) indirection tables. Chaining of indirection data is provided with one block pointing to another block of the indirection data stored to disk or flash memory. An EPO-safe buffer is used to store a metadata entry responsive to completing each host write command. Each metadata entry is added to a metadata block, a pointer is stored in the EPO-safe buffer to a current metadata block and a previous metadata block. For a next EPO-safe buffer update entries are removed for the previous metadata block, keeping the last two metadata pointers and last metadata block.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: May 6, 2014
    Assignee: HGST Netherlands B.V.
    Inventor: David Robison Hall
  • Patent number: 8713367
    Abstract: Embodiments of the present invention provide an apparatus and a method for recording a reboot reason of equipment. Besides a first watchdog provided for triggering a global reset of the equipment, the apparatus provided by the present invention further includes a second watchdog. The second watchdog is used to trigger a logic chip to record a value representing the reboot reason of power-down in a storage array after the equipment is powered on. Thus, reboot reason of the equipment could recorded as power-down reboot.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: April 29, 2014
    Assignee: Hangzhou H3C Technologies Co., Ltd.
    Inventors: Xiaoyong Deng, Yutian Wang
  • Patent number: 8689074
    Abstract: Decoding information using error-correcting codes includes, in one aspect, receiving transmitted information that includes original information coded using an error correction coding technique, and using at least one processor to iteratively decode the transmitted information to correct transmission errors and determine the original information. The iterative decoding includes determining that the iterative decoding has become trapped in a trapping set before a predetermined maximum number of iterations has been performed. Some embodiments allow that, in response to determining the trapping set, an exit can be performed from the iterative decoding before the predetermined maximum number of iterations has been performed.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Ying Y. Tai
  • Patent number: 8689084
    Abstract: Decoding information using error-correcting codes includes, in one aspect, receiving transmitted information that includes original information coded using an error correction coding technique, and using at least one processor to iteratively decode the transmitted information to correct transmission errors and determine the original information. The iterative decoding includes, in response to becoming trapped in a trapping set, adjusting information used in the iterative decoding and using the adjusted information to break the trapping set and continue the iterative decoding.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventor: Ying Y. Tai
  • Patent number: 8677110
    Abstract: A client terminal receives, in response to a boot command issued by a user to boot the client terminal, a first start command to start monitoring. The client terminal acquires first time information, repeatedly at certain time intervals from a basic software, and stores the first time information in a storage area. The client terminal receives a termination command to terminate the basic software. If the termination command is a command to terminate the basic software by using the basic software, the client terminal stores normal termination information in the storage area. When a second start command is received, and no normal termination information is stored in the storage area, the client terminal acquires second time information from the basic software and creates, depending on a result of comparison between the second time information and the first time information, log information relating to a termination of the basic software.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Kanako Ogasawara, Tadashi Okada
  • Patent number: 8665962
    Abstract: A method of operating a digital television decoder is disclosed. The decoder includes a memory, the memory storing onboard software, and the decoder is operable in a run mode to execute the onboard software. The method comprises: activating a power saving mode on the decoder; and upon activating the power saving mode: maintaining power to the memory; suspending execution of the onboard software; acquiring an execution context of the onboard software; updating the execution context of the onboard software to form an updated execution context; and saving the updated execution context in the memory.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: March 4, 2014
    Assignee: NDS Technologies France
    Inventors: Hassan Taleb, David Ludet, Eric Delaunay, Nicolas Beaunoir, Thierry Furet, Franck Bellanger, Laurent Chauvier, Laurent Proust, Laurent Douat
  • Patent number: 8661130
    Abstract: Server management data describes observed operating condition of a pool of spare servers. Based on a demand forecast of a specific target system, a dynamic allocation period is determined as a period during which the target system needs additional server resources to handle an expected demand. Based on the dynamic allocation period and server management data, a set of allocation candidates are nominated from the spare server pool, by eliminating therefrom spare servers which are likely to fail during the dynamic allocation period. An appropriate allocation candidate is then selected for allocation to the target system, such that the selected candidate will satisfy a specified requirement during its allocation period.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Masataka Sonoda, Satoshi Tsuchiya, Kunimasa Koike, Atsuji Sekiguchi
  • Patent number: 8650363
    Abstract: A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
    Type: Grant
    Filed: May 27, 2012
    Date of Patent: February 11, 2014
    Assignee: AgigA Tech
    Inventor: Ronald H Sartore
  • Patent number: 8635494
    Abstract: Provided is a RAID controlled storage device of a PCI-Express (PCI-e) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a disk mount coupled to a set of PCI-Express SSD memory disk units, the set of PCI-Express SSD memory disk units comprising a set of volatile semiconductor memories; a disk monitoring unit coupled to the disk mount for monitoring the set of PCI-Express memory disk units; a disk plug and play controller coupled to the disk monitoring unit and the disk mount for controlling the disk mount; a high speed host interface coupled to the disk monitoring unit and the disk mount for providing high-speed host interface capabilities; a disk controller coupled to the high speed host interface and the disk monitoring unit; and a host interface coupled to the disk controller.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: January 21, 2014
    Assignee: Taejin Info Tech Co., Ltd.
    Inventor: Byungcheol Cho
  • Patent number: 8631300
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 14, 2014
    Assignee: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zhi Kai Chen, Lei Wang, Changyou Xu
  • Publication number: 20130346797
    Abstract: In one aspect, a technique for restarting a software system on a computer platform after an unintentional software system shutdown. The technique includes, for instance, generating a core dump file on the computer platform when the software system shuts down unintentionally, restarting the software system, using a library for copying software system related data from the core dump file to the software system, and continuing execution of the software system.
    Type: Application
    Filed: April 30, 2013
    Publication date: December 26, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jakob C. Lang, Angel Nunez Mencias, Albert Schirmer, Jochen Schweflinghaus
  • Patent number: 8615681
    Abstract: Embodiments of the invention are directed to systems and methods for reducing an amount of backup power needed to provide power fail safe preservation of a data redundancy scheme such as RAID that is implemented in solid state storage devices where new write data is accumulated and written along with parity data. Because new write data cannot be guaranteed to arrive in integer multiples of stripe size, a full stripe's worth of new write data may not exist when power is lost. Various embodiments use truncated RAID stripes (fewer storage elements per stripe) to save cached write data when a power failure occurs. This approach allows the system to maintain RAID parity data protection in a power fail cache flush case even though a full stripe of write data may not exist, thereby reducing the amount of backup power needed to maintain parity protection in the event of power loss.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 24, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert L. Horn
  • Patent number: 8601316
    Abstract: A power supply system includes a power supply unit, a number of electrical loads and a sequence circuit. The power supply unit provides power for the electrical loads through the sequence circuit. When any one of the electrical loads fails the sequence circuit will record the failure, shut down and lock the power supply unit to prevent the power supply unit from powering the electrical loads.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 3, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Kai-Fu Chen, Chia-Yun Lee, Chuang-Wei Tseng
  • Patent number: 8601252
    Abstract: A restart controller for an information handling system includes a first latch and a second latch. An output of the second latch is coupled to an input of the first latch. The restart controller is configured to detect that the information handling system has been shut down responsive to a first disorderly shutdown, and in response to detecting the shut down, to set the first latch, initiate a first startup of the information handling system to enable a remote wake mechanism of a chipset of the information handling system, and determine, at the second latch, that a basic input/output system (BIOS) of the information handling system is operational. In response to determining that the BIOS is operational, The restart controller is further configured to initiate an orderly shutdown of the information handling system, and clear the first latch.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 3, 2013
    Assignee: Dell Products, LP
    Inventors: Matthew B. Mendelow, Todd W. Schlottman, Joseph N. Alperin
  • Patent number: 8595558
    Abstract: A computer turning on/off testing apparatus for turning on a computer automatically includes a control module, a switch module, and a power supply module. The control module outputs control signals and receives a turn on signal from the computer to determine whether the computer turns on successfully. The switch module receives the control signals and turns on/off the computer according to the control signals. The power supply module provides power to the control module and the switch module. The control module stores a predetermined test time. The control module records abnormal information and test times when the computer turns on/off, and outputs the control signals to turn on the computer again when the computer cannot restart. The computer is turned on and off until a turning on/off time of the computer is equal to the predetermined test time.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: November 26, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Ling-Yu Xie, Xing-Ping Xie
  • Patent number: 8589733
    Abstract: Saving the state of at least one open application on a data processing system when an event forces open applications to close includes monitoring data processing system activities to detect an event indicative of a forthcoming system shutdown action. The system shutdown action includes a command which forces closing of running applications. Responsive to detecting the event, execution of said shutdown action is suspended and the state of the at least one open application is recorded. An indication that a state of the at least one running application has been recorded for reuse is stored and, following the recording and storing steps, execution of said shutdown action is restored.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Daniela Di Domenico, Viviana Tripodi
  • Patent number: 8560890
    Abstract: The present invention is aimed to provide means and methods for recovery of an IP Multimedia Subsystem ‘IMS’ where a Home Subscriber Server ‘HSS’ holding subscriber data for subscribers of the IMS has suffered a restart. A first method of recovery is applied after detecting a HSS restart, and as receiving a registration from a given subscriber or an invitation to communicate with a given subscriber from another subscriber. A second method of recovery is applied after detecting a HSS restart, and as receiving a request from a given subscriber at a S-CSCF previously assigned for serving the given subscriber in the IMS.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: October 15, 2013
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Maria Carmen Belinchón Vergara, Juan Manuel Fernández Galmes, Germán Blanco, Santiago Muñoz Muñoz
  • Patent number: 8560867
    Abstract: A method for processing power-off suitable for a server system is provided. The server system includes a first node, a second node, and a power supply. The first and second nodes share the power supply. The method includes the following steps. A power-off process is performed by the first and second nodes respectively according to a power-off signal. An interception process is activated to intercept a completion signal generated in the power-off process, and an interrupt is triggered. The interrupt is performed by an interrupt handler, so as to detect whether the first and second nodes complete a power-off process. When the first and second nodes already complete the power-off process, the interception process is inactivated and the generated completion signal is recovered and transferred to the power supply for turning off a power.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 15, 2013
    Assignee: Inventec Corporation
    Inventors: Ying-Chih Lu, Wen-Ping Huang
  • Patent number: 8533528
    Abstract: A system comprising a plurality of subsystems and a master power sequencer. Each of the plurality of subsystems is coupled to an associated power switch and an associated slave power sequencer. The master power sequencer is coupled to each of the slave power sequencers and each of the power switches. Upon a slave power sequencer identifying a fault with its associated subsystem, the master power sequencer determines whether to provide power to any other subsystem. Further, the master power sequencer is configured to send a signal to each of the power switches indicating whether to provide power to the subsystem associated with each of the power switches.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: September 10, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: David Maciorowski
  • Patent number: 8527745
    Abstract: An I/O device includes a host interface configured to process function level reset (FLR) requests in a specified amount of time. The host interface includes a control unit and groups of configuration space registers, each group corresponding to a function. The host interface also includes application availability registers, each associated with a respective function, and which may indicate whether application hardware within the respective function is available for access by a corresponding application device driver. The I/O device also includes application hardware resources associated with a respective function. In response to receiving an FLR request of a particular function, the control unit may cause the associated application availability register to indicate that the application hardware within the particular function is not available to the driver.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 3, 2013
    Assignee: Oracle America, Inc.
    Inventors: John E. Watkins, Elisa Rodrigues
  • Patent number: 8522058
    Abstract: A computer system with power source control and a power source control method are presented. The computer system at least includes a first storage unit and a second storage unit, and the first storage unit stores a system program required by the computer system in basic operation. A switch is disposed on a power supply path between a power supply module and the second storage unit, such that the power supply module provides an electric power for the second storage unit to operate through the switch. When the second storage unit is in an idle state, the switch is used to cut off the power supply to the second storage unit, so as to effectively reduce the power consumption of the computer system.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: August 27, 2013
    Assignee: MSI Computer (SHENZHEN) Co., Ltd.
    Inventors: Chen-Yu Chang, Chun-Chieh Chien, Wei Hao Chen, Ruei-Chang Hsu, Tsung-Hai Hsu
  • Patent number: 8510593
    Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: August 13, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Noriaki Adachi
  • Patent number: 8499194
    Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 30, 2013
    Assignee: Dell Products L.P.
    Inventors: Gary Verdun, William F. Sauber
  • Patent number: 8495423
    Abstract: A Flash-based memory system comprises a plurality of Flash memory devices, a Flash controller communicating independently with each Flash memory device to perform memory operations, a power circuit providing power the Flash memory devices, and a CPU configured to perform a controlled powering down procedure upon detecting a power failure. In some embodiments, the Flash-based memory system includes a backup power source having a charge storage device and charging circuitry, the CPU configured to perform one or more test procedures on the charge storage device to provide an indication of a charge storage capacity of the charge storage device. A plurality of Flash-based memory systems may be mounted on a Flash-based memory card, and multiple such Flash-based memory cards may be combined into a Flash-based memory module. A number of Flash-based memory modules may then be removably mounted in a rack-mountable housing to form unitary Flash-based memory unit.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Holloway H. Frost, Don D. Davis, Adrian P. Glover, Lance W. Shelton
  • Patent number: 8495422
    Abstract: Described herein are a method, system, and computer readable medium for resetting a subsystem of a communication device. The method involves utilizing a subsystem error handler to generate a reset request signal indicating the subsystem has experienced an exception; distributing to a software component, residing externally to the subsystem, a status message indicative of a current state of the subsystem; performing a reset of the subsystem in response to the reset request signal; and rebooting the subsystem. When the subsystem can be reset without performing a system wide reset of the communication device, communication device downtime is reduced, which facilitates a positive user experience.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: July 23, 2013
    Assignee: Research In Motion Limited
    Inventors: Evgeny Mezhibovsky, Joseph Tu-Long Deu-Ngoc, Alan K. C. Sung, Jeffrey P. Laver, Anthony W. Tod
  • Patent number: 8489058
    Abstract: A receiver includes a memory, processing circuitry, and a memory protection unit. The processing circuitry is coupled to the memory, and has an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency. The processing circuitry includes one or more independently powered components adapted to write data to the memory. The memory protection unit is coupled to the memory, and monitors a power supply voltage level corresponding to each independently powered component and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Donald A. Kerth, Brian D. Green, Augusto M. Marques
  • Patent number: 8473784
    Abstract: A storage apparatus includes a backup processing unit that stores data stored in a first memory into a second memory as backup data upon occurrence of a power failure, a restore processing unit that upon recovery from the power failure restores the backup data backed up in the second memory to the first memory and erases the backup data, and an erasure processing termination unit that terminates the erasure processing upon a power failure occurring during erasure processing for erasing the backup data stored in the second memory, and a re-backup processing unit that re-backs up data in the first memory corresponding to the backup data erased from the second memory before the erasure processing is terminated by the erasure processing termination unit to a location in the second memory subsequent to a last location that contains the backup data which has not been erased.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 25, 2013
    Assignee: Fujitsu Limited
    Inventors: Yuji Hanaoka, Terumasa Haneda, Atsushi Uchida, Yoko Kawano, Emi Narita
  • Patent number: 8464099
    Abstract: A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: June 11, 2013
    Assignee: Dell Products L.P.
    Inventors: Gary Verdun, William F. Sauber
  • Patent number: 8441661
    Abstract: An image processing apparatus includes a platform and plugins installed in the platform to cause devices to perform functions, wherein the platform includes a power control unit to control supply of power to the devices and a first power control interface to transmit to the plugins an advanced notice of shutdown, wherein each of the plugins includes a second power control interface to receive the advanced notice of shutdown and a power processing control unit to make a preparation for shutdown in response to the advanced notice of shutdown received through the second power control interface, and to send information about the preparation to the power control unit through the second power control interface, wherein the power control unit controls supply of power to at least one of the devices based on the information about the preparation received from at least one of the plugins.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 14, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Rie Nakamura, Yoshifumi Kawai, Masateru Kumagai, Shinsuke Yanazume
  • Patent number: 8433941
    Abstract: A system and method for information preservation on a portable electronic device is disclosed. A signal indicating an energy capacity threshold remaining in the battery of a hand held device may be generated. Then, responsive to such a signal, information may be copied from a volatile memory into a non-volatile memory. The non-volatile memory may be configured to provide instructions for direct execution by a processor, or the non-volatile storage may be attached via an expansion interface. The non-volatile memory may be a removable card. The copy function is typically done in low power modes. Alternatively, the information is only copied provided sufficient battery capacity remains to perform the copy function.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: April 30, 2013
    Assignee: Hewlett-Packard Deveolpment Company, L.P.
    Inventor: Yoon Kean Wong
  • Patent number: 8429674
    Abstract: Methods, program products, and systems of maintaining data states upon forced exit are disclosed. In one aspect, an application program executing on the mobile device can maintain a connection to a remote data store and retrieve and cache data from the data store. When the mobile device receives an event that forces the application program to terminate, the mobile device can provide a time window in which the mobile device can perform various state preservation actions. During the time window, the mobile device can store data states, including states of the connection and states of the cached data. When the application program is re-launched, the mobile device can use the stored data states to restore a connection and a displayed view.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: April 23, 2013
    Assignee: Apple Inc.
    Inventors: Clay Maeckel, Christopher Crim
  • Patent number: 8423724
    Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: April 16, 2013
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Kelvin Marino, Michael Rubino, Mike H. Amidi
  • Patent number: 8423832
    Abstract: A system for preventing processor errors in accordance with one exemplary embodiment of the present disclosure has a processor core, a patch, and a controller. The patch configures the processor core to detect occurrences of an event indicative of an imminent error in the processor core. The controller is configured to adjust, in response to a detection of an occurrence of the event by the processor core, a clock signal or a power signal provided to the processor core such that the imminent error is prevented.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 16, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reid J. Riedlinger, Douglas John Cutter, Rich McGowen, II
  • Patent number: 8397103
    Abstract: A method for detecting an improper removal of the electronic equipment. In the method, having received a command from a higher-level device, the electronic equipment (card reader) executes processing operations in accordance with the command. The electronic equipment includes a first RAM for saving electronic information including the confidential data, a detection means (such as a switching circuit) for detecting the improper removal of the electronic equipment, a power supply control IC for shutting off a power supply to the RAM in accordance with a signal coming from the detection means, and a second RAM being separate from and independent of the first RAM. Data saved in the RAM is not deleted even if the power supply is shut off by the power supply control IC. Then, the detection means is activated after the confidential data saved in the first RAM is copied to the second RAM.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: March 12, 2013
    Assignee: Nidec Sankyo Corporation
    Inventor: Tsutomu Baba
  • Patent number: 8392695
    Abstract: Microprocessor-based devices may experience crashes due to failures in software, hardware, or a combination thereof. Details about a crash may provide valuable information for determining cause of the crash. Devices may save crash information in volatile memory, place the volatile memory into a self-refresh mode, power cycle the remainder of the device, reboot, and retrieve the crash information. Other information to be persisted across a power cycle may also be saved to volatile memory in this fashion as well.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: March 5, 2013
    Inventors: Manish Lachwani, David Berbessou