Safe Shutdown Patents (Class 714/24)
  • Patent number: 7774650
    Abstract: A method of providing a power failure warning in a storage system includes partitioning early power off warning (EPOW) control logic of a storage enclosure to be symmetric with a power distribution network power domain. A power failure warning system for a storage system having a plurality of storage enclosures includes a power system control module coupled to a power supply for control and management of input power to the storage system. An output stage of the power supply is dedicated to a first virtual storage enclosure within one of the plurality of storage enclosures.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: John C. Elliott, Robert A. Kubo, Gregg S. Lucas
  • Publication number: 20100192012
    Abstract: An apparatus and method for detecting a defect in a multi-core processor in a system is provided. The apparatus comprises a processor and an operating layer. The processor includes a plurality of cores capable of executing instructions to enable the system to function in a normal operating mode. The operating layer is configured to select at least one first target core from the plurality of cores in the normal operating mode and to test the at least one first target core for a defect while at least one remaining core from the plurality of cores is configured to execute the instructions to enable the system to function in the normal operating mode.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventor: Ishwardutt Parulkar
  • Patent number: 7765392
    Abstract: A programmable processor calculates a hash value of a memory region, then monitors program operation to detect a security monitoring system initialization. The hash value is added to extend a security measurement sequence if the security monitoring system initialization clears a security state. Processors that implement similar methods, and systems using such processors, are also described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventors: Antonio S. Cheng, Kirk D. Brannock
  • Patent number: 7765431
    Abstract: Systems and articles of manufacture for preserving error data on a computing platform that lacks non-volatile storage (e.g., a “diskless” platform) are provided. In response to detecting a platform error (e.g., automatically by hardware, software, or manually by a user when a wait or loop condition is suspected), platform error data may be gathered and temporarily stored in volatile storage accessible on the platform. In order to preserve the platform error data in the event power is lost after the error, the platform error data is transferred to a target system with access to non-volatile storage. Once the target system indicates the platform error data has been stored in non-volatile storage, the volatile storage used to temporarily store the platform error data may be freed-up.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Salim Ahmed Agha, Brent Robert Tiefenthaler
  • Publication number: 20100185898
    Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.
    Type: Application
    Filed: January 19, 2009
    Publication date: July 22, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ping T. Chan, Paul M. Gioquindo, Ying-Yeung Li, Bruce H. Ratcliff, Stephen R. Valley, Mooheng Zee
  • Patent number: 7752498
    Abstract: An interface controller initializing method for an information processing device equipped with multiple interfaces of the same type comprises the steps of: detecting control of an interface executed by a first control unit; detecting an end of the control of the interface by the first control unit executed according to instructions regarding the control of the interfaces issued by a second control unit; detecting abnormality regarding the control of an interface by the first control unit; allowing a user to input an initialization instruction for initialization of the first control unit; and executing the initialization of the first control unit on condition that the abnormality regarding the control of an interface by the first control unit has been detected, the initialization instruction has been inputted, and the end of the control of at least one of the other interfaces by the first control unit has been detected.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: July 6, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Tomoyasu Yabuki
  • Publication number: 20100169711
    Abstract: A method for safely removing an external image processing device for a computer system is disclosed. The computer system is operated in a power-on mode. The method includes receiving a removing command indicating to remove the external image processing device from the computer system, asking a BIOS of the computer system to response a management message corresponding to the removing command according to the removing command, and informing an operating system of the computer system to safely remove the external image processing device according to the management message.
    Type: Application
    Filed: November 18, 2009
    Publication date: July 1, 2010
    Inventor: Yung-Yen Chang
  • Publication number: 20100169240
    Abstract: Systems and methods for providing funds recovery for mailing machines including integrated circuits such as those used in postal security devices are described, and in certain configurations, systems and methods for recovering data such as postal funds records from a partially disabled single integrated circuit in a postal security device are described.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Robert J. Tolmie, JR., Douglas A. Clark, Mark A. Scribe
  • Patent number: 7747900
    Abstract: Mechanisms for thresholding system power loss notifications in a data processing system are provided. Power loss detection modules are provided in a data processing system having one or more data processing devices, such as blades in an IBM BladeCenter® chassis. The power loss detection modules detect the type of infrastructure of the data processing system, a position of a corresponding data processing device within the data processing system, and a capability of the data processing system to provide power during a power loss scenario. The detection module detects various inputs identifying these types of data processing system and power system characteristics and provides logic for defining a set of behaviors during a power loss scenario, e.g., behaviors for sending system notifications of imminent power loss. The detection of the various inputs and the defining of a set of behaviors may be performed statically and/or dynamically.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Charles Elliott, Robert Akira Kubo, Gregg Steven Lucas
  • Patent number: 7716526
    Abstract: An information processing apparatus carrying out hardware diagnosis processing by means of initializing processing of each part of hardware when power supply in the apparatus is started, has a power-off initializing processing part carrying out the hardware diagnosis processing when the power supply in the apparatus is cut off; and a power-off timing control part controlling timing of cutting off the power supply in the apparatus in such a manner that the power supply in the apparatus is carried out after the hardware diagnosis processing and trouble reporting processing carried out by said power-off initializing processing part are finished.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: May 11, 2010
    Assignee: Fujitsu Limited
    Inventor: Yoichi Tanimura
  • Patent number: 7716525
    Abstract: A method of providing assured message delivery with low latency and high message throughput, in which a message is stored in non-volatile, low latency memory with associated destination list and other meta data. The message is only removed from this low-latency non-volatile storage when an acknowledgement has been received from each destination indicating that the message has been successfully received, or if the message is in such memory for a period exceeding a time threshold or if memory resources are running low, the message and associated destination list and other meta data is migrated to other persistent storage. The data storage engine can also be used for other high throughput applications.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: May 11, 2010
    Assignee: Solace Systems, Inc.
    Inventors: Steven Buchko, Paul Kondrat, Shawn McAllister, Jonathan Bosloy
  • Publication number: 20100083044
    Abstract: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for resume function on a main memory for each user. When a power source is again turned on, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. The work preservation areas can be provided on a file server apparatus in a network not needing battery back-up. When the information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each user.
    Type: Application
    Filed: December 2, 2009
    Publication date: April 1, 2010
    Inventors: Hiromichi ITOH, Keiichi Nakane, Naomichi Nonaka, Yoshinori Watanabe
  • Patent number: 7685466
    Abstract: A system is provided with a basic input/output system (BIOS) with the ability to intervene, when a suspend process is initiated in response to an AC failure condition to place the system in a suspended to memory state, to initiate a number of data transfer operations to save a persistent copy of an operational state of the system. The BIOS is further equipped to check one or more times whether the data transfer operations are completed, and causing a processor of the system to operate in a reduced power consumption mode at least one time period while the BIOS is not performing the checking.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Robert A. Dunstan, Larry D. Selseth, Dan H. Nowlin
  • Patent number: 7684447
    Abstract: A method and apparatus for sequencing determines possible next states for respective possible previous states based upon resources, selects one of the possible next states as an actual next state based upon an actual previous state, and communicates the actual next state as the actual previous state.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: March 23, 2010
    Assignee: Agilent Technologies, Inc.
    Inventors: Michael Rytting, Glenn Wood
  • Publication number: 20100064124
    Abstract: A digital power controller (DPC, 1) controls an SMPC power stage (2). The DPC (1) interfaces with the SMPC power stage (2), and it has a system-on-a-chip (SoC) architecture including a digital signal processor (DSP, 5) for real-time control of SMPC outputs (such as output voltage) and a RISC processor (CPU, 6). An ADC (7) receives sense signals and routes them to the DSP (5), and a DPWM circuit (8) drives the SMPC. Communication with the CPU (6) is via a bus (10). The CPU (6) features include fault management and data transfers to the DSP co-processors and other peripheral blocks.
    Type: Application
    Filed: November 15, 2007
    Publication date: March 11, 2010
    Inventors: Karl Rinne, Eamon O'Malley
  • Patent number: 7661029
    Abstract: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for resume function on a main memory for each user. When a power source is again turned on, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. The work preservation areas can be provided on a file server apparatus in a network not needing battery back-up. When the information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each user.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiromichi Itoh, Keiichi Nakane, Naomichi Nonaka, Yoshinori Watanabe
  • Publication number: 20090327808
    Abstract: An image forming apparatus includes an error detection unit, a determination unit, an output unit, and a power source control unit. The error detection unit detects an occurrence of an error in printing operation. The determination unit determines whether or not to perform power-off operation based on a detection result of the error occurrence detected by the error detection unit. The output unit outputs an error content of the error where the determination unit determines to perform the power-off operation.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 31, 2009
    Applicant: OKI DATA CORPORATION
    Inventor: Kazuhiko TAKIZAWA
  • Patent number: 7640455
    Abstract: An apparatus for forcing outputs of a digital controller of a switching power converter to a safe state during shutdown of the switching power converter is described. The apparatus includes a multiplexer providing an output signal of the digital controller and having a first input of the multiplexer connected to receive a switching control signal control signal from the digital controller. The multiplexer also has a plurality of inputs from control registers providing programmed safe state values. The multiplexer connects one of the first input or the inputs from the plurality of control registers to the output of the multiplexer responsive to a multiplexer control signal. Control logic generates the multiplexer control signal responsive to at least one of an end of frame interrupt, an over current interrupt, an enable interrupt or a software bypass signal.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 29, 2009
    Assignee: Silicon Laboratories Inc.
    Inventors: Ka Y. Leung, Kafai Leung, Donald E. Alfano
  • Patent number: 7636606
    Abstract: The present invention relates to a method for process control, wherein at least one process device to be controlled is controlled by at least one process module and at least one safety module in that process signals of the process module not relevant to safety and safety signals of the safety module relating to process safety are logically linked to one another and at least one local safety signal of a local safety sensor is supplied directly to at least one control output of a local control unit associated with the process device while bypassing this logical linking operation in order to effect a fast change in state at the process device to be controlled which is connected to the control output, wherein the fast switching path includes a fast switching function with which the result of the logical linking operation and the local safety signal are evaluated together and wherein a fast change in state at the process device to be controlled effected via the fast changing path is changed again, and is in partic
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: December 22, 2009
    Assignee: Sick AG
    Inventors: Franz Dold, Irina Hippenmeyer
  • Patent number: 7634688
    Abstract: A system and method for automatically saving the contents of volatile memory in a data processing device on power failure. A secondary power supply is provided, which upon failure of the primary power supply supplies power long enough for all modified information stored in volatile memory to be written to a non-volatile memory device such as NAND flash in an AutoSave procedure. In the preferred embodiment modified sectors in volatile memory are flagged, and only modified sectors with a directory list are written to non-volatile memory during the AutoSave procedure.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: December 15, 2009
    Assignee: Research In Motion Limited
    Inventors: Richard C. Madter, Karin Alicia Werder, Wei Yao Huang
  • Publication number: 20090240980
    Abstract: An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.
    Type: Application
    Filed: September 13, 2007
    Publication date: September 24, 2009
    Inventors: Hiroaki Inoue, Masamichi Takagi, Masayuki Mizuno
  • Patent number: 7593324
    Abstract: A port shutdown protocol coordinates among various components involved in the process of administratively bringing down a link at both ends of a link connecting two switches. Execution of the protocol avoids or reduces frame drops and/or reordering. In this protocol, peer switches perform various actions when bringing down an ISL in a synchronized manner. In one implementation, this protocol uses the Exchange Peer Protocol (EPP) as the underlying transport to carry the port shutdown protocol frames.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: September 22, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Praveen Jain, Ranganathan Rajagopalan, Ramsundar Janakiraman, Shashank Gupta, Sachin Jain
  • Patent number: 7590890
    Abstract: A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being declared operational by the power controller. When powering down the equipment, the DLY_PWRGD signal is first deasserted and power is decoupled from the card or other equipment. The PWRGD signal is then deasserted after a short delay. This short delay allows circuitry within the card to be properly shut down by, for example, carrying out a shutdown routine, using stored charge in the card to temporarily power the card. A state machine is used to carry out the four-state power up and power down sequence.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: September 15, 2009
    Assignee: Micrel, Inc.
    Inventors: William Andrew Burkland, Adolfo A. Garcia
  • Publication number: 20090217092
    Abstract: A method for controlling a computer system having at least two execution units and one comparator unit, which system is operated in the lock-step mode and in which the results of the at least two execution units are compared, wherein when or after an error is detected by the comparator unit, an error-detection mechanism is processed on at least one execution unit for this execution unit.
    Type: Application
    Filed: July 26, 2006
    Publication date: August 27, 2009
    Inventors: Reinhard Weiberle, Bernd Mueller, Rainer Gmehlich
  • Patent number: 7581137
    Abstract: A storage apparatus according to the present invention can store information related to a power supply abnormality after shutting down the principal functions of a data processing board when a power supply abnormality occurs in a data processing board. A power supply controller of a data processing board mounted in the storage apparatus monitors the operational status of DC/DC power supplies mounted to the data processing board, on the basis of detection signals from a voltage detection circuit. When a power supply abnormality is detected, the power supply controller immediately shuts down the operation of all the DC/DC power supplies. Shutting down the DC/DC power supplies also shuts down the principal functionality of the data processing board. Then, after storing information related to the power supply abnormality in memory, the power supply controller shuts down the auxiliary power supply.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 25, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Okada, Hidehiro Nagaya, Shin Nakamura
  • Patent number: 7580773
    Abstract: A handling robot system, including a table having a placement surface for placing articles; an article dispersing mechanism for dispersing the articles placed on the placement surface of the table across the placement surface; a vision sensor for detecting each of the articles dispersed on the placement surface of the table; and a robot operating, based on article detection data from the vision sensor, to hold the articles one by one.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: August 25, 2009
    Assignee: Fanuc Ltd
    Inventors: Kazuo Hariki, Masaru Oda
  • Patent number: 7552148
    Abstract: Aspects of the subject matter described herein relate to shutdown recovery for resource replication systems. In aspects, a mechanism is described in which a machine having replicated data thereon can recover from a dirty shutdown. First, the machine determines whether a dirty shutdown has occurred. If so, the machine automatically performs shutdown recovery by causing resource metadata stored by the machine to be consistent with resource data stored by the machine. This may involve fixing the resource metadata for updates to the resource data that were not flushed to disk or may involve deleting the resource metadata and restoring it from another machine replicating the data.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 23, 2009
    Assignee: Microsoft Corporation
    Inventors: Huisheng Liu, Guhan Suriyanarayanan, Nikolaj S. Bjorner, Dan Teodosiu
  • Patent number: 7549097
    Abstract: Functional circuits such as a processor, an SRAM, a DRAM and a flash-EEPROM are mounted on a semiconductor chip. Of these functional circuits, for example, the flash-EEPROM which fluctuates a potential of the semiconductor chip is separated from the other circuits by means of a separating region provided in the semiconductor chip. In addition, the separating region is put in contact with the entire side faces of the semiconductor chip.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: June 16, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomomi Momohara
  • Patent number: 7543170
    Abstract: A system for monitoring and controlling the safety system of equipment, which is used to insure personnel safety and cause the system to “fail safe” in the event of computer or software failure, the failure of a critical piece of hardware, or the opening of any interlock indicating, for example, the unexpected entry of personnel into a dangerous area. Provides an integrated system of timed status monitoring hardware and software for use in a distributed-network computer-controlled environment. The hardware piece of this system includes a digital I/O computer add-on card, or other hardware supporting high-speed alternating state telemetry, and a custom circuit card. Such a circuit, when used within the overall control system can monitor the state of interlock switches and monitor the status of the computer control system(s). Such a safety circuit can then cause a shutdown appropriate to the failure detected.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 2, 2009
    Assignee: Novacentrix Corp.
    Inventors: Rens Ross, Steven C. McCool
  • Patent number: 7516042
    Abstract: Various technologies and techniques are disclosed for performing load tests based upon user pace. A load test application is provided. Load test settings are received from a user that includes a test mix based upon user pace. A test start interval is calculated using the text mix. A load test is performed based upon the text mix. For example, the tests are executed at a pace that is based upon the test start interval for the particular user profile that the test is contained within.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: April 7, 2009
    Assignee: Microsoft Corporation
    Inventors: Ed Glas, Bill Barnett
  • Patent number: 7506209
    Abstract: A shutoff condition monitoring method for a computer, includes the steps of: a) determining that an abnormal shutoff has occurred when the computer shuts off without passing through predetermined shutoff processing; b) counting the number of times of repetitive occurrences of the abnormal shutoff; and c) determining that predetermined recovery processing should be carried out on the computer when the number of times of repetitive occurrences of abnormal shutoff exceeds a predetermined value.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: March 17, 2009
    Assignee: Fujitsu Limited
    Inventor: Shohachi Kawata
  • Patent number: 7496790
    Abstract: A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Richard Louis Arndt, Patrick Allen Buckland, Harvey Gene Kiel, Renato John Recio, Jaya Srikrishnan
  • Patent number: 7490252
    Abstract: An abnormal power interruption internal circuitry protection method and system is proposed for use with a computer platform, such as a blade server, which is characterized by the utilization of each server module's identification code (i.e., blade ID signal) and power-good signal to judge whether each server module is subjected to an abnormal power interruption, such that in the event of the abnormal power interruption, a small amount of remnant electrical power left in the internal circuitry of the blade server can be fetched as power source to shut down the server modules through a normal shutdown procedure. This feature can help protect the internal circuitry of the server modules of the blade server from being damaged due to abnormal shutdown in the event of abnormal power interruption.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: February 10, 2009
    Assignee: Inventec Corporation
    Inventor: Sheng-Yuan Tsai
  • Patent number: 7490203
    Abstract: Provided are a method, system and program for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: February 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yu-Cheng Hsu, David Frank Mannenbach, Glenn Rowan Wightwick
  • Publication number: 20090037770
    Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Rainer Troppmann, Guiseppe Maimone
  • Patent number: 7472309
    Abstract: A method and apparatus to write a file to a nonvolatile memory is provided. The method may include writing a file to a nonvolatile memory using at least two headers and at least two file fragments and using only information stored in one header of the at least two headers to determine if the writing of the file to the nonvolatile memory was interrupted by a loss of power. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventor: Kiran Kumar G. Bangalore
  • Patent number: 7467331
    Abstract: A method for preserving error data on a computing platform that lacks non-volatile storage (e.g., a “diskless” platform) is provided. In response to detecting a platform error (e.g., automatically by hardware, software, or manually by a user when a wait or loop condition is suspected), platform error data may be gathered and temporarily stored in volatile storage accessible on the platform. In order to preserve the platform error data in the event power is lost after the error, the platform error data is transferred to a target system with access to non-volatile storage. Once the target system indicates the platform error data has been stored in non-volatile storage, the volatile storage used to temporarily store the platform error data may be freed-up.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Salim Ahmed Agha, Brent Robert Tiefenthaler
  • Patent number: 7467322
    Abstract: In a computer system having a cluster configuration, a reset command issued from each of computers to any of the other computers is transmitted to a reset control unit. A control module of the reset control unit judges whether a target of the newly inputted reset command conflicts with a target and a source of a reset command currently executed. If judging as no conflict, the newly inputted reset command is transmitted to a destination computer of the reset command, and then information of the transmitted reset command is stored as information of the reset command that is currently being executed. With this configuration, when one of the computers in which failure has occurred is reset by means of heartbeat mutual monitoring, it is possible to avoid a delay caused by a mutual reset or a repeated reset, and thereby to quickly reset the failed computer.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: December 16, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Tsunehiko Baba
  • Publication number: 20080294938
    Abstract: An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.
    Type: Application
    Filed: May 9, 2008
    Publication date: November 27, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Takao Kondo
  • Patent number: 7454656
    Abstract: According to the present invention, in cases where a CHA function and a DKA function are mounted within a single package, a battery power supply that is used during the occurrence of power supply trouble is effectively utilized so that the supply of power can be separately controlled for each function. A CHA part and DKA part are disposed in a single control package. When trouble such as a power outage is detected, the CHA part blocks access requests from the host, and initiates end processing. When the end processing of the CHA part is completed, the package internal power supply control part stops the clock supply to the CHA part. Then, when the DKA part completes destage processing, the package internal power supply control part stops the supply of power to the DKA part. The power consumption of the package is lowered in stages in accordance with the progress of the end processing.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: November 18, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Okada, Kenji Mori, Nobuyuki Minowa
  • Publication number: 20080256388
    Abstract: A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 16, 2008
    Applicant: International Business Machines Corporation
    Inventors: Gary Dean Anderson, Sheldon Ray Bailey, Wayne Allan Britson, Alongkorn Kitamorn, Michael Alan Kobler
  • Patent number: 7434224
    Abstract: Multiple different operating systems are enabled to run concurrently on the same computer. A first operating system is selected to have a relatively high priority (the realtime operating system, such as C5). At least one secondary operating system is selected to have a relatively lower priority (the general purpose operating system, such as Linux). A common program (a hardware resource dispatcher similar to a nanokernel) is arranged to switch between these operating systems under predetermined conditions and modifications are provided to the first and second operating systems to allow them to be controlled by the common program.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: October 7, 2008
    Assignee: Jaluna SA
    Inventors: Eric Lescouet, Vladimir Grouzdev
  • Publication number: 20080240741
    Abstract: An image forming apparatus according to the invention includes a cooling fan as a cooling device, an image formation processing unit, a changeover unit, a main control unit, a secondary control unit, and a power supply unit. The main control unit and the secondary control unit make an appropriate action in association with each other in the event of the occurrence of an abnormality in the cooling device. The changeover unit is configured to connect the image formation processing unit to the main image formation control unit in the main control unit in a case where power is supplied to the main control unit, and to connect the image formation processing unit to the secondary image formation control unit in the secondary control unit in a case where power supply to the main control unit is stopped by the power supply control unit in the secondary control unit.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Kazuo Sasama, Takaaki Suzuki
  • Publication number: 20080215918
    Abstract: A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a server's sub-systems and deployed applications. The SHM may make health check inquiries to server sub-systems periodically or based on external trigger events. The sub-systems perform self health checks on themselves and provide sub-system health information to requesting entities such as the SHM. Sub-systems self health updates may be based on internal events such as counters or changes in status or based on external entity requests. Corrective action may be performed upon sub-systems by the SHM depending on their health status or the health status of the server. Corrective action may also be performed by a sub-system upon itself.
    Type: Application
    Filed: April 10, 2008
    Publication date: September 4, 2008
    Applicant: BEA SYSTEMS, INC.
    Inventors: Rahul Srivastava, Eric M. Halpern
  • Patent number: 7418627
    Abstract: A high availability cluster computer system can realize exclusive control of a resource shared between computers and effect failover by resetting a currently-active system computer in case a malfunction occurs in the currently-active system computer. In case a malfunction occurs in a certain system in a cluster, another system in the cluster which has detected the malfunction issues a reset based on a priority to realize failover, in which a standby system takes over the processing of the malfunctioning system when the malfunctioning system is stopped.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 26, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Tsunehiko Baba
  • Patent number: 7412615
    Abstract: Information processing equipment is so constructed that the power consumption of a disk drive for hard disks, optical disks, or the like can be reliably and sufficiently reduced. The host CPU (120) of an information processing unit (100) forms a command for changing the power consumption mode of a HDD (200) based on the state of control on the HDD (200). The host CPU supplies the command to the HDD (200) through a media controller (106). When the HDD (200) accepts the command, it changes its power consumption mode according to the instruction from the information processing unit. Thus, the information processing unit can control the power consumption mode of the HDD (200) based on the state of control on the HDD (200).
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: August 12, 2008
    Assignee: Sony Corporation
    Inventors: Junichi Yokota, Atsuo Okamoto, Keiji Kanota, Ryogo Ito
  • Patent number: 7411314
    Abstract: A system is provided with the ability to automatically shut off a backup power source from further sourcing power for the system, when AC is absent, after the backup power source has sourced power for the system for a period of time.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: August 12, 2008
    Inventor: Robert A. Dunstan
  • Patent number: 7406624
    Abstract: A method is provided for saving system information immediately following a hardware or software failure that causes a processor to reset. After failure is imminent and before the processor allows the reset to occur, the processor is instructed to copy a fixed amount of the system stack SRAM, in addition to any processor registers that can be used to determine the reset cause, into a preserved area of SRAM. During the initialization sequence, the preserved area of SRAM is tested, but not overwritten. This allows all of the preserved SRAM data including previous stack contents and register settings at the time of the failure to be available for analysis.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: July 29, 2008
    Assignee: General Motors Corporation
    Inventors: Timothy A. Robinson, James H. Stewart
  • Patent number: 7403837
    Abstract: A portable device (1) with at least one optical output device (2) for displaying at least process data of a machine, a robot or a technical process, with at least one input device (3) for at least intervening in the operating functions of the device (1) and/or for operating the machine or robot or technical process, and having a safety switch device (12) for preventing the output of undesirable, unintended control commands for the machine, robot or technical process. The output devices (2) and input devices (3) are connected to a control device (14), which is accommodated in a housing (7) that is unbreakable as far as possible and at least one communication interface (17) is provided to an external control device disposed at a distance away. Several of the input and output devices (2, 3) are functionally combined by means of a touch-sensitive screen (4) in the form of a touch-screen (5) and the touch-sensitive screen (4) extends across substantial regions of the surface of the housing (7).
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 22, 2008
    Assignee: KEBA AG
    Inventors: Dieter Graiger, Hans-Peter Wintersteiger, Martin Danner
  • Patent number: RE41014
    Abstract: A system and method for preventing damage to media files within a digital camera comprise a power manager for detecting power failures, an interrupt handler for responsively incrementing a counter device and a removable memory driver for performing memory access operations, evaluating the counter device to determine whether a power failure has occurred during the memory access operation and for repeating the memory access operation whenever a power failure has occurred during the memory access operation.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: November 24, 2009
    Assignee: Apple Inc.
    Inventor: Eric C. Anderson