Abstract: A board adapter device includes: a first adapter structure provided with a gold finger matched with a board of a target memory module, a second adapter structure provided with a connector matched with the gold finger, and a signal transmission structure including a first and second transmission module. The first transmission module is for connecting a data signal line, a clock signal line, an address signal line, and a control signal line of the gold finger to corresponding connecting lines of the connector. The second transmission module is configured to, when receiving a power input signal, convert the power input signal into a power output signal matched with a power supply of the target memory module, and transmit the power output signal to a power signal line of the connector.

Abstract: Executable memory space is protected by receiving, from a process, a request to configure a portion of memory with a memory protection attribute that allows the process to perform at least one memory operation on the portion of the memory. Thereafter, the request is responded to with a grant, configuring the portion of memory with a different memory protection attribute than the requested memory protection attribute. The different memory protection attribute restricting the at least one memory operation from being performed by the process on the portion of the memory. In addition, it is detected when the process attempts, in accordance with the grant, the at least one memory operation at the configured portion of memory. Related systems and articles of manufacture, including computer program products, are also disclosed.

Abstract: A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory device, a control unit, a memory as a work area, a wireless communication module, and an extension register. The control unit controls the non-volatile semiconductor memory device. The extension register is provided in the memory and has a data length by which a wireless communication function of the wireless communication module can be defined. The control unit causes the non-volatile semiconductor memory device to store, as a file, an HTTP request supplied from a host, causes the extension register, based on a first command supplied from the host, to register an HTTP transmission command transmitted together with the first command, and causes the wireless communication module to transmit the HTTP request stored in the non-volatile semiconductor memory device based on the transmission command registered in the extension register.

Abstract: The present invention provides a method for read/write speed testing, comprising: obtaining a test speed of reading data from or writing data to each of a plurality of memories, the plurality of memories including a random access memory and at least one buffer memory associated with the random access memory; and determining an actual speed of reading data from or writing data to the random access memory according to the test speed of reading data from or writing data to the each memory. Embodiments of the present invention further disclose an apparatus for read/write speed testing and electronic device. With the embodiments of the present invention, the read/write speed of the random access memory can be tested more accurately.

Abstract: An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.

Abstract: In one implementation, computer executable instructions are provided to identify a group of instructions corresponding to a code block for an executable module. The instructions increment a counter associated with the code block to indicate the code block has been tested.

Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.

Abstract: A method for a server to process a transaction on remote client hardware is disclosed. A local request is generated for the transaction. A driver level message to the remote client hardware is generated. The driver level message is sent directly to the remote client hardware to process the transaction.

Abstract: A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

Abstract: A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: A method for manipulating a memory operation of a control unit program on a memory of a virtual or real electronic control unit (ECU), such as is used in vehicles, for example. The manipulation of the memory operation is accomplished by a memory manipulation program component, via which a set of manipulation functions is provided, from which at least one manipulation function is selected, so that this function, by activating the memory manipulation program component, changes a memory access initiated by the control unit program in accordance with the selected manipulation function during execution of the control unit program.

Abstract: A mechanism for virtual machine (VM)-based disk rescue is disclosed. A method of the invention includes starting a reboot process of a VM hosted on a host computing machine, controlling an invocation of a recovery media that is used by a recovery process on a disk of the VM and is located separate from the VM disk, and restarting the VM after the recovery process using the recovery media successfully completes.

Abstract: Described are computer-based methods and apparatuses, including computer program products, for system health monitoring. Backup set metadata is received, wherein the backup set metadata comprises information about backup data sets that are received by a backup storage system. One or more processes that process the backup set metadata through an emulated processing flow path are executed, wherein the one or more processes are also implemented in the backup storage system. Two or more potential processing states are determined within the emulated processing flow path. A reason code is determined for each backup set metadata entry of the backup set metadata indicative of a reason that the backup set metadata entry is in a processing state of the two or more potential processing states. A problem with the manner in which the backup set metadata is flowing through the emulated processing flow path is identified based on the reason codes.

Abstract: A telephone system comprising switching circuitry configured for coupling a call to a telephone extension coupled to the system, voice processing circuitry configured for automatically interacting with the call, a microprocessor, a first data bus connected between the microprocessor and the switching circuitry, and a second data bus connected between the microprocessor and the voice processing circuitry.

Abstract: A data receiver module receives, at a storage device simulator, a data transmission from a storage controller being tested. The data transmission includes data and metadata. The metadata is associated with the data. A signature receiver module receives a signature from the storage controller as part of the data transmission. The signature is used to distinguish the metadata from the data. A data/metadata determination module examines the data transmission and determines data from metadata using the signature. A metadata storage module stores the metadata of the data transmission on the storage device simulator in response to the data transmission including metadata. The data storage simulator includes a data storage device. A data discard module discards the data of the data transmission in response to the data transmission including data.

Abstract: A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution.

Abstract: An electronic card (4) comprising a processing unit (7), able to receive a command originating from a diagnostic module (6) and a command originating from a simulation system (3). The electronic card (4) comprises means of managing the execution priority of the command originating from the simulation system (3) relative to the command originating from the diagnostic module (6). A diagnostic system of an electronic card comprising a diagnostic module and means of managing the execution priority of the commands. A simulation method is associated with the electronic card (4). For use in particular for analysing malfunctions on electronic cards (4) incorporated in integration simulators (1).

Abstract: Systems, methods, apparatus and software can implement a flexible I/O fence mechanism framework allowing clustered computer systems to conveniently use one or more I/O fencing techniques. Various different fencing techniques can be used, and fencing mechanism can be customized.

Abstract: Various methods and systems for scoring applications are disclosed. One method involves generating a baseline measuring a parameter of a computer system. The parameter is related, directly or indirectly, to the energy consumption of the computer system. The method next involves installing and running an application on the computer system. The previously measured parameter is measured with the application running. Next, a score is calculated for the application based on the two measurements. This score indicates how green the application is.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.

Abstract: An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method.

Abstract: A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

Abstract: A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.

Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: A virtual hard disk drive includes at least one test transmission interface and a processing unit, wherein the test transmission interface is used for electrically connecting with the processing unit. The test transmission interface can electrically connect with a transmission interface under test of a computer. The processing unit includes an obtaining module and a simulation module. When an access instruction is received through the test transmission interface from the transmission interface under test of the computer, the obtaining module obtains a number of accessed blocks from the access instruction. The simulation module simulates a step of accessing a set of accessed data with the number of accessed blocks with respect to the transmission interface under test via the test transmission interface.

Abstract: A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device.

Abstract: A fault tolerant system is simulated to determine the occurrence of data loss in the fault tolerant system. A list of erasure patterns corresponding to an erasure code implemented across the devices in the system is provided and a device event is simulated. The list of erasure patterns is updated based on the device event, and the occurrence of data loss is determined based on the updated list.

Abstract: Disclosed is a method of verifying the integrity of data acquired from a device emulating a hard disk to a host computer over a data transfer pathway. A storage medium containing known data is connected to the data transfer pathway, the storage medium capable of emulating a hard disk. The known data is transferred from the storage medium to the host computer over the data transfer pathway for storage on the host computer. A characteristic of the data stored on the host computer is compared with a corresponding characteristic of said known data to determine whether data corruption has occurred during data transfer over said data transfer pathway. The characteristic could be a hash code value, such as a Message-Digest 5 (MD5) or Secure Hash Algorithm (SHA) value.

Abstract: A system and method for emulating disk drives in a storage area network, including providing a system with one or more ports for connecting to a storage area network, emulating one or more targets for each port of the system, and emulating one or more LUNs for each emulated target of the system.

Abstract: A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

Abstract: A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

Abstract: A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system.

Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

Abstract: A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted dynamically at runtime to optimize the performance of the interface.

Abstract: The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.

Abstract: A method and system for accessing audiovisual data in a computer, which has a hard disk, a hard disk controller and a device driver. The hard disk is divided into a partition region and a non-partition region. The partition region has an audiovisual table to record a location of the audiovisual data stored in the non-partition region. The non-partition region is emulated as an emulated compact disk drive. When the device driver determines to access the emulated compact disk drive, it performs a converting procedure to convert an access instruction to the compact disk drive into an access instruction to the non-partition region, and sets a command register of the hard disk controller in accordance with the instruction converted and the audiovisual table, thereby accessing the non-partition region.

Abstract: A microcomputer logic development device realizing high speed sampling RAM monitoring by connecting an existing RAM measurement device, provided with a first block providing functions corresponding to a microcomputer core, a second block having functions corresponding to microcomputer resources, a bus connecting the first and second blocks, and a RAM measurement block provided with a common memory, connected with the bus and RAM measurement device, and realizing a RAM monitor function with respect to the first block, the RAM measurement block realizing a high speed RAM monitoring operation by dividing the timing for processing between the first block and common memory and the timing for processing between the common memory and RAM measurement device.

Abstract: A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE (in-circuit emulation) to form a virtual microcontroller. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code for debugging purposes. The microcontroller residing on a test circuit includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. Software in the host device compares the content of the first memory and the content of the second memory for consistency.

Abstract: A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells.

Abstract: A test system for testing memory modules uses vertically-mounted personal computer (PC) motherboards. Many test adaptor boards that contain test sockets for testing memory modules are mounted horizontally across a test bench. Each test adaptor board connects to a motherboard that tests the memory modules in the test sockets. The motherboard is mounted below and perpendicularly to the test adaptor board. The motherboard is modified to extend the memory bus to edge contact pads along an edge of the motherboard. An edge socket on the test adaptor board mates with the edge contact pads to make electrical connection. A robotic arm inserts a memory module into the test socket, allowing the vertically-mounted motherboard to execute programs to test the memory module.

Abstract: A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.

Abstract: A method for verifying the functionality of a repair system of configurable memory that functions to replace memory that fails predetermined tests with unused memory that passes the tests. The method includes the steps of providing a matrix comprising a plurality of reconfigurable memory blocks, providing an emulation system, generating a substitute memory block for each of the reconfigurable memory blocks utilizing the emulation system computing platform, providing a memory design that incorporates the substitute memory blocks, generating files for mapping errors into the reconfigurable memory blocks and providing a control file associated with the emulation system, and operating the emulation system to emulate the memory design.

Abstract: Systems, methods and media for managing software defects by aggregating potential software defect information from a plurality of user computer systems are disclosed. Embodiments may include receiving a plurality of software state logs each from an originating user computer system, where each software state log is associated with a potential software defect of an application executing on its originating user computer system and each software state log includes software state information associated with its originating user computer system. Embodiments may also include storing the received software state logs in a defect repository and analyzing the software state information of the stored software state logs to detect patterns in the software state information. Further embodiments may include verifying that a potential software defect associated with a software state log is a defect and transmitting a verification of the software defect to the particular user computer system.

Abstract: Method and system for testing an Application Specific Integrated Circuit is provided. The system includes, a simulator that interfaces with a host computer emulation module; and a virtual interface driver (“VID”) that interfaces with the host computer emulation module and a bus interface module, wherein the VID maps plural stimulus to the simulator via the bus interface module. The method includes, loading a bus functional module in an ASIC simulator; determining configuration of devices supported by a host emulation system; and mapping configuration information to the host emulation system, wherein a virtual interface driver maps the configuration information to the host emulation system.