Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: A hardware and software co-simulation method for non-blocking cache access mechanism verification is provided. The method is applied for cache access mechanism verification. First, at least one way buffer is added into the software modeling, then the hardware and software modeling are simulated. Wherein, the hardware modeling issues a trigger event for reading request when one ‘outstanding miss’ occurs. At this moment, the software modeling stores the data of the address to be accessed into a way buffer. When the hardware modeling obtains the data from the main memory, it issues a trigger event for reading completion, and causes for writing the data from the way buffer into the data memory of the software modeling. The verification result of the software simulation is compared with the verification result of the hardware simulation.

Abstract: Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module socket, but from the reverse (solder) side of the motherboard. The adapter pins connect to the test adapter board either directly, through a connector plug, or through an intervening adapter board. The test adapter board has soldered onto it additional memory chips and buffer chips on a memory module, such as an Advanced Memory Buffer (AMB) for a fully-buffered memory module. The built-in-self-test (BIST) feature of the AMB may be used to test the memory chip under test in the chip test socket, or the processor on the motherboard may write and read the memory chip.

Abstract: Techniques are provided for expanding the functionality of live memory analysis commands to analyze a memory dump or other differing memory types. To this end, a live memory command which normally analyzes live memory is modified to invoke a virtual machine. Live memory commands, in general, have different code segments including a locate code segment which, when executed, locates a first control block in live memory. The locate code segment of the live memory command is modified to invoke a virtual machine for locating a second control block in a memory dump. When the modified code segment is executed, the second control block from a memory dump is accessed.

Abstract: A low-cost micro-controller debugging system with a ROM or RAM emulator is disclosed. The system includes a target microcontroller (MCU) and at least one ROM connected together, with a debugger unit which debugs that target MCU. A ROM/RAM emulator is connected to the target MCU and the debugger unit for emulating the ROM.

Abstract: A method of and system for troubleshooting a first computer system using a second computer system having a processor and a memory storing an electronic document including troubleshooting information and storing a set of troubleshooting commands for execution by the first computer system is described. The troubleshooting command set is related to the troubleshooting information contained in the electronic document. A method of generating an electronic document including troubleshooting information and a set of troubleshooting commands for execution by a first computer system is also described.

Abstract: A method and apparatus non-intrusive tracing. The method includes: counting selected events by multiple counters; sampling the multiple counters to retrieve multiple counter values in response to predefined triggering events; receiving additional trace information that comprises at least one program counter value, and outputting, as a trace information, at least one of the multiple counters values and the additional trace information.

Abstract: The described program controlled unit has first supply voltage connections for applying a first supply voltage to the program controlled unit and second supply voltage connections for applying a second supply voltage to the program controlled unit. The full OCDS module or a part of the OCDS module is supplied with power by the second supply voltage. The remaining components of the program controlled unit are supplied with power by the first supply voltage. This means that the entire OCDS module or part of the OCDS module can actually be supplied with power, before the time at which the remaining parts of the program controlled unit are supplied with power. A debugger supplies the OCDS module with control information that prescribes a particular state of the OCDS module.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract: A data storage system includes a plurality of disk drives for data storage. A storage server controls the reading and writing of data to the disk drives. The storage server can be tested prior to connecting the disk drives and other components of the data storage system by connecting ports of the storage server to other ports of the storage server. One of the connected ports is changed from an initiator to a target to simulate a the target state of a disk drive. The server can test itself at normal data transfer rates using the initiator-target pair just as if it was testing a normal server/disk drive connection, but without having to test the actual disk drive and without having to detect or distinguish any problems that may exist with the disk drive and its connection, or other components that may be in the loop.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by data processing system (10). One use of this additional control over the physical address (83) and over the address attributes (84) is to avoid address translation failure and unintended modification of cache (13) and memory (18) system state during debugging.

Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.

Abstract: The present invention relates to a system and method for emulating a greater range of behavior of a peripheral device connected to a host device or host computer than was available in the prior art. The emulation of a greater range of activity of the peripheral device provides an opportunity to more fully test the interaction of a host device with the emulated peripheral device. More specifically, the present invention preferably adds control data line and power data line connections to user data line connections between the host device and an intelligent emulator so that variations in control settings and power levels may be exercised in addition to manipulation of transmissions along a user data line, thereby more fully exercising host device interaction with an emulated device.

Abstract: A method and apparatus for maintaining consistent data is described. A computer implemented method comprises generating a first command for a set of network data to be executed on a local memory, executing a second command for the set of network data on a remote memory in response to generation of the first command, determining whether the second command has been executed successfully on the remote memory, executing the first command on the local memory upon determining the second command is executed successfully, and generating an error upon determining the second command is not executed successfully.

Abstract: The present invention relates to a system and method for emulating the operation of storage devices deployed in a host computer system. The inventive approach preferably involves the use of an emulator employing storage space and equipment specifically allocated for the emulation of particular storage devices associated with the host computer. Emulating storage devices preferably preserve their data through various possible power cycling operations of the emulated devices. The emulating or emulator devices may generally be disposed inside or outside of the emulator housing.

Abstract: Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis.

Abstract: A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.

Abstract: The present invention is to provide an emulator and a method of emulation for using testing a system having complex interfaces capable of stable testing can be realize under the system regulation frequency or less frequency without using the high-performance and expensive tester. The emulator comprises a content addressable memory (CAM) configured to store addresses accessed by a system to be tested, a memory unit having storage area corresponding to the entry of the CAM, configured to store data corresponding to the address stored in the CAM, and test information for emulation, a shift register configured to store data and test information from a tester and transfer the data and the test information to the CAM and the memory unit, and a state machine configured to receive a request from a system or a tester and control transferring between a system and a tester.

Abstract: A trace data compression system includes a data acquisition circuit which is configured to acquire address information for identifying an address for reading or writing operation of a microcomputer which performs predetermined processing, and data information as operand data stored in the address; an address information compression circuit which is configured to compress the address information having been acquired by the data acquisition circuit and output the address information as compressed; a data information compression circuit which is configured to compress the data information having been acquired by the data acquisition circuit and output the data information as compressed; a data output circuit which is configured to output variable length data containing the address information having been compressed and outputted by the address information compression circuit and the data information having been compressed and outputted by the data information compression circuit.

Abstract: An integrated circuit includes a debugging unit which uses a multi-master general purpose bus within the IC to perform debugging functions. The storage elements of the IC are mapped into the address space of the general purpose bus. The debugging unit can operate as a bus master and read from or write to the storage elements of the integrated circuit directly with the general purpose bus. Thus, the integrated circuit can be rapidly configured for testing and debugging. Furthermore, the debugging unit can work with a breakpoint unit on the IC to detect and analyze specific situations on the IC.

Abstract: An integrated circuit with multiple circuit cores each of which have integrated emulated circuits, and an emulation interface module, such that the integrated circuit has an on-chip debugging system. As cores other than a processor core have integrated emulation circuits, debugging of programs and operations of systems-on-a-chip becomes viable.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

Abstract: A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction register and at least one data register for supporting testing and emulating a memory subsystem with different types of physical memory in a microprocessor based system.

Abstract: The present invention provides a disk unit suitable for recording and reproducing time-series continuous data such as AV data.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. An embodiment of a processor core is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks.

Abstract: A data image management system (DIMS) that includes a local data image manager (LDIM), a remote data image manager (RDIM), and a remote persistent storage device (RPSD). The LDIM communicates with the RDIM through a direct communication link or through a communication network. The RDIM can store data on and retrieve data from the RPSD. In an environment where an LDIM has been installed in a computer having a “local” persistent storage device (LPSD), the DIMS allows for the storing of the LPSD's data image on the RPSD, with the LPSD serving as a persistent, consistent cache of the data image. The data image stored on the RPSD is referred to as the “master data image” and the data image cached on the LPSD is referred to as the “local data image” or “cached data image.” The LDIM functions to intercept read/write requests that are intended to be received by the LPSD. The read/write requests specify an address of the LPSD.

Abstract: The application discloses a system and method for providing a compact and high speed mechanism for emulating an ASIC or other chip operating within a large computing system environment for diagnostic purposes. A two step process is disclosed for generating data patterns for fully exercising a chip and to then transmit these data patterns at a high frequency to a system under test. In phase one, a pattern generator preferably transmits test pattern data at a first frequency to a memory storage device. In phase two, the memory storage device is enabled to transmit the stored test pattern data at a high frequency to a system under test. Buffering the test pattern data in this manner enables the inventive system to bypass the data transmission speed limitation of the pattern generator while still employing the test patterns created by the pattern generator and to thereby test the system under test under high speed operating conditions.

Abstract: An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

Abstract: A data image management system (DIMS) that includes a local data image manager (LDIM), a remote data image manager (RDIM), and a remote persistent storage device (RPSD). The LDIM communicates with the RDIM through a direct communication link or through a communication network. The RDIM can store data on and retrieve data from the RPSD. In an environment where an LDIM has been installed in a computer having a “local” persistent storage device (LPSD), the DIMS allows for the storing of the LPSD's data image on the RPSD, with the LPSD serving as a persistent, consistent cache of the data image. The data image stored on the RPSD is referred to as the “master data image” and the data image cached on the LPSD is referred to as the “local data image” or “cached data image.” The LDIM functions to intercept read/write requests that are intended to be received by the LPSD. The read/write requests specify an address of the LPSD.

Abstract: A system and method for simplifying the testing and manufacturing process of multi-board solid-state storage systems. The system is constructed by placing secondary non-volatile memory components onto every board in multi-board system that carries primary solid-state components. This allows separate or independent testing of the boards, and final construction of the solid-state system by simply connecting these boards, without the need to either test the completely constructed system or to transfer geometry, faulty location and auxiliary records if the boards have been tested independently.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: Margin testing of memory modules uses a personal computer (PC) motherboard. A test adaptor board has a test socket that receives a memory module under test. Pins from the test adaptor board are plugged into holes of a removed memory-module socket on the motherboard, mounted on the reverse, solder side of the motherboard. The test adapter board has a voltage regulator that controls the power-supply (Vcc) voltage applied to the module under test. A delay circuit on the test adapter board varies the phase delay of a clock to the memory module under test. Margin control signals are generated by a controller card in the PC's expansion slots, to control Vcc and clock delay to the module under test without changing the motherboard's Vcc voltage. The test program executing on the PC motherboard writes to the controller card to adjust voltage and delay, allowing Vcc and setup and hold margins to be tested.

Abstract: A microcontroller including a system bus; a microprocessor coupled to the system bus and configured to transfer data and control signals over the system bus; a memory device coupled to the microprocessor and mapped to the system bus and configured to store microprogram instructions for execution by the microprocessor; a controller coupled to the system bus and configured to transfer data and control signals to the microprocessor over the system bus; a host interface coupled to the system bus and configured to interface to a host computer and receive the data and the control signals over the system bus from the microprocessor; and an I/O interface coupled to the system bus and configured to interface to at least one I/O device and receive the data and the control signals over the system bus from the microprocessor.

Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.

Abstract: The present invention is to provide an emulator and a method of emulation for using testing a system having complex interfaces capable of stable testing can be realize under the system regulation frequency or less frequency without using the high-performance and expensive tester. The emulator comprises a content addressable memory (CAM) configured to store addresses accessed by a system to be tested, a memory unit having storage area corresponding to the entry of the CAM, configured to store data corresponding to the address stored in the CAM, and test information for emulation, a shift register configured to store data and test information from a tester and transfer the data and the test information to the CAM and the memory unit, and a state machine configured to receive a request from a system or a tester and control transferring between a system and a tester.

Abstract: A system for reducing or obviating the requirement for a large amount of defect capture memory in memory test and analysis systems by compressing test results. The compression means system reduces or replaces the fault capture memory in the test system or workstation or both, a major cost in test system, while providing for subsequent regeneration of the test results, either without loss, or with the loss of certain features immaterial to the application.

Abstract: An E2PROM controller is provided for an emulation chip. An E2PROM is connected to a CPU via a memory interconnect bus. The E2PROM and the CPU are also connected to each other via a peripheral circuit interconnect bus independent of the memory interconnect bus. During emulation, the emulation chip is connected to an in-circuit emulator via an emulator interconnect bus, and the memory interconnect bus is disconnected. However, the E2PROM controller allows electrical communication through the peripheral circuit interconnect bus and thereby accesses the E2PROM as one of peripheral circuits. Accordingly, it is possible to check out whether or not a reprogramming program stored in the E2PROM is running normally.

Abstract: An in-circuit emulator (ICE) including an internal trace memory and a bit-width converter. The internal trace memory is embedded in an ICE CPU to trace CPU internal signals fed from a CPU core that executes the same operations as a CPU of a debugged system. The bit-width converter converts the CPU internal signal, which is read out of the internal trace memory, into a plurality of reduced bit-width signals, and supplies them to an ICE controller outside the chip of the ICE CPU in multiple cycles. The configuration makes it possible to remove the restriction imposed, by the number of terminals of the ICE CPU chip, on the number of bits of the CPU internal signal to be output in parallel, and to overcome the difficulty involved in sampling the internal CPU signals by the trace memory, even if the operation frequency of the ICE CPU increases.

Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.

Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.