Abstract: A system and method for asynchronous execution of a test executive subsequence. A first test executive sequence (calling sequence) may be created and configured to asynchronously call a second test executive sequence (subsequence). In one embodiment, a “subsequence call” step may be included in the first test executive sequence, wherein the subsequence call step is operable to asynchronously call the second test executive sequence when the subsequence call step is executed. In response to executing the first test executive sequence, the second test executive sequence may also be executed, asynchronously from the first test executive sequence. The user may specify various options affecting execution of the second test executive sequence (the subsequence). For example, the user may specify various aspects of the execution environment or execution location for the subsequence.

Abstract: A computerized method and system for testing a function of an information-processing system. This includes providing an architecture having a set of test commands, the test commands including a set of one or more stimulation commands and a set of one or more result-testing commands, and defining a set of test verbs out of combinations of the test commands. This allows the test programmer to define an overall test program that uses the test verbs in writing a test program that specifies an overall function that will extensively test a system-under-test. The methods further includes executing a program that includes a plurality of test verb instructions and outputting a result of the program. In some embodiments, the present invention provides a computer-readable media that includes instructions coded thereon that when executed on a suitably programmed computer executes one or more of the above methods.

Abstract: A system and method for detecting and isolating a code portion of a program code thread in a simulator environment wherein the code portion is operable to modify a simulated register object.

Abstract: An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configured to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults to which the added weights are given, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.

Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.

Abstract: A method and a system evaluate an efficacy of a test suite in a model-based diagnostic testing system to determine a revision of the test suite. The evaluation comprises suggesting a test to be added to the test suite based on probabilities of a correct diagnosis and an incorrect diagnosis. The evaluation either alternatively or further comprises identifying a test to be deleted from the test suite based on probabilities of a correct diagnosis for the test suite and for a modified test suite that does not include a test. An efficacy value of each test in the test suite is computed. The system has a computer program comprising instructions that implement an evaluation of diagnostic efficacy of the test suite. The system either is a stand-alone system or is incorporated into the testing system.

Abstract: The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-calculation of only part of a large-scale circuit relating to the measurement point. As shown in FIG. 1, the failure propagation path estimate system according to the present embodiment is generally provided with an input device 1 such as a keyboard or an interface for external devices, a failure propagation path estimate processor (failure propagation path estimate device, error propagation path estimate processor) 2 operated under the control of a program, a storage device 4 for storing information necessary for the failure propagation path estimate process, and an output device 5 such as a display device, a printer or an interface for external devices.

Abstract: A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.

Abstract: A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.

Abstract: A method for verification of multiple priority command processing, including: inputting over time, multiple simulated requests into a simulation model of the computer system, each request having a priority and each request comprising a request and tag transaction, a command ID transaction, command system ID transaction, a system combined response transaction and a completion tag transaction; sorting the priority of each request based; issuing an error if any particular command ID transaction is not a transaction of a request previously sorted; issuing an error if any particular command system ID transaction is not a transaction of a request having a previously issued command ID transaction, if any particular system combined response transaction is not a transaction of a request having a previously issued command system ID transaction and if any particular completion tag transaction is not a transaction of a request having a previously issued system combined response transaction.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: A method and system for testing a microprocessor. The method includes executing debug application software on an external device, downloading diagnostic program instructions from the external device to a cache memory within the microprocessor via a serial test interface. Once the diagnostic program instructions are loaded into the cache memory, the method includes executing the diagnostic program instructions from within the cache memory.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A remote central helpdesk for a plurality of POS appliances includes a diagnostics engine which, on input of a reported problem, executes a series of manual and automated queries in a sequence determined by a decision tree and by the answers to the queries. The diagnostics engine displays the queries on a display, and prompts the helpdesk operator to answer those queries which require a manual input. Automatic queries are executed by the helpdesk computer which interrogates the POS appliance for any necessary data. The diagnostics engine makes the problem-solving visible to the helpdesk operator, and helps the operator to understand their job and the possible reasons why problems might occur.

Abstract: A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information.

Abstract: A peripheral device (which is preferably a disk drive) can automatically collect trace data upon detecting certain error conditions. The peripheral device has the ability to selectively alter the range of state data collected in a trace depending on the error type. Preferably, the device includes a programmable processor executing a control program. A set of trace switches, each enabling a corresponding set of trace points, can be independently set by the control program. An error trace identification table identifies, for each error type, a corresponding set of trace switches. If an error is encountered, the trace switches corresponding to the error type are determined from the table, and the switches are set accordingly. In another invention aspect, a set of trap switches in the device can be set to trap on the occurrence of a specific error type, thereby supporting a more detailed error analysis.

Abstract: A system and method for testing memory management functions of a data processing system. A controller is configured to start and monitor progress of one or more programs, and each of the one or more programs is configured to start a number of threads as specified by input parameter values. At least one or more of the threads are configured to create, modify, and delete one or more memory areas. A feedback activity measures performance characteristics of the data processing system while the one or more threads are executing and selectively adjusts the parameter values in response to the performance characteristics relative to target performance characteristics.

Abstract: A system and method for software test is disclosed that allows user management and adaptation of test procedures and the resulting test data. In an embodiment, the system and method provide a cross-platform user interface which allows testing to be conducted on a plurality of platforms, i.e. it is not integrated with a single platform or language (e.g., C++, Visual Basic, Java, or the like). The method further allows a user to customize a predetermined set of system characteristics relating to the stored test procedure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope of meaning of the claims.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: Embodiments of the invention provide methods for enhancing the downstream product yield without significantly affecting the yield of components from which downstream products are made or enhancing yield of the components without significantly affecting the downstream product yield and performance. In one embodiment, a method comprises obtaining a failure rate of the downstream manufacturing process as a function of each of a plurality of component performance parameters of the current manufacturing process of the component; optimizing weighted factors based on correlation between the current manufacturing process of the component and the downstream product, the weight factors each corresponding to one of the plurality of component performance parameters; and calculating figure of merits (FOM) with respect to the plurality of component performance parameters of the current manufacturing process of the component, the FOM including the weighted factors.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A method and apparatus for testing a computing arrangement. In various embodiments, a plurality of parameter definitions are established, including a static-value parameter and a dynamic-value parameter. A plurality of sets of parameter values are established in association with the parameter definitions. A results storage area has portions respectively associated with the sets of parameter values. A test program is associated with the parameter definitions and is configured to execute using one set of parameter values at a time. The test program inputs a parameter value associated with a static parameter, automatically generates a value for each dynamic parameter, and exercises the computing arrangement using the parameter values in a set, the value of each parameter affecting behavior of the computing arrangement via the test program.

Abstract: Method for diagnosing faults in a system under test (SUT) are provided. A representative method includes identifying at least some portions of the data transmission paths of the SUT capable of introducing errors in data transfer; providing constraints defining relationships of at least some of the portions of the data transmission paths; and diagnosing the SUT with respect to the constraints. Systems, computer-readable media and other methods also are provided.

Abstract: A dynamic waveform manager and an application policy are provided to an electronic device that executes an application requiring the use of waveforms accessed from a waveform table characterized by a limited number of entries. The application policy contains waveform sequencing information specific to the application. The application may utilize any number of waveforms that are typically stored in a memory separate from the waveform table. The dynamic waveform manager monitors the execution of the application, and manages loading and unloading of waveforms required by the application into and out of the waveform table such that each waveform required by the application is loaded in the waveform prior to and at least by the time it is needed by the application. The dynamic waveform manager accesses the application policy to reference the waveform sequencing information specific to the application for use in determining when and which waveforms to load and unload to and from the waveform table.

Abstract: A watchdog timer circuit modified to operate during periods of microcomputer shut-down or sleeping, as for energy conservation purposes, controlled by an independent external rectangular-wave signal for inhibiting watchdog timer reset signal generation for the microcomputer during such shut-down periods and until a wake-up signal is generated at the end of such microcomputer sleeping, whereupon the watchdog circuit will generate a reset signal in the absence of proper microcomputer operation.

Abstract: A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

Abstract: A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

Abstract: A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.

Abstract: A method for creating a guardband that incorporates statistical models for test environment, system environment, tester-to-system offset and reliability into a model and then processes a final guardband by factoring manufacturing process variation and quality against yield loss.

Abstract: A method and system for tracking frequently occurring fail events that are detected during testcase simulation of a simulation model within a batch simulation farm in which testcases are executed within respect to a simulation model on one or more simulation clients. In accordance with the method of the present invention, the instrumentation server receives fail event packets from one or more simulation clients. The fail event packets contains an aggregate of detected occurrences of a specified fail event. The instrumentation server monitors the rate of occurrence of the specified fail event from received fail event packets to detect an excess rate of occurrence of the specified fail event.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.

Abstract: A method of abstracting information through object interfaces is described. The object interfaces are used to present platform device information in a pre-boot service environment. Firmware tables such as Advanced Configuration and Power Interface and System Management Basic Input/Output System may be used to auto-configure diagnostic test suites through an abstracted software interface.

Abstract: A computerized method and system for testing a function of an information-processing system. This includes providing an architecture having a set of test commands, the test commands including a set of one or more stimulation commands and a set of one or more result-testing commands, and defining a set of test verbs out of combinations of the test commands. This allows the test programmer to define an overall test program that uses the test verbs in writing a test program that specifies an overall function that will extensively test a system-under-test. The methods further includes executing a program that includes a plurality of test verb instructions and outputting a result of the program. In some embodiments, the present invention provides a computer-readable media that includes instructions coded thereon that when executed on a suitably programmed computer executes one or more of the above methods.

Abstract: When a computer virus outbreak is detected, a predefined sequence of steps are automatically or manually followed using rule definitions, that may include office hours, to invoke anti-virus counter-measures. The counter-measures can include reducing virus notification, increasing scanning options, blocking E-mail attachments, hiding E-mail address books and the like. The predetermined sequence of actions may be varied with the time of day and day of week.

Abstract: Test tool logic and testing methods are provided for facilitating testing a duplexed computer function, such as a duplexed coupling facility. The test tool allows a testcase written for a first environment to be automatically driven in a second environment, thereby facilitating testing of a function of the second environment. Other aspects include logic for intercepting a system event by a test tool to facilitate testing of system-managed event processing, and for adjusting a display characteristic of one or more messages to be displayed by the test tool based on message type. Further, logic for propagating an environmental error indication and for facilitating processing a wait state are also provided, as are several new test tool verbs and macros.

Abstract: A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predetermined count) and an underflow (decremented to a predetermined count) can be tested by a trigger machine of the Logic Analyzer.

Abstract: A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer.

Abstract: A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and an instruction generator and simulator. The present invention generates a test by selecting instructions for parallel execution based upon resource availability as indicated by the resource-related data structures and the processor's instruction grouping rules, simulating the parallel execution of the instructions on a golden model, updating the resource-related data structures, and evaluating the updated architectural state of the golden model.

Abstract: A computerized method and system for testing a function of an information-processing system. This includes providing an architecture having a set of test commands, the test commands including a set of one or more stimulation commands and a set of one or more result-testing commands, and defining a set of test verbs out of combinations of the test commands. This allows the test programmer to define an overall test program that uses the test verbs in writing a test program that specifies an overall function that will extensively test a system-under-test. The methods further includes executing a program that includes a plurality of test verb instructions and outputting a result of the program. In some embodiments, the present invention provides a computer-readable media that includes instructions coded thereon that when executed on a suitably programmed computer executes one or more of the above methods.

Abstract: A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results.

Abstract: A test pattern generator and a method of generating a test pattern. The method includes converting a test pattern into a program and simulating the program to produce a test pattern. The test pattern is applied to a test circuit to obtain simulated test results. The program is written to a memory unit. The test circuit is tested using the program inside the memory unit to produce actual test results. The simulated test results and the actual test results are compared. If the simulated and the actual results match each other, the test circuit is repeatedly test using the test pattern until no delay between loop backs is found. However, if there is a mismatch between the simulated and the actual results, the program is adjusted and the test circuit re-tested until a match between the simulated results and the actual results is found.

Abstract: An invention is provided for testing in a Java based environment. The method includes launching a test harness in a first JVM, and starting a virtual machine (VM) agent in a second JVM. The VM agent is placed in communication with the test harness. The VM agent then executes a test application such that both the test application and the VM agent execute in the second JVM. In this manner, the VM agent is restarted using the test harness if the second JVM fails.

Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.

Abstract: A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.

Abstract: An improved method and system for detecting differences between first and second test executive sequence files in a computer system. Each of the test executive sequence files may comprise a plurality of interrelated objects. The objects may be compared and differences between the objects may be displayed. The objects may comprise one or more of: a sequence; a global variable; and/or a data type. A sequence may comprise: a step, a parameter, and/or a local variable. A step of a sequence may comprise a tree structure of step properties. Each step property may comprise one or more of: a property value, property flags, and/or a property comment. An object may comprise a hierarchy of objects (e.g., a parent object and a child sub-object). Differences between the hierarchy of objects may be detected. Differences may be navigated. Each displayed difference may be characterized as an insertion or a deletion.

Abstract: An in-circuit emulation system consisting of an emulation base and a slightly modified, flash-based COP8 architecture microcontroller. In addition to the flash memory where the User's program resides, the COP8 device includes a small ROM area with a monitor program that is used to communicate commands and data with the emulation base. Two new instructions are added, one for entering the ROM area and one for exiting it. A small set of the COP8 device's digital pins are modified to allow data, status and control to be exchanged between the COP8's CPU and the emulation base. These modified COP8 pins are recreated by the emulation base so that emulation occurs with the COP8's full complement of I/O. The content of the signals shared between the COP8 and the emulation base allows for a full range of emulation capabilities. The COP8 device is emulated in situ on the printed circuit board providing accurate operation of precision peripherals and environmental variables.

Abstract: A simulation system simulates an operation of a memory. This system includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a read/write operation of a memory model only by setting a memory address. A set of free bits, which is not used for the simulation of a memory operation, is used as a memory address for indicating the error generation. It is thus unnecessary to prepare a new description of a signal line exclusively for indication of error generation and it is possible to simulate a memory operation containing an error only by the normal descriptions of an address, data, and the like.

Abstract: In order to measure the power consumed by a central processing unit during execution of a software program, the trace components are used to determine the input signals and the output signals and interrupt conditions for each clock cycle. The input signals and the output signals can be applied to a simulation model of the central processing system to determine the state of the central processing unit for each clock cycle. The simulation model is also used to determine the power dissipated for each state. Combining the knowledge of the progression of states of the central processing unit with the power consumed by the central processing unit for each state, the consumption of power by the central processing unit can be determined as a function of execution of the program. By comparing the power consumed with the portion of the program being executed, the program can be adjusted to reduce the power required during the execution of the program.