Abstract: An automatic testing system (100) for testing an electronic device (300) includes a testing plan module (130), a testing storage and management module (120), a testing script generating module (140), and an automatic testing module (110). The testing plan module is used for receiving a testing plan. The testing storage and management module is used for saving the testing plan. The testing script generating module is used for generating testing scripts according to the testing plan, and for saving the testing scripts in the testing storage and management module. The automatic testing module is used for reading at least one testing script saved in the testing storage and management module, for automatically testing the electronic device, for receiving test data from the electronic device, and for saving the test data in the testing storage and management module. An automatic testing method for testing the electronic device is also provided.

Abstract: An apparatus having: an agent; and a first test session servlet running on the agent, receiving a test description in a predetermined format from a caller, threading a first test session that invokes the agent to run the at least one subtest. The test description has at least one predefined subtest, dynamic data, and predefined test parameters. The first test session servlet receives test results from the first test session, and sends the subtest results from the at least one subtest and the dynamic data back to the caller.

Abstract: The invention relates to a system and method for facilitating programmable coverage domains for test case generation, feedback, and measurement. The system comprises a domain definition input file; user-defined coverage domain data entered into the domain definition input file; and a parser operable for translating the user-defined coverage domain data into machine-readable computer program code. The system further includes an internal coverage domain comprising: a union of enabled coverage domains extracted from the user-defined coverage domain data; a session component comprising a session update count for each domain element; and a history component comprising a history update count for each domain element. The system further comprises a testcase generator including an internal coverage feedback and measurement system.

Abstract: An automated system for improving the testing of computer devices designed for coupling with docking devices. A plurality of networked computing devices that are individually connected to a compatible docking device through a slave switch. Each slave switch independently connects or disconnects individual computing devices from an attached docking device based on commands obtained from a server. By controlling the electrical connection between the individual computing devices and attached docking devices, the slave switch can simulate the action of docking or undocking one or more selected computers without human intervention. As a result, the present invention provides a system and method that automates the action of docking or undocking a computer. For example, the present invention is suited for use in computer device testing systems wherein a shut down command is sent to a selected computer, after which the selected computer is disconnected from an attached docking device.

Abstract: A processor code debugger method and system enables the setting at one time of breakpoints corresponding to a given line of source code associated with an instruction in multiple processing engines.

Abstract: Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Abstract: A method and apparatus for reinitializing firmware in the event of a fault in a storage area network comprising at least one storage controller having programmable memory and RAM, said at least one storage controller for controlling data access between at least one host server and a storage device. The method is provided during background operations, and includes detecting a fault and suspending data access commands from the at least one host server. The firmware stored in programmable memory is reinstalled, and the at least one storage controller is reinitialized. The reinstallation of the firmware and reinitializing of the controller is quickly completed such that data access commands from the at least one host server to the at least one storage device are satisfied prior to the host server timing out and initiation a data access error message.

Abstract: A computer system enables a user to define the system's security profile while automatically detecting whether the security profile being defined creates data hazards for the computer system. To achieve the foregoing, the computer system utilizes memory and a security application. The security application displays a list of security rules to a user and selectively enables the security rules based on user inputs. The security application causes the computer system to enforce the enabled security rules by modifying security settings of the computer system. For each enabled rule, the security application analyzes data that indicates which of the security rules, when enforced by the computer system, create a data hazard for a particular computer application. The security application then detects a data hazard, if the data indicates that the enabled rule creates a data hazard for the particular application and if the particular application is installed on the computer system.

Abstract: One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison are checked only for redundant operations. Another embodiment disclosed relates to a microprocessor with built-in functional testing capability. The microprocessor includes multiple functional units of a same type and registers that receive outputs from the multiple functional units. In addition, comparator circuitry is built-in that also receives the outputs from the multiple functional units and compares the outputs to provide functional testing.

Abstract: Improved methods and structures for testing of SAS components, in situ, in a SAS domain. A first SAS component is adapted to generate stimuli such as error conditions to elicit a response to the error condition from a second SAS component coupled to the first in the intended SAS domain configuration. In one aspect, a SAS device controller generates stimuli applied to a SAS expander coupled thereto and verifies proper response from the SAS expander. In another aspect, a SAS expander generates stimuli applied to a SAS device controller coupled thereto and verifies proper response from the SAS device controller. Stimuli may be generated by custom circuits or firmware/software within the first component. Vendor specific SAS SMP transactions may be used to cause the first component to enter the special verification mode.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: Disclosed herein is a method of storing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, result data obtained by simulation of at least one HDL model are received. In association with the result data, a plurality of value sets is received, where each value set includes at least one keyword having an associated value. Each keyword identifies a parameter external to the HDL model that affected the result data. The data results are stored within a data storage subsystem in association with the plurality of value sets such that particular result data are attributable to particular ones of the plurality of value sets. In one embodiment, a keyword table is built in the data storage system that indicates which data subdirectories store result data associated with particular value sets. The result data can then be queried based upon selected keywords of interest, for example, by reference to the keyword table.

Abstract: One embodiment of the invention provides a method for simulating the operation of a system. The method includes providing a fault tree representation of the system. The fault tree defines a set of problems that may occur in the system, and specifies propagations in the system whereby a problem may create one or more errors that may in turn be detected by error detectors to produce corresponding error reports. The fault tree representation allows the presence of a problem in the system to be simulated, and the set of error reports resulting from the simulated problem to be determined. This simulation can be repeated for different problems to compare the sets of error reports potentially produced by the different problems.

Abstract: A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Abstract: A configuration contains a test unit that, during emulation, replaces a program-controlled unit that is used in normal operation of the system containing the program-controlled unit. The test unit has a first program-controlled unit and a second program-controlled unit. The first program-controlled unit contains only some of the components of the program-controlled unit replaced by the test unit, and the second program-controlled unit contains those components of the program-controlled unit replaced by the test unit that are not contained in the first program-controlled unit. In addition, the first program-controlled unit contains a control device which monitors whether one of the components of the first program-controlled unit requests access to a component not present in the first program-controlled unit and which, if this is so, prompts appropriate access to the corresponding component in the second program-controlled unit.

Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: A system and method for asynchronous execution of a test executive subsequence. A first test executive sequence (calling sequence) may be created and configured to asynchronously call a second test executive sequence (subsequence). In one embodiment, a “subsequence call” step may be included in the first test executive sequence, wherein the subsequence call step is operable to asynchronously call the second test executive sequence when the subsequence call step is executed. In response to executing the first test executive sequence, the second test executive sequence may also be executed, asynchronously from the first test executive sequence. The user may specify various options affecting execution of the second test executive sequence (the subsequence). For example, the user may specify various aspects of the execution environment or execution location for the subsequence.

Abstract: A computerized method and system for testing a function of an information-processing system. This includes providing an architecture having a set of test commands, the test commands including a set of one or more stimulation commands and a set of one or more result-testing commands, and defining a set of test verbs out of combinations of the test commands. This allows the test programmer to define an overall test program that uses the test verbs in writing a test program that specifies an overall function that will extensively test a system-under-test. The methods further includes executing a program that includes a plurality of test verb instructions and outputting a result of the program. In some embodiments, the present invention provides a computer-readable media that includes instructions coded thereon that when executed on a suitably programmed computer executes one or more of the above methods.

Abstract: An invention is disclosed for providing methods for parsing test results having diverse formats. Test results from executed test suites are identified. Test result formats of the test results are categorized. An order of the test results is tracked. A chain of parsers is assembled from individual parsers such that each individual parser is charged with parsing a particular test result format. Test results are parsed such that the data features that define attributes of the test results are identified where the attributes define pass, fail, and comments associated with the pass or fail.

Abstract: A system and method for detecting and isolating a code portion of a program code thread in a simulator environment wherein the code portion is operable to modify a simulated register object.

Abstract: An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configured to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults to which the added weights are given, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.

Abstract: External test equipment is used to simulate an internal BIST test, thus enabling the capture or generation of detailed test results. By simulating the BIST test sequence in real time during the test, the external tester may monitor an output from the BIST and determine the exact location of failures when they occur. The external tester may generate a bit fail map indicating whether each memory location passed or failed the BIST test.

Abstract: A method and a system evaluate an efficacy of a test suite in a model-based diagnostic testing system to determine a revision of the test suite. The evaluation comprises suggesting a test to be added to the test suite based on probabilities of a correct diagnosis and an incorrect diagnosis. The evaluation either alternatively or further comprises identifying a test to be deleted from the test suite based on probabilities of a correct diagnosis for the test suite and for a modified test suite that does not include a test. An efficacy value of each test in the test suite is computed. The system has a computer program comprising instructions that implement an evaluation of diagnostic efficacy of the test suite. The system either is a stand-alone system or is incorporated into the testing system.

Abstract: The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-calculation of only part of a large-scale circuit relating to the measurement point. As shown in FIG. 1, the failure propagation path estimate system according to the present embodiment is generally provided with an input device 1 such as a keyboard or an interface for external devices, a failure propagation path estimate processor (failure propagation path estimate device, error propagation path estimate processor) 2 operated under the control of a program, a storage device 4 for storing information necessary for the failure propagation path estimate process, and an output device 5 such as a display device, a printer or an interface for external devices.

Abstract: A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.

Abstract: A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.

Abstract: A method for verification of multiple priority command processing, including: inputting over time, multiple simulated requests into a simulation model of the computer system, each request having a priority and each request comprising a request and tag transaction, a command ID transaction, command system ID transaction, a system combined response transaction and a completion tag transaction; sorting the priority of each request based; issuing an error if any particular command ID transaction is not a transaction of a request previously sorted; issuing an error if any particular command system ID transaction is not a transaction of a request having a previously issued command ID transaction, if any particular system combined response transaction is not a transaction of a request having a previously issued command system ID transaction and if any particular completion tag transaction is not a transaction of a request having a previously issued system combined response transaction.

Abstract: A method and system for testing a microprocessor. The method includes executing debug application software on an external device, downloading diagnostic program instructions from the external device to a cache memory within the microprocessor via a serial test interface. Once the diagnostic program instructions are loaded into the cache memory, the method includes executing the diagnostic program instructions from within the cache memory.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A remote central helpdesk for a plurality of POS appliances includes a diagnostics engine which, on input of a reported problem, executes a series of manual and automated queries in a sequence determined by a decision tree and by the answers to the queries. The diagnostics engine displays the queries on a display, and prompts the helpdesk operator to answer those queries which require a manual input. Automatic queries are executed by the helpdesk computer which interrogates the POS appliance for any necessary data. The diagnostics engine makes the problem-solving visible to the helpdesk operator, and helps the operator to understand their job and the possible reasons why problems might occur.

Abstract: A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information.

Abstract: A peripheral device (which is preferably a disk drive) can automatically collect trace data upon detecting certain error conditions. The peripheral device has the ability to selectively alter the range of state data collected in a trace depending on the error type. Preferably, the device includes a programmable processor executing a control program. A set of trace switches, each enabling a corresponding set of trace points, can be independently set by the control program. An error trace identification table identifies, for each error type, a corresponding set of trace switches. If an error is encountered, the trace switches corresponding to the error type are determined from the table, and the switches are set accordingly. In another invention aspect, a set of trap switches in the device can be set to trap on the occurrence of a specific error type, thereby supporting a more detailed error analysis.

Abstract: A system and method for testing memory management functions of a data processing system. A controller is configured to start and monitor progress of one or more programs, and each of the one or more programs is configured to start a number of threads as specified by input parameter values. At least one or more of the threads are configured to create, modify, and delete one or more memory areas. A feedback activity measures performance characteristics of the data processing system while the one or more threads are executing and selectively adjusts the parameter values in response to the performance characteristics relative to target performance characteristics.

Abstract: A system and method for software test is disclosed that allows user management and adaptation of test procedures and the resulting test data. In an embodiment, the system and method provide a cross-platform user interface which allows testing to be conducted on a plurality of platforms, i.e. it is not integrated with a single platform or language (e.g., C++, Visual Basic, Java, or the like). The method further allows a user to customize a predetermined set of system characteristics relating to the stored test procedure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope of meaning of the claims.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: Embodiments of the invention provide methods for enhancing the downstream product yield without significantly affecting the yield of components from which downstream products are made or enhancing yield of the components without significantly affecting the downstream product yield and performance. In one embodiment, a method comprises obtaining a failure rate of the downstream manufacturing process as a function of each of a plurality of component performance parameters of the current manufacturing process of the component; optimizing weighted factors based on correlation between the current manufacturing process of the component and the downstream product, the weight factors each corresponding to one of the plurality of component performance parameters; and calculating figure of merits (FOM) with respect to the plurality of component performance parameters of the current manufacturing process of the component, the FOM including the weighted factors.

Abstract: A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.

Abstract: A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Abstract: A method and apparatus for testing a computing arrangement. In various embodiments, a plurality of parameter definitions are established, including a static-value parameter and a dynamic-value parameter. A plurality of sets of parameter values are established in association with the parameter definitions. A results storage area has portions respectively associated with the sets of parameter values. A test program is associated with the parameter definitions and is configured to execute using one set of parameter values at a time. The test program inputs a parameter value associated with a static parameter, automatically generates a value for each dynamic parameter, and exercises the computing arrangement using the parameter values in a set, the value of each parameter affecting behavior of the computing arrangement via the test program.

Abstract: Method for diagnosing faults in a system under test (SUT) are provided. A representative method includes identifying at least some portions of the data transmission paths of the SUT capable of introducing errors in data transfer; providing constraints defining relationships of at least some of the portions of the data transmission paths; and diagnosing the SUT with respect to the constraints. Systems, computer-readable media and other methods also are provided.

Abstract: A dynamic waveform manager and an application policy are provided to an electronic device that executes an application requiring the use of waveforms accessed from a waveform table characterized by a limited number of entries. The application policy contains waveform sequencing information specific to the application. The application may utilize any number of waveforms that are typically stored in a memory separate from the waveform table. The dynamic waveform manager monitors the execution of the application, and manages loading and unloading of waveforms required by the application into and out of the waveform table such that each waveform required by the application is loaded in the waveform prior to and at least by the time it is needed by the application. The dynamic waveform manager accesses the application policy to reference the waveform sequencing information specific to the application for use in determining when and which waveforms to load and unload to and from the waveform table.

Abstract: A watchdog timer circuit modified to operate during periods of microcomputer shut-down or sleeping, as for energy conservation purposes, controlled by an independent external rectangular-wave signal for inhibiting watchdog timer reset signal generation for the microcomputer during such shut-down periods and until a wake-up signal is generated at the end of such microcomputer sleeping, whereupon the watchdog circuit will generate a reset signal in the absence of proper microcomputer operation.

Abstract: A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

Abstract: A software and hardware system and an associated methodology provides ATE-independent go/no-go testing as well as advanced failure diagnosis of integrated circuits for silicon debug, process characterization, production (volume) testing, and system diagnosis comprises an embedded test architecture designed within an integrated circuit; means for seamlessly transferring information between the integrated circuit and its external environment; and an external environment that effectuates the seamless transfer for the user to perform relevant test and diagnosis.

Abstract: A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.

Abstract: A method for creating a guardband that incorporates statistical models for test environment, system environment, tester-to-system offset and reliability into a model and then processes a final guardband by factoring manufacturing process variation and quality against yield loss.

Abstract: A method and system for tracking frequently occurring fail events that are detected during testcase simulation of a simulation model within a batch simulation farm in which testcases are executed within respect to a simulation model on one or more simulation clients. In accordance with the method of the present invention, the instrumentation server receives fail event packets from one or more simulation clients. The fail event packets contains an aggregate of detected occurrences of a specified fail event. The instrumentation server monitors the rate of occurrence of the specified fail event from received fail event packets to detect an excess rate of occurrence of the specified fail event.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.