Analysis (e.g., Of Output, State, Or Design) Patents (Class 714/37)
  • Patent number: 8984344
    Abstract: During a debug mode of operation of a data processor it is determined whether a data access request is to a stack of the data processor. If not, a data trace message based on the data access request is generated for transmission to a debugger so long as an address being accessed by data access request meets a predefined address range criteria. Otherwise, if the data access request is to the stack of the data processor, a data trace message based on the data access request is prevented from being generated for transmission to the debugger regardless the predefined address range criteria.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8984342
    Abstract: Method and system for a test process. The method may include performing tests on one or more units under test (UUTs). At least one test on one or more UUTs may be performed. A signal may be acquired from the UUT. A reference signal may be retrieved. The reference signal may be derived from a transmitted signal characteristic of the UUT. The signal may be analyzed with respect to the reference signal. Results, useable to characterize the one or more UUTs, from performing the at least one test on the one or more UUTs may be stored. The reference signal may be derived from an initial test and may be stored for subsequent retrieval. A respective reference signal may be retrieved for all UUTs of the one or more UUTs for a respective test. The signal may be a radio frequency signal. The UUT may be a wireless mobile device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: March 17, 2015
    Assignee: National Instruments Corporation
    Inventors: Craig E. Rupp, Gerardo Orozco Valdes, I. Zakir Ahmed, Vijaya Yajnanarayana
  • Patent number: 8983790
    Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Ushasri Merugu, Siva V. N. Hemasunder Tallury, Sudheer Kumar Koppolu
  • Publication number: 20150074464
    Abstract: A computer hardware-implemented method, system, and/or computer program product prevents a cascading failure in a complex stream computer system causing an untrustworthy output from the complex stream computer system. Multiple upstream subcomponents in a complex stream computer system generate multiple outputs, which are used as inputs to a downstream subcomponent, wherein the multiple upstream subcomponents execute upstream computational processes. Each upstream computational process is examined to determine an accuracy of each identified output. An accuracy value is assigned to each of the multiple outputs from the upstream subcomponents, and weighting values are assigned to each of the inputs to the downstream subcomponent. The accuracy values and weighting values are utilized to dynamically adjust inputs to the downstream subcomponent until an output from the downstream subcomponent meets a predefined trustworthiness level.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: ROBERT R. FRIEDLANDER, JAMES R. KRAEMER, JUSTYNA M. NOWAK, ELIZABETH V. WOODWARD
  • Publication number: 20150074463
    Abstract: The present invention is directed to a method and information handling system (IHS) for improving system performance in a storage area network. An embodiment of the present invention begins by obtaining diagnostic data for the storage area network by asking a user one or more questions and storing results to the one or more questions. Next, test data is obtained by running one or more testing modules on at least one component of the storage area network. A performance analysis of the storage area network is executed, including the obtained diagnostic data and the obtained test data. Then, one or more performance issues and one or more action plans for resolution are identified based upon the analysis. Finally, a report to one or more users is provided including the one or more identified performance issues and the one or more action plans.
    Type: Application
    Filed: March 25, 2014
    Publication date: March 12, 2015
    Applicant: Dell Products, LP
    Inventors: Robert B. Jacoby, Howard Earnest Arnold
  • Publication number: 20150074462
    Abstract: The invention pertains to a method and information handling system (IHS) for reducing storage device vulnerability to degraded performance, data unavailability or data loss. An embodiment of the method of the present invention begins by storing debug data associated with at least one storage device and obtaining diagnostic data for the at least one storage device. Next, an analysis is performed using the obtained data and the stored debug data. Then, one or more issues and one or more action plans for resolution may be identified. Finally, a report is provided to one or more users including the one or more identified issues and the one or more action plans.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 12, 2015
    Applicant: Dell Products, LP
    Inventor: Robert B. Jacoby
  • Patent number: 8977901
    Abstract: Disclosed are various embodiments for generating a service call pattern for a system. A monitor is installed on a first and a second service call channel. Each service call channel is used by a first and second system under test, respectively. Through the monitor, service calls are received from the respective system under test. The service calls are issued to at least one service. A first service call pattern is generated based at least in part on the plurality of service calls issued by the first system under test. A second service call pattern is generated based at least in part on the plurality of service calls issued by the second under test. The first service call pattern report and the second service call pattern report are compared. An error condition if the comparison indicates a difference greater than a predefined threshold.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: March 10, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Nirav J. Desai, Stanislava R. Vlasseva, Kyle Andrew Farrell, Michael C. Moore
  • Publication number: 20150067401
    Abstract: A computer recovery method for a computer system, the computer system having: a management computer having a processor and a memory; and a computer having a processor, a memory, and a monitoring part for notifying, when an abnormality occurs, the management computer of the abnormality, the management computer being configured to instruct recovery from the abnormality, the computer recovery method having: a first step of obtaining, by the management computer, hardware components and software components of the computer as configuration information; a second step of receiving, by the management computer, notification of an abnormality from the monitoring part of the computer; and a third step of generating, by the management computer, after the notification is received, component string information for identifying a component where the abnormality has occurred from the configuration information.
    Type: Application
    Filed: June 22, 2012
    Publication date: March 5, 2015
    Applicant: HITACHI, LTD.
    Inventors: Yujiro Ichikawa, Yoshifumi Takamoto, Takashi Tameshige, Masaaki Iwasaki, Masayasu Asano
  • Publication number: 20150067403
    Abstract: Method and Apparatus for rapid scalable unified infrastructure system management platform are disclosed by discovery of compute nodes, network components across data centers, both public and private for a user; assessment of type, capability, VLAN, security, virtualization configuration of the discovered unified infrastructure nodes and components; configuration of nodes and components covering add, delete, modify, scale; and rapid roll out of nodes and components across data centers both public and private.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Zeeshan Naseh, Yusuf Akhtar, Faisal Azizullah
  • Publication number: 20150067400
    Abstract: A method, computer program product, and system that discards unneeded elements when generating a fault tree of an object to be analyzed. Configuration information identifies a plurality of functional blocks comprised by the object and a plurality of signal lines that connect the functional blocks in logical relationships. Exclusion target information identifies a signal line that may be excluded from the plurality of signal lines without loss of information or a functional block that may be excluded from the plurality of functional blocks without loss of information. Exclusion of a block or signal line may be determined by detecting a redundant functional block or by detecting a circular signal path traversed by two or more signal lines. The generated fault tree omits the excluded block or signal line and identifies the existence of a redundant block or of a circular signal path.
    Type: Application
    Filed: July 1, 2014
    Publication date: March 5, 2015
    Inventor: Sugio Ishii
  • Publication number: 20150067399
    Abstract: A method and system to perform analysis, recovery or repair of devices attached to a remote computing system from a local computing system is presented. The remote computing system is initialized with an independent operating system that executes computer code, and interfaced, over a digital network, with a local computing system. This converts the remote computing system into an analysis, recovery and repair tool for the remote delivery of advanced technical services such as: network analysis, data recovery, digital forensics, software installation and operating system repair, data cloning, and malware remediation.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Inventor: Jon Jaroker
  • Publication number: 20150067402
    Abstract: A processor-implemented method provides a remote diagnosis for an information appliance via a secure connection. A command is received from a console, and an examination is performed to determine whether or not the command is permitted to be issued. In response to a remote diagnostic module being initiated, a determination is made as to whether a secure connection to a remote information appliance has been created. In response to determining that the secure connection to the remote information appliance has been created, the command is transmitted to the remote information appliance via the secure connection.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Cheng-Ta Lee, Jeffrey CH Liu, Joey HY Tseng, Rick MF Wu
  • Patent number: 8972789
    Abstract: A diagnostic system provides identification of symptoms in a distributed network and an engine for providing recommended rectification of error sources that correspond to the symptoms. The distributed network may be accessed for current statistics. Symptoms may be identified that correspond to the current statistics. A recommended course of action for the distributed network may be provided based on a predetermined list of courses of actions that correspond to rectifying the performance in the error sources.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keshav Kamble, Nandakumar Peethambaram, Abhijit Prabhakar Kumbhare, Vijoy A. Pandey
  • Patent number: 8972790
    Abstract: A controller section outputs a first signal and a second signal holding a phase relationship with the first signal. The second signal is received by a memory I/F section via a FIFO memory of an error detecting section. The memory I/F section performs timing adjustment for the first and second signals, outputs the first and second signals after the timing adjustment to a memory, and loops back the second signal. A data comparator compares the looped-back second signal with the original second signal outputted from the FIFO memory and corresponding to the looped-back signal.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: March 3, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hisataka Nakabayashi, Miho Takeda, Masanori Ito
  • Patent number: 8972795
    Abstract: In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the number of interprocessor communications as a result of the analysis; and optimization method output unit for displaying and outputting a method of optimizing the system in response to a result of the analysis.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Spansion LLC
    Inventor: Masaomi Teranishi
  • Patent number: 8972788
    Abstract: A method of ticket consolidation in computing environment may in one aspect analyze problem reports, determine whether problems reported by machines are caused by the same or substantially the same run-time configuration error or are occurring on the same physical server, and are within the given sensitivity time window, consolidate the problem tickets and increase the priority of the consolidated ticket.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Ruchi Mahindru, Valentina Salapura
  • Patent number: 8972786
    Abstract: During starting of a field device for pressure measurement, flow measurement and/or fill level measurement, which field device including a memory that includes a boot memory region in which a boot function is stored, and an operating memory region in which an operating function is stored, the following steps are carried out: carrying out the boot function; determining whether a memory check of the operating memory region is to be carried out; carrying out a memory check of the operating memory region when it has been determined that a memory check is to be carried out; and carrying out the operating function.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: March 3, 2015
    Assignee: VEGA Grieshaber KG
    Inventors: Andreas Isenmann, Martin Gaiser
  • Patent number: 8972787
    Abstract: A flexible system for collecting and reporting instrumentation metrics relating to performance of a software product. Computing devices that execute the software product receive a manifest that specifies the manner in which instrumentation metrics are collected and reported, including what instrumentation metrics are collected. Based on the manifest, an instrumentation metrics client associated with a software product may retrieve instrumentation data from a software product or other sources. The metrics client may then generate one or more instrumentation metrics, based on the instrumentation data, in accordance with instructions in the manifest. The metrics client may then take one or more actions based on the instrumentation metrics and the manifest, such as reporting the information to an instrumentation metrics server for aggregation and analysis by the metrics server or performing escalation actions that can modify the metrics collected and reported.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: March 3, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sivarudrappa Mahesh, Kinshumann Kinshumann, Kripashankar Mohan, Shlok Bidasaria
  • Publication number: 20150058674
    Abstract: A message control program of an embodiment causes a monitoring apparatus to further function as a plurality of message control unit configured to individually controlling a communication method of a message transmitted from each internal application unit. Each message control unit receives a message containing a message type and service name from the internal application unit. Each message control unit specifies communication method identification information from a file based on the message type and service name in the received message. Each message control unit changes the communication method of the received message based on the specified communication method identification information, and sends the message to a common bus.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Yosuke TERASHITA, Kaori MORISHITA, Chika NAKAZATO
  • Publication number: 20150052400
    Abstract: A debugging system may display snapshot information that may be collected in response to an event identified while an application executes. The debugging system may allow a user to browse the various data elements in the snapshot, and may allow the user to modify a snapshot configuration by including or excluding various data elements within the snapshot data. The user interface may have a mechanism for including or excluding data elements that may be presented during browsing, as well as options to change the events that may trigger a snapshot. The updated snapshot configuration may be saved for future execution when the event conditions are satisfied.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: CONCURIX CORPORATION
    Inventors: Charles D. GARRETT, Alexander G. Gounares
  • Publication number: 20150052399
    Abstract: A network system comprising logical work and protect Connection Termination Points. Performance Monitoring (PM) records are provided by generating for each work Connection Termination Point (CTP) a work bit vector and a protect bit vector. The work bit vector keeps track of severely errored seconds (SES) occurrences at the work CTP only when the work CTP is selected. The protect bit vector keeps track of severely errored seconds (SES) occurrences at the protect CTP only when the protect CTP is selected. Processing the work bit vector and the protect bit vector provides accurate PM records.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: Ciena Corporation
    Inventors: Simmon YAU, Satish M. GOPALAKRISHNA, Yossi Joseph KHALON, Matthew W. CONNOLLY
  • Patent number: 8959398
    Abstract: An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: February 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott P. Nixon, Eric M. Rentschler
  • Publication number: 20150046750
    Abstract: An error operation unit configured to output an error detection code in response to a plurality of control signals, a plurality of vectors and data, a vector storage unit configured to store the plurality of vectors, and a vector switching unit configured to provide the plurality of vectors to the error operation unit in response to the plurality of control signals are included.
    Type: Application
    Filed: November 27, 2013
    Publication date: February 12, 2015
    Applicant: SK hynix Inc.
    Inventor: Chan Gi GIL
  • Publication number: 20150046751
    Abstract: Provided are a computer program product, system, and method for managing traces to capture data for memory regions in a memory. A trace includes a monitor parameter used by a trace procedure to monitor data in a memory device. A frequency is determined at which the trace procedure monitors the memory device. The trace procedure is invoked at the determined frequency to perform trace procedure operations comprising determining a region in the memory device according to the monitor parameter and copying data in the determined region to trace data in a data space.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Neal E. Bohling, Joseph V. Malinowski, David C. Reed, Max D. Smith
  • Publication number: 20150039940
    Abstract: A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Oracle International Corporation
    Inventors: Paul N. Loewenstein, Basant Vinaik
  • Patent number: 8949674
    Abstract: A computational geometry technique is utilized to detect, diagnose, and/or mitigate fault detection during the execution of a software application. Runtime measurements are collected and processed to generate a geometric enclosure that represents the normal, non-failing, operating space of the application being monitored. When collected runtime measurements are classified as being inside or on the perimeter of the geometric enclosure, the application is considered to be in a normal, non-failing, state. When collected runtime measurements are classified as being outside of the geometric enclosure, the application is considered to be in an anomalous, failing, state. In an example embodiment, the geometric enclosure is a convex hull generated in N-dimensional Euclidean space. Appropriate action (e.g., restart the software, turn off access to a network port) can be taken depending on where the measurement values lie in the space.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 3, 2015
    Assignee: Drexel University
    Inventors: Spiros Mancoridis, Chris Rorres, Maxim Shevertalov, Kevin M. Lynch, Edward Stehle
  • Publication number: 20150033077
    Abstract: An approach is presented for identifying related problem tickets in an information technology (IT) environment. A pattern of actions included in interactions with a computer program is determined to be effective at proactively preventing a problem in the IT environment based on a frequency at which user(s) performed the interactions which perform text and statistical analyses of content of historical problem tickets. A script based on the pattern of actions is generated. A root cause of the problem is determined based on the text and statistical analyses. Responsive to a receipt of a new problem ticket, the script is executed to automatically perform the pattern of actions. The new problem ticket is classified as being in a group of problem tickets which are related to the problem and included in the historical problem tickets. The new problem ticket is determined to specify the problem which has the root cause.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Anuradha Bhamidipaty, Winnie Wing-Yee Cheng, Aliza R. Heching, Anshu N. Jain, Jia Liu, James R. Moulic, Daniela Rosu, Mithkal M. Smadi, Srikanth G. Tamilselvam
  • Publication number: 20150033076
    Abstract: A method is for handling an anomaly in an industrial control system (ICS) connected to a network with a plurality of other ICSs and an anomaly analyzer. An ICS receives status data from its own industrial process, and stores this status data as normal pattern data. The ICS transmits its own status data to one or more other ICSs. The ICS receives an indication from the anomaly analyzer that the ICS is suspected of having an anomaly. The ICS transmits alternate status data based on the normal pattern data stored during non-suspect operation, and stores the status data received from its own industrial process as real status data. In response to receiving from the anomaly analyzer an indication that the ICS is not operating anomalously, the ICS transmits the stored real data, and switches back to transmitting its own status data to one or more other ICSs.
    Type: Application
    Filed: September 11, 2014
    Publication date: January 29, 2015
    Inventors: Kazuhito Akiyama, Michiharu Kudo, Takuya Mishina, John D. Wilson
  • Publication number: 20150033064
    Abstract: A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Microsoft Corporation
    Inventors: John D. Davis, Karin Strauss, Mark Steven Manasse, Parikshit S. Gopalan, Sergey Yekhanin
  • Patent number: 8943366
    Abstract: Methods, apparatuses, and computer program products for administering checkpoints for incident analysis are provided. Embodiments include a checkpoint manager receiving from each incident analyzer of a plurality of incident analyzers, a checkpoint indicating an incident having the oldest identification number still in analysis by the incident analyzer at the time associated with the checkpoint. The checkpoint manager examines each received checkpoint to identify, as a restore incident, an incident having the oldest identification number indicated in any of the received checkpoints. A monitor sends to the incident analyzers, a stream of incidents beginning with the identified restore incident and continuing with any incidents having a newer identification number than the identified restore incident.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: James E. Carey, Philip J. Sanders
  • Patent number: 8943367
    Abstract: A method for metric ranking in invariant networks includes, given an invariant network and a set of broken invariants, two ranking processes are used to determine and rank the anomaly scores of each monitoring metrics in large-scale systems. Operators can follow the rank to investigate the root-cause in problem investigation. In a first ranking process, given a node/metric, the method determines multiple scores by integrating information from immediate neighbors to decide the anomaly score for metric ranking. In a second ranking process, given a node/metric, an iteration process is used to recursively integrate the information from immediate neighbors at each round to determine its anomaly score for metric ranking.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 27, 2015
    Assignee: NEC Laboratories America, Inc.
    Inventors: Guofei Jiang, Min Ding, Yong Ge
  • Publication number: 20150026521
    Abstract: In the invariant analysis, a fault cause is judged correctly. A correlation model storing unit (112) of an operation management apparatus (100) stores a correlation model including one or more correlation functions each of which indicates a correlation between two metrics different each other among a plurality of metrics in a system. The correlation destruction detecting unit (103) detects correlation destruction of the correlation which is included in the correlation model by applying newly inputted values of the plurality of metrics to the correlation model. The abnormality calculation unit (104) calculates and outputs a centrality degree which indicates a degree to which a first metric is estimated to be center of distribution of correlation destruction on the basis of a correlation destruction degree of one or more correlations between each of one or more second metrics having a correlation with the first metric and each of one or more metrics other than the first metric among the plurality of metrics.
    Type: Application
    Filed: January 22, 2013
    Publication date: January 22, 2015
    Applicant: NEC CORPORATION
    Inventor: Kentaro Yabuki
  • Patent number: 8938383
    Abstract: Apparatus and method for allowing a test script to be played back correctly in a locale of different test language. The invention uses a synonymy dictionary storing the different appearances of the property value of a property in an object of a software product to be tested in different test locales; and compares the property value of the property in the object of the software product to be tested to the corresponding property value pre-recorded in a test script to detect whether they match each other.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Min Ding, Chi Qi, Xiao Bin Yang
  • Publication number: 20150019913
    Abstract: A device may receive a first alert from a first technology layer of an information technology system. The first alert may be associated with an occurrence of a first event within the first technology layer. The device may receive a second alert from a second, different technology layer of the information technology system. The second alert may be associated with an occurrence of a second event within the second technology layer. The device may determine that the first alert is related to the second alert. The device may generate, based on the first alert being related to the second alert, a third alert that includes information associated with the first alert and information associated with the second alert. The device may provide the third alert to at least one of the first technology layer or the second technology layer.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Inventors: Shivinder SINGH, Sojan JOSEPH, Krishna REDDY
  • Publication number: 20150019914
    Abstract: Embodiments relate to testing of a computing system using a base protocol layer testing device. An aspect includes, based on determining, by the base protocol layer testing device, that a current test comprises a test of a base protocol layer of the computing system, enabling a low level test assist device of the base protocol layer testing device for the current test, wherein the low level test assist device comprises a hardware device that is directly attached to an input/output (I/O) card of the computing system. Another aspect includes storing base protocol layer traffic that passes through the I/O card by the low level test assist device during performance of the current test by the base protocol layer testing device. Yet another aspect includes analyzing the stored base protocol layer traffic after completion of the current test to determine a result of the current test.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Inventors: Tara Astigarraga, Louie A. Dickens, Carlos J. Lujan, Daniel J. Winarski
  • Publication number: 20150012781
    Abstract: A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.
    Type: Application
    Filed: July 30, 2014
    Publication date: January 8, 2015
    Applicant: TRW Automotive U.S. LLC
    Inventor: Kerfegar K. Katrak
  • Patent number: 8930761
    Abstract: A computer-implemented method for test case result processing includes receiving, by a test case result processing logic in a processor of a computer, a test result from a test case that executes on the computer; determining, by the test case result processing logic based on a result description file, whether a result description corresponding to the received result exists in the result description file; based on the result description corresponding to the received result existing in the result description file, determining an action description associated with the result description based on an action definition file; and executing an action corresponding to the determined action description.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joel L. Masser, David C. Reed, Max D. Smith
  • Patent number: 8930762
    Abstract: The tracking of cluster-wide connectivity information is optimized. I/O errors that result from failed operations in which specific nodes attempt to access shared storage are detected. The start-times of failed operations are tracked. The tracked start-times are compared to the time at which the cluster-wide connectivity information was last updated. Responsive to the results of the comparing, the cluster-wide connectivity information is updated in response only to a single I/O error that results from a single failed operation that was initiated after the update time, wherein additional errors resulting from failed operations with start-times after the update time are also detected, thereby preventing redundant updates of the cluster-wide connectivity information. The update time is set to the time at which the cluster-wide connectivity information is updated.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Symantec Corporation
    Inventors: Prasanta Dash, Chaitanya Yalamanchili
  • Publication number: 20150006960
    Abstract: An operations management apparatus, includes a correlation model storing unit which stores a correlation model including one or more correlation functions each of which indicates a correlation between pieces of sequence information out of a plural types of sequence information, for each of plural monitored objects and a correlation destruction detecting unit which detects correlation destruction related to a correlation which is included in said correlation model by applying inputted said sequence information of said monitored object to said correlation model of said monitored object which said correlation model storing unit stores; and a fault analyzing unit which determines and outputs said monitored object through comparing results of judging whether detecting or not detecting said correlation destruction related to a common correlation in said monitored objects which have said correlation models including said common correlation.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 1, 2015
    Applicant: NEC Corporation
    Inventor: Kentarou Yabuki
  • Publication number: 20150006961
    Abstract: A computer identifies a first trace output, generated during a first execution of a first program, that is annotated with an indication of a first pattern of logged events and one or more second programs that identify additional logged events. The computer identifies the first pattern of logged events in a second trace output, which is generated during a second execution of the first program. The computer executes the one or more second programs to gather one or more additional logged events that are discoverable during the second execution of the first program, wherein the one or more additional logged events are not included in the first trace output.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 1, 2015
    Inventors: Donald A. Bourne, Albert A Chung, Dana L. Price
  • Patent number: 8924797
    Abstract: At least one value of abnormal metrics is identified as being an abnormal dimension value. A dominant dimension related to the anomaly is identified based on the identified abnormal dimension value.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Hewlett-Packard Developmet Company, L.P.
    Inventors: Ruth Bernstein, Ira Cohen
  • Publication number: 20140380100
    Abstract: A monitoring system performs cause analysis of an event occurring in any of a plurality of monitoring-target objects to be monitored based on a rule. In this case, the monitoring system makes a detection during the analysis time width and determines a plurality of conclusions based on an event corresponding to the condition for determining the conclusion. Moreover, the monitoring system performs one or more of (A) displaying change of certainty to be used for determination of a conclusion in a case where the analysis time width is assumed to be changed, (B) performing sort display of the determined conclusion based on an index value showing an affected range and (C) calculating the analysis time width based on the index value.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventors: Atsushi MIKAMI, Takaki KURODA
  • Publication number: 20140380099
    Abstract: Embodiments relate to testing of a computing system using a base protocol layer testing device. An aspect includes, based on determining, by the base protocol layer testing device, that a current test comprises a test of a base protocol layer of the computing system, enabling a low level test assist device of the base protocol layer testing device for the current test, wherein the low level test assist device comprises a hardware device that is directly attached to an input/output (I/O) card of the computing system. Another aspect includes storing base protocol layer traffic that passes through the I/O card by the low level test assist device during performance of the current test by the base protocol layer testing device. Yet another aspect includes analyzing the stored base protocol layer traffic after completion of the current test to determine a result of the current test.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Applicant: International Business Machines Corporation
    Inventors: Tara Astigarraga, Louie A. Dickens, Carlos J. Lujan, Daniel J. Winarski
  • Patent number: 8918678
    Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eli Almog, Olaf K. Hendrickson, Christopher A. Krygowski
  • Publication number: 20140372803
    Abstract: The present invention relates to an apparatus and method that analyze the problems of abnormal states in a component-based system in which embedded systems including an autonomous control function are operated. In the method, an apparatus for analyzing abnormal states of a component-based system models, interaction between components, and creates an interaction model. An incoming/outgoing message table corresponding to the interaction model is generated. A state table to be used to identify state changes between the components and an analysis table to be used to analyze other components associated with one component are generated based on the incoming/outgoing message table. A knowledge template of a target system is generated based on the state table and analysis table. Each component is monitored by applying constraint conditions of the component to the knowledge template of the target system, and states of the component are detected based on results of monitoring.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 18, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Min PARK, Sung-Joo KANG, In-Geol CHUN, Won-Tae KIM
  • Publication number: 20140372802
    Abstract: A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 1018 floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect a computing component failure, memory element failure and/or an interconnect failure through an automated comparison of signal trajectories generated by the chaotic maps.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventor: Nageswara S. Rao
  • Publication number: 20140372805
    Abstract: A system comprising at least one controller including a controller processor with a memory configured to execute self-healing rules. The self-healing rules may include at least one corrective measure and at least one failure symptom. The system may include an automated incident management device including a central processor with a memory to receive service management information from the at least one controller, correlate at least one corrective measure with at least one failure symptom, adjust the self-healing rules based on the correlation, and propagate the adjusted self-healing rules to the at least one controller.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 18, 2014
    Inventors: Jan Marcel Rijnders, Neil Ronketti, Christopher A. Kimm
  • Publication number: 20140372804
    Abstract: A system and method for remote maintenance of user units allows efficient diagnosis of failures in a reduced time. Each user unit transmits to a management server, via a network, state data related to hardware and software parameters associated to an operating mode of the user unit. The method includes: storing state data in a user unit memory, monitoring state data stored in the memory, and detecting at least one datum of a state indicating an operational failure of the user unit. When a failure is detected, state data corresponding to current states of the user unit at the moment of the failure and state data corresponding to states stored during a predetermined period before the failure are extracted and transmitted to the management server which determines a statistic correlation coefficient between the values of each state of a user unit and the values of states of other user units.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 18, 2014
    Inventor: Alain DELPUCH
  • Patent number: 8914757
    Abstract: A method, system and product for explaining illegal combinations in combinatorial models. The method comprising obtaining a combinatorial model and an illegal combination that is excluded from the model by one or more restrictions, utilizing a Satisfiability solver on a satisfiability formula that encodes the legal test space and that assigns values to attributes as defined by the illegal combination, whereby the satisfiability solver provides an indication of unsatisfiability of the satisfiability formula and an UNSAT core comprising a subset of clauses defined by the satisfiability formula which are unsatisfiable; and identifying the one or more restrictions by mapping the clauses of the UNSAT core with clauses encoding the set of restrictions.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sharon Keidar-Barner, Itai Yosef Segall, Rachel Tzoref-Brill
  • Patent number: 8914678
    Abstract: A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Robert Daniel Brummayer