Memory Or Storage Device Component Fault Patents (Class 714/42)
  • Patent number: 10817363
    Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Marco Redaelli
  • Patent number: 10816596
    Abstract: A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Woo Kim, Chang-Ho Lee, Jin-Ho Choi
  • Patent number: 10795748
    Abstract: Tailoring diagnostic information specific to current activity of multiple threads within a computer system. A request to dump system state is received. A system dump is created, including main memory and system state information. The system dump is stored to a database. In response to a request to format the system dump, the system dump is loaded from the database, whereby a virtual memory image of system state at system dump time is created. The virtual memory image and system state information is scanned to identify tasks that were running, tasks that have failed due to an error, and tasks that were suspended at system dump time. State information and control blocks associated with the identified tasks are collected from the system dump and collated based on task number. The database is updated with a formatted system dump, including the state information and control blocks associated with the identified tasks.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Edward A. Addison, Darren R. Beard, William J. Bulfin, Peggy A. DeVal, James A. Harrison, Manuela Mandelli, John S. Tilling, Andrew Wright
  • Patent number: 10785301
    Abstract: A network storage appliance comprises solid state disks, a network interface adapter communicatively coupled to the solid state disks and a host client, a non-volatile semiconductor memory device communicatively coupled to the solid state disks and the network interface adapter, and a CPU communicatively coupled to the non-volatile semiconductor memory device and the network interface adapter. The non-volatile semiconductor memory device can receive data from the host client via the network interface adapter, store the data temporarily, and transfer the data to one of the solid state disks.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yaron Klein
  • Patent number: 10776384
    Abstract: A method of replicating changes to a dataset includes receiving from a client a request for an operation on the dataset, dynamically selecting from a plurality of replication assurance policies a selected replication assurance policy for the operation, the selected replication assurance policy determining a selected assurance level, wherein the selection is based on at least one of an operation criteria or a connection criteria, submitting, to a first replica of the dataset, a command comprising the operation, and reporting to the client the result of the operation according to the selected assurance level.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: September 15, 2020
    Assignee: Ping Identity Corporation
    Inventors: Patrick Edward Jackson, David Michael Ely, Bjorn Aannestad
  • Patent number: 10776027
    Abstract: Provided herein may be a storage device and a method of operating the same. The storage device for additionally securing an over-provisioning area may include at least one memory device, each including first memory blocks and second memory blocks, and a memory controller configured to store system data, stored in the first memory blocks of the at least one memory device, in the second memory blocks when a size of a residual space in a memory area of the at least one memory device is less than a threshold.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Ji Hoon Lee
  • Patent number: 10769016
    Abstract: A method for execution by a dispersed storage and task (DST) client module includes obtaining a plurality of sorted data entries. A data access performance goal level associated with the plurality of sorted data entries is obtained, and obtaining DSN performance information is obtained. Compression parameters are selected based on the data access performance goal level and the DSN performance information. Sorted data entries of the plurality of sorted data entries are selected based on the selected compression parameters to produce a data object. The data object is compressed to produce a compressed data object using the selected compression parameters. The compressed data object is dispersed storage error encoded to produce one or more sets of encoded data slices for storage in a set of storage units.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 8, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Jason K. Resch, Greg R. Ohuse
  • Patent number: 10733073
    Abstract: An instruction to perform load testing is sent to a mobile device where an application running on the mobile device determines whether the mobile device is in a state where load testing is permitted. In response to receiving the instruction, the application running on the mobile device performs load testing on a web server if the mobile device is in the state where load testing is permitted. Performance information associated with the load testing is received from the application running on the mobile device and the performance information associated with the load testing is displayed.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 4, 2020
    Assignee: Neocortix, Inc.
    Inventors: Donald Lloyd Watts, Dmitry Moskalchuk
  • Patent number: 10705931
    Abstract: Embodiments of the present disclosure relate to methods, devices and computer readable mediums for managing a storage system. The storage system includes a disk array which includes at least one disk array group. The method comprises in response to receiving a first message indicating that a failure occurs in a disk in the disk array, determining first information on a disk array group that the failed disk belongs to. The method further comprises obtaining a first number of outstanding input/output (I/O) operations on rebuilding the failed disk in the disk array group. The method further comprises determining, based on the first information and the first number, a threshold number of I/O operations that is applicable for the disk array group. In addition, the method further comprises controlling, based on the threshold number, the number of I/O operations initiated to the disk array group.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: July 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Lifeng Yang, Xinlei Xu, Jian Gao, Jibing Dong, Geng Han
  • Patent number: 10705901
    Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor that receives the interrupts, accumulates a count of the interrupts, and provides an error indication when the count exceeds an error threshold. The failure predictor receives a first in time interrupt, suspends the accumulation of the count for a first duration of time in response to receiving the first in time interrupt, and resumes the accumulation of the count. In resuming the accumulation of the count, the failure predictor increments the count each time the predictor receives a first subsequent interrupt and decrements the count in accordance with an error leak rate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Dell Products, L.P.
    Inventors: Amit S. Shah, Tuyet-Huong Thi Nguyen, James R. Pledge, Vadhiraj Sankaranarayanan
  • Patent number: 10685009
    Abstract: A computerized system and method may include, in response to receiving a blockchain via a communications network that includes information associated with an event, parsing, by a blockchain parsing engine being executed by a blockchain node, the information to identify a status state of an item related to the event. The blockchain may be inclusive of the information along with the status state of the item may be stored in a storage unit. An event tracking engine may determine from the parsed information that the status state of the item transitioned from a first state to a second state. Responsive to the event tracking engine determining that a qualifying state is satisfied by the item being in the second state, automatically executing, by the blockchain node, a smart code inclusive of initiating communications between a first party and a second party.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 16, 2020
    Assignee: Massachusetts Mutual Life Insurance Company
    Inventors: Jennifer Rutley, Abigail Jennings O'Malley
  • Patent number: 10678450
    Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues by determining a soft failure level for the memory device, wherein the soft failure level includes a plurality of discrete usability levels with a highest usability level representing a maximum amount of usable memory, a second usability level representing a lower usability level than the highest usability level and a lowest usability level representing an unusable level when the usable memory is below a threshold. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 9, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Gary W. Grube, Jason K. Resch, Timothy W. Markison, Ilya Volvovski, Manish Motwani
  • Patent number: 10679221
    Abstract: A computerized system and method may include, in response to receiving a blockchain via a communications network that includes information associated with an event, parsing, by a blockchain parsing engine being executed by a blockchain node, the information to identify a status state of an item related to the event. The blockchain may be inclusive of the information along with the status state of the item may be stored in a storage unit. An event tracking engine may determine from the parsed information that the status state of the item transitioned from a first state to a second state. Responsive to the event tracking engine determining that a qualifying state is satisfied by the item being in the second state, automatically executing, by the blockchain node, a smart code inclusive of initiating communications between a first party and a second party.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 9, 2020
    Assignee: Massachusetts Mutual Life Insurance Company
    Inventors: Jennifer Rutley, Abigail Jennings O'Malley
  • Patent number: 10659426
    Abstract: A method and a system and computer readable medium configured to perform and store the method for providing domain registry services is provided. The method includes receiving, at a domain registry comprising at least one electronic server computer, a first domain request from a registrar, wherein the first domain request comprises a first extensible provisioning protocol (“EPP”) command to perform a first action on a first domain name associated with a first pool of network resources; accessing, by at least one electronic processor, an electronically stored first policy, wherein the first policy comprises connection and throughput parameters for the registrar to access the first pool of network resources; applying, by at least one electronic processor, the first policy to the first domain name request; and providing, by at least one electronic processor, a first response to the first domain request.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 19, 2020
    Assignee: VERISIGN, INC.
    Inventor: James Gould
  • Patent number: 10649799
    Abstract: A hypervisor virtual server system, including a plurality of virtual servers, a plurality of virtual disks that are read from and written to by the plurality of virtual servers, a physical disk, an I/O backend coupled with the physical disk and in communication with the plurality of virtual disks, which reads from and writes to the physical disk, a tapping driver in communication with the plurality of virtual servers, which intercepts I/O requests made by any one of said plurality of virtual servers to any one of said plurality of virtual disks, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted I/O write requests from the tapping driver, and that provides data services based thereon.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: May 12, 2020
    Assignee: Zerto Ltd.
    Inventor: Ziv Kedem
  • Patent number: 10644874
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by performing a key derivation function on a password to produce a key and issuing a set of blinded passwords to a set of storage units, where the blinded passwords are generated based on the key. The method continues by receiving at least a decode threshold number of confidential information responses, where each of the confidential information responses includes an encrypted encoded data slice and an associated passkey, regenerating a set of keys using the associated passkeys of the confidential information, decrypting a set of encrypted slices of the confidential information using the set of keys to reproduce a set of encoded data slices, and dispersed storage error decoding a decode threshold number of the set of reproduced encoded data slices to produce recovered data.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 5, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Greg R. Dhuse, Bart R. Cilfone
  • Patent number: 10613936
    Abstract: A method for a dispersed storage network (DSN) begins by encoding a data segment of data to produce a set of encoded data slices including an information dispersal algorithm (IDA) width number of encoded data slices. The method continues by determining a number of storage locations, where the number of storage locations is less than the IDA width number, combining, for each storage location, a portion of at least two encoded data slices of the set of encoded data slices to produce a combined slice and sending the combined slice to the storage location for storage. When retrieving the data, the method includes combining slices associated with a set of encoded data slices, de-combining the combined slice, aggregating portions of common encoded data slices and decoding a decode threshold number of the encoded data slices of the set of encoded data slices to produce a recovered data segment.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 7, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Niall J. McShane, Jason K. Resch
  • Patent number: 10606481
    Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinken Okamoto
  • Patent number: 10592326
    Abstract: A method, including receiving, by a secure processor housed in a disaster-proof casing located at a local site, recurring wireless signals from an application server and from a storage system that are collocated with the processor at the local site, the application server configured to store data to the primary storage system, and to mirror the data to a remote site, each of the wireless signals indicating a status of the application server or the storage system at a given time. A status log including the respective statuses of the application server and the storage system at the received times is stored to a memory in the casing, and subsequent to failures of the application server, the storage system and the mirroring, the status log analyzed to compute a data loss at the local site resulting from the failures of the application server, the storage system, and the mirroring.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 17, 2020
    Assignee: AXXANA (ISRAEL) LTD.
    Inventor: Alex Winokur
  • Patent number: 10579275
    Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 3, 2020
    Assignee: HITACHI, LTD.
    Inventors: Akihiko Araki, Yusuke Nonaka, Noboru Morishita
  • Patent number: 10564884
    Abstract: Migrating data in a storage array that includes a plurality of storage devices, including: detecting, by the storage array, an occurrence of a storage device evacuation event associated with one or more source storage devices; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage array, one or more target storage devices for receiving data stored on the one or more source storage devices; reducing, by the storage array, write access to the one or more source storage devices; and migrating the data stored on the one or more source storage devices to the one or more target storage devices.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 18, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Andrew Kleinerman, Benjamin Scholbrock, Taher Vohra, Xiaohui Wang
  • Patent number: 10552261
    Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Hashizume, Naoya Fujita, Shunya Nagata, Yoshisato Yokoyama, Katsumi Shinbo, Kouji Satou
  • Patent number: 10545485
    Abstract: A method for controlling a plurality of machines and at least a first assembly; the plurality of machines comprises at least a first machine and a second machine; the first assembly is associated with the first and second machines and is arranged to provide a first auxiliary function to the first and second machines; control is carried out by at least a first and a second controllers; the first and the second controllers are associated respectively to the first and second machines and are arranged to control a main function of each of the first and the second machines; the first and the second controllers are associated with the first assembly and are arranged to control an auxillary function of the first assembly; the first and the second controllers maintain a dialog between each other to assure that only one controller controls the first assembly at a time.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: January 28, 2020
    Assignee: Nuovo Pignone S.P.A.
    Inventors: Marco Lisco, Giulio Guaglianone
  • Patent number: 10528288
    Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, John B. DeForge, Warren E. Maule, Kirk D. Peterson, Sridhar H. Rangarajan, Saravanan Sethuraman
  • Patent number: 10528422
    Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 7, 2020
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
    Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
  • Patent number: 10467160
    Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Xiang Li, Yunhui Chu, Jun Liao, George Vergis, James A. McCall, Charles C. Phares, Konika Ganguly, Qin Li
  • Patent number: 10448438
    Abstract: According to one embodiment, a computer program embodied on a tangible computer readable medium includes computer code for identifying a wireless communications gateway in communication with a management controller, computer code for establishing a wireless communications connection between one or more drives and the management controller, utilizing the wireless communications gateway, and computer code for communicating one or more of monitoring data and control data between the management controller and the one or more drives, utilizing the wireless communications connection.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Pravin Patel, Theodore Brian Vojnovich, Patrick Leo Caporale, Mark E. Andresen
  • Patent number: 10437489
    Abstract: A memory system may include: a memory device comprising: a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing data; a plurality of memory blocks each having the pages; a plurality of planes each having the memory blocks; and a plurality of memory dies each having the planes, and a controller suitable for transmitting a request command for acquiring setting information on the memory device to the memory device, receiving an acknowledgement signal corresponding to the request command from the memory device, acquiring the setting information through the acknowledgement signal, and checking the setting information to perform a command operation based on a command received from a host on the memory device.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Gi-Pyo Um
  • Patent number: 10437311
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pierce I. Chuang, Divya Pathak, Phillip J. Restle, Christos Vezyrtzis
  • Patent number: 10432550
    Abstract: A method, apparatus and device for scheduling resources of a cluster comprising a plurality of hosts, each running at least one instance, including acquiring a resource parameter of the cluster; calculating the number of predicted hosts in the cluster according to the resource parameter; determining to-be-migrated hosts and target hosts from the current hosts in the cluster when the number of current hosts in the cluster is greater than the number of predicted hosts; and migrating instances running on the to-be-migrated host to the target host.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 1, 2019
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Yunyang Zhang, Huining Yan, Meng Li, Hongbin Xu
  • Patent number: 10410738
    Abstract: According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsuo Shono, Katsuhiko Ueki
  • Patent number: 10402254
    Abstract: Systems and methods for real-time storage drive monitoring are described. In one embodiment, the method may include monitoring one or more aspects of a storage drive located in a storage enclosure, detecting, based at least in part on the monitoring, an anomaly in relation to an operation of the storage drive, and communicating information regarding the anomaly to a remote computing device.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 3, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Ashish Virmani
  • Patent number: 10402560
    Abstract: Methods, systems, and computer program products for selecting a virtual machine to perform a task corresponding to a client request and performing the task at the virtual machine. After performing the task at the virtual machine, an indicator corresponding to a shutdown of the virtual machine is detected. After detecting the indicator and prior to the shutdown of the virtual machine, a memory space is preserved corresponding to the virtual machine. The preserved memory space is then scanned for malware.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 3, 2019
    Assignee: RED HAT, INC.
    Inventor: David Gilbert
  • Patent number: 10394645
    Abstract: Techniques are provided for correcting the operational state of a multi-process system without disrupting any running processes. A library providing error correction and logging functionality is statically linked to modules in the system. A script in the library loads a package file having a patch for returning an error state to a normal state. The script issues commands to invoke functions in the patch. Once the error state has returned to a normal state, the script issues commands to remove the package file from the system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 27, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Kashyap Merchant, Srinivas Pitta
  • Patent number: 10394634
    Abstract: Apparatuses, systems and methods are disclosed herein that generally relate to distributed storage, such as for big data, distributed databases, large datasets, artificial intelligence, genomics, or any other data processing environment using that host large data sets or utilize big data hosts using local storage or storage remotely located over a network. More particularly since large scale data requires many storage devices, scrubbing storage for reliability and accuracy requires communication bandwidth and processor resources. Discussed are various ways to use known storage structure, such as LBA, to offload scrubbing overhead to storage by having storage engage in autonomous self-validation. Storage may scrub itself and identify stored data failing data integrity validation, or identify unreadable storage locations, and report errors to a distributed storage system that may reverse-lookup the affected storage location to identify, for example, a data block at that location needing correction.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Anjaneya R. Chagam Reddy
  • Patent number: 10395688
    Abstract: Implementations generally relate to storage systems. In one implementation, a system includes a plurality of storage libraries that store a plurality of removable media units. The system also includes a plurality of head units for reading and writing to one or more of the removable media units. The system also includes a plurality of robots that transfer one or more of the removable media units between one or more of the storage libraries and one or more of the head units. The system also includes enabling one or more of the robots to recover a set of data from two or more of the removable media units if a failure occurs in association with at least one of the other removable media units.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 27, 2019
    Assignee: SONY CORPORATION OF AMERICA
    Inventors: Giovanni Coglitore, Ando Hideki, Horst Schellong
  • Patent number: 10380058
    Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 13, 2019
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Daniel Fowler, Rishabh Jain, Erik Schlanger, Michael Duller
  • Patent number: 10365839
    Abstract: According to certain aspects, an information management cell can include at least one secondary storage computing device configured to conduct primary data generated by at least one client computing device to a secondary storage device(s) as part of secondary copy operations, wherein the secondary storage computing device normally operates to conduct primary data to the secondary storage device(s) for storage as a secondary copy in a first secondary copy file format, at the direction of a main storage manager; and can include a failover storage manager configured to activate in response to loss of connectivity between the cell and the main storage manager, and instruct a secondary copy application to perform a secondary copy operation in which the primary data generated by the at least one client computing device is stored as a secondary copy in a second secondary copy file format different than the first secondary copy file format.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Parag Gokhale, Rajiv Kottomtharayil, Amey Vijaykumar Karandikar, Manoj Kumar Vijayan
  • Patent number: 10331191
    Abstract: Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 25, 2019
    Assignee: Empire Technology Development, LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 10331902
    Abstract: Techniques for providing data loss prevention, including data exfiltration prevention and crypto-ransomware prevention, are provided. In some embodiments, a slack-space file system is created by using a modified packing algorithm to increase and/or optimize an amount of slack space created by files stored in a standard file system. A program for accessing and indexing the slack-space file system may be stored, and requests by a user to store data on a storage medium of a computer system may cause the information to be stored in the slack-space file system, where it may be protected from destructive malware that operates solely on the standard file system. In some embodiments, sensitive information may be hidden by storing the information in an alternate data stream of a file and by replacing the information in the unnamed data stream of the file with non-sensitive information that may appear to be sensitive.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: NOBLIS, INC.
    Inventors: Matthew K. Monaco, Daniel Negron, Brian Satira
  • Patent number: 10324780
    Abstract: For efficient data system error recovery, an error threshold is dynamically adjusted from a default error threshold to one of a plurality of error threshold values comprising at least high threshold values, medium threshold values, and low threshold values, for a particular error associated with an event object indicating a responsive action for handling the particular error in a data system. The responsive action to the event object comprises determining whether the error threshold needs to be adjusted for the particular error, and if it is determined the error threshold for the particular error does not need adjustment, the default error threshold is used.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herve G. P. Andre, Larry Juarez, Brian A. Rinaldi, Todd C. Sorenson, Liang H. Wu
  • Patent number: 10324782
    Abstract: A hiccup management scheme for use within a storage system can maintain low latency on client I/O when a storage device is temporarily unavailable. In some embodiments, a storage using uses double parity data protection can tolerate concurrent hiccups by up to two storage devices within a storage array.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC Corporation
    Inventors: Eli Dorfman, Tal Ben-Moshe, David Krakov, Noa Cohen, Niko Farhi, Roman Vainbrand
  • Patent number: 10297335
    Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10289489
    Abstract: Technology is provided for updating a data set at a data storage system. In an example storage system, the system stores a data set in a plurality of data storage devices. The system stores parity data at a plurality of parity devices. The system receives update data from a client system for a first section of the data set. The system generates updated parity data based on an original version of the first section of the data set and the update data. The system transmits update parity data to the plurality of parity devices. The system receives update notifications from a plurality of parity devices. The system determines that update notifications have been received from at least a threshold number of parity devices in the plurality of parity devices. In response, the system updates the first section of the data set at the leader data storage device.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Arman Fazeli Chaghooshi, Lluis Pamies-Juarez, Cyril Guyot, Robert Eugeniu Mateescu
  • Patent number: 10284645
    Abstract: Various systems and methods for backing up multiplexed backup data streams from a Network Attached Storage (NAS) device to a sequential access media device are disclosed. One such method involves creating multiple identities of the sequential access media device on a server. A portion of a memory of the server is allocated to each respective identity of the sequential access media device. A backup data stream from the NAS device is written to each allocated portion of the memory. Data written to each allocated portion of the memory is multiplexed for transmission to the sequential access media device for storage.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: May 7, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Alioune Thiam
  • Patent number: 10282265
    Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas P. Grosser, Gerrit Koch, Ralf Winkelmann
  • Patent number: 10248561
    Abstract: The disclosed embodiments provide a system that detects anomalous events in a virtual machine. During operation, the system obtains time-series garbage-collection (GC) data collected during execution of a virtual machine in a computer system. Next, the system generates one or more seasonal features from the time-series GC data. The system then uses a sequential-analysis technique to analyze the time-series GC data and the one or more seasonal features for an anomaly in the GC activity of the virtual machine. Finally, the system stores an indication of a potential out-of-memory (OOM) event for the virtual machine based at least in part on identifying the anomaly in the GC activity of the virtual machine.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Dustin R. Garvey, Sampanna S. Salunke, Lik Wong, Xuemei Gao, Yongqiang Zhang, Eric S. Chan, Kenny C. Gross
  • Patent number: 10228990
    Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 12, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yiwei Song, Nian Niles Yang, James Fitzpatrick
  • Patent number: 10224115
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • Patent number: 10169152
    Abstract: Data recovery following the loss of a volume manager is described, wherein a volume manager receives a command, and location information and credentials to access a distributed storage. The data to be recovered may include one or more data files stored as one or more discrete portions. Each portion includes metadata, including at least a file ID tag. The volume manager retrieves each portion of data from the distributed storage and records, in an index, the location that each portion of data was retrieved from. The volume manager reads and stores the file ID tag with the associated location of the attached portion of data in the distributed storage in the volume manager index.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Murilo O. Araujo, Ricardo M. Matinata, Rafael P. Sene