Abstract: A method includes receiving, at a controller of a storage device, a command reserving a program slot of a processing device of the storage device to an application. The method further includes storing, by the controller of the storage device, an association between the program slot and the application. The method further includes receiving, at the controller of the storage device, a request to load the application into the execution slot. The method further includes loading, by the controller of the storage device, the application into the program slot based on the association and the request. The method further includes executing, at the processing device of the storage device, the application in the program slot.

Abstract: A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Abstract: A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An electronic device includes a memory and a processor. The processor acquires a platform management profile, the platform management profile including information defining one or more platform management policies. The processor provides the platform management profile to platform management drivers executing on one or more electronic devices, the platform management profile being configured so that each of the platform management drivers can extract the one or more platform management policies from the platform management profile and use the one or more platform management policies for controlling operating states of elements (e.g., functional blocks, devices, etc.) of the respective electronic device.

Abstract: A method, computer program product, and computing system for determining a recovery point object (RPO) value for a storage object. An amount of data to transfer from the storage object to a disaster recovery site is determined. A data replication transfer schedule for the storage object is generated based upon, at least in part, the RPO value and the amount of data to transfer. Data is asynchronously transferred from the storage object to the disaster recovery site using the data replication transfer schedule.

Abstract: Dynamically adjusting an amount of log data generated for a storage system that includes a plurality of storage devices, including: detecting that a value for a performance-related characteristic of a component of a storage system has reached a performance threshold, and based on the detection, changing an extent to which log data should be generated for the component.

Abstract: A system for evaluating manufactured items that includes a memory module; an evaluation unit configured to execute instructions related to the evaluating of the manufactured items while applying a group of features; and a memory leakage unit configured to: select a first feature out of the group of features and disable an execution, by the evaluation unit, of instructions associated with the first feature at a presence of a memory leakage event. The first feature has a priority that is lower than a priority of a second feature of the group of feature. Priorities of features of the group of features are determined based on (i) priority information provided by one or more developers of the instructions related to the evaluating of the manufactured item, and (ii) usage information indicative of usage of the features of the group of features by the evaluation unit.

Abstract: According to one embodiment, a computer-implemented method, a computer system, and a computer program product for data maintenance is provided. The present invention may include receiving, by one or more processing units, a maintenance request for a first data set stored in a first non-transient storage; copying, by one or more processing units, the first data set into a second non-transient storage as a second data set during a copy phase in response to receiving the maintenance request; writing, by one or more processing units, update content indicated by an update request to the first data set into a first transient memory in response to receiving the update request during the copy phase; and updating, by one or more processing units, the second data set based on the written update content in the first transient memory during a write-back phase responsive to a completion of the copy phase.

Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

Abstract: Embodiments of the present disclosure relate to a method, system and computer program product for trace data protection. In some embodiments, a method is disclosed. According to the method, a target task is determined from a plurality of tasks, where trace data of the target task is to be protected. The trace data of the target task is transferred from a first area to a second area of a memory. Existing trace data in the second area is offloaded to a storage device before being overwritten. In other embodiments, a system and a computer program product are disclosed.

Abstract: A method for operating a performance optimization device of memory system is provided, the method including determining N, where N is a natural number greater than 0, candidate performance parameter values for a performance parameter of the memory system; calculating N objective function results for an objective function defined for the memory system; and determining an additional candidate performance parameter value for the performance parameter of the memory system, based on the N candidate performance parameter values and the N objective function results.

Abstract: The present disclosure generally relates to validating memory devices. Rather than using debug hardware (HW) to consume, record, and decode firmware (FW) events, standard non-volatile memory express (NVMe) asynchronous event request (AER) and NVMe asynchronous event notification (AEN) is used. The NVMe AER results in initiating a particular function to be performed by a device under test (DUT) and triggering a cross feature (CF) that should at least partially overlap in time with the particular function. Using NVMe AER and AEN will eliminate the need for debug HW, reduce FW custom logic, and reduce latency.

Abstract: Managing PCIe slots, including identifying a table, stored at a database, indicating, for each PCIe card, a number of PCIe slots to be designated as inaccessible to other PCIe cards; detecting coupling of a particular PCIe card to a particular PCIe slot; accessing, in response to detecting the coupling of the particular PCIe card to the particular PCIe slot, the table; determining, based on the accessing, that the table includes data indicating the particular PCIe card; identifying, based on determining that the table includes data indicating the particular PCIe card, the number of PCIe slots adjacent to the particular slot to be designated as inaccessible to other PCIe cards; adjusting, based on the number of PCIe slots adjacent to the particular slot to be designated as inaccessible to other PCIe cards, a power state of one or more PCIe slots adjacent to the particular PCIe slot to an off-power state.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Systems and methods to throttle a universal backup host are described. The system receives responses, over a network, corresponding to one or more requests by utilizing one or more threads from a thread pool. The threads include a first thread. The requests include a first request. The receiving the responses includes receiving a first response corresponding to the first request by utilizing the first thread, the first response includes a first metadata item. The system processes the responses by generating a first latency based on the first response and incrementing a number for registering requests based on the first response. Next, the system aggregates samples. The samples include the first latency and the number of requests. Next, the system resizes the thread pool based on the aggregating and backs up the file set from the source host based on the metadata.

Abstract: Aspects of this disclosure provide a data backup method and apparatus, a server, and a non-transitory computer-readable storage medium, belonging to the field of data database technologies. The method can include receiving a backup task that is used for backing up a data item of a target data table. The method can further include obtaining a first snapshot difference between a first historical transaction snapshot and a second historical transaction snapshot when a backup time of the backup task is a historical time period. The first historical transaction snapshot and the second historical transaction snapshot can be transaction snapshots respectively located at a start moment and an end moment of the historical time period. Additionally, the method can include performing the backup task based on the first snapshot difference to obtain backup data including at least a visible version of the data item in the target data table.

Abstract: An implementation is for one or more hardware-based non-transitory memory devices storing computer-readable instructions which, when executed by the one or more processors disposed in a computing device, cause the computing device to monitor a logic block and a memory block to detect a fault condition, determine a subset of the logic block or the memory block that is impacted by the fault condition, and perform at least one action on the logic block and the memory block.

Abstract: Implementations of the present disclosure provide a system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includes a memory controller, having a processor and a memory, operatively coupled to the array of memory cells. The system further includes a host, having another processor and another memory, operatively coupled to the memory controller. The other processor of the host is configured to perform a first RAID encode operation on memory data to form first parity data. The processor of the memory controller is configured to receive the first parity data and the memory data, and perform a second RAID encode operation on the first parity data and the memory data to form second parity data.

Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

Abstract: Methods, systems, and devices for predictive media management for read disturb are described. A read disturbance manager can monitor a bit error rate for a block of a memory die. The read disturbance manager can detect that a degradation of the bit error rate satisfies a degradation threshold specific to the memory die. In some cases, the read disturbance manager can perform a write operation to write data from the block of the memory die to a second block of the memory die based on detecting that the degradation of the bit error rate satisfies the degradation threshold.

Abstract: The present application provides a method and a system for calculating a stripe of a strip for a disk, a terminal and a storage medium. The method includes: calculating a pack offset of a parity block according to a given disk index; calculating an address of a strip where the parity block is located in the disk according to the pack offset; comparing an address of a to-be-checked strip with the address of the strip where the parity block is located in the disk to determine whether the parity block is on the to-be-checked strip; and calculating a stripe index of the to-be-checked strip by considering redundant elements caused by the parity block in response to determining that the parity block is on the to-be-checked strip; or calculating the stripe index of the to-be-checked strip directly in response to determining that the parity block is not on the to-be-checked strip.

Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair regions in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair region by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair region is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.

Abstract: A storage system includes a central storage controller and a solid-state storage device operatively coupled to the central storage controller, the solid-state storage device including a processing device, the processing device to determine whether a die of the solid-state storage device is likely to fail. In response to determining that the die of the solid-state storage device is likely to fail, the processing device is further to mark the die of the solid-state storage device as likely to fail and transmit, to the central storage controller, an indication that the die of the solid-state storage device has been marked as likely to fail.

Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.

Abstract: Embodiments for a system and method of selecting data protection policies for a new system, by collecting user, policy, and asset metadata for a plurality of other users storing data dictated by one or more protection policies. The collected metadata is anonymized with respect to personal identifying information, and is stored in an anonymized analytics database. The system receives specific user, policy and asset metadata for the new system from a specific user, and matches the received specific user metadata to the collected metadata to identify an optimum protection policy of the one or more protection policies based on the assets and protection requirements of the new system. The new system is then configured with the identified optimum protection policy as an initial configuration.

Abstract: Methods, systems, and devices for memory device health evaluation at a host device are described. The health evaluation relates to a host device that is associated with a memory device that monitors and reports health information, such as one or more parameters associated with a status of the memory device. The memory device may transmit the health information to the host device, which may perform one or more operations and may transmit the health information to a device of another entity of a system (e.g., ecosystem) including the host device. The host device may include one or more circuits for transmitting and processing the health information, such as a system health engine, a safety engine, a communication component, or a combination thereof. Based on a determination by the host device or information received from an external device, the host device may transmit a command to the memory device.

Abstract: While a compiler compiles source code to create an executable binary, code is added into the compiled source code that, when executed, identifies and stores in a metadata table base and bounds information associated with memory allocations. Additionally, additional code is added into the compiled source code that performs memory safety checks during execution. This updated compiled source code automatically determines a safety of memory access requests during execution by performing an out-of-bounds (OOB) check using the base and bounds information retrieved and stored in the metadata table. This enables the identification and avoidance of unsafe memory operations during the implementation of the executable by a GPU.

Abstract: Duplication of files in a storage device of a computing device can be avoided using some techniques described herein. In one example, a system can determine a checksum of a file in a software package. The system can then determine that the file is absent from a storage device by issuing a command for accessing the file based on the checksum. In response to determining that the file is absent from the storage device, the system can download a copy of the file from a remote computing device to the storage device over a network.

Abstract: A processor may receive data regarding a reference source code commit. The processor may identify, using an artificial intelligence model, a first group of source code commits including source code commits similar to the reference source code commit, where each source code commit in the first group is associated with a repository. The processor may determine, using the artificial intelligence model, a first risk associated with implementing a first source code commit from the first group of source code commits. The processor may determine an error budget associated with a first repository associated with the first source code commit. The processor may determine a first time for implementing the first source code commit.

Abstract: A memory module system level tester device provides contact between the motherboard and the memory modules by using a test tray, thereby minimizing a time required for attaching and detaching the memory modules and omitting an additional configuration for attaching and detaching the memory modules. Accordingly, space limitations can be minimized, and as a result, test units can be arranged in two or more stages in the vertical direction to configure a compact layout to thereby increase space efficiency.

Abstract: A memory device includes an auto error check scrub (ECS) control circuit configured to generate an auto ECS command for performing an ECS operation based on a refresh control signal. The memory device also includes a burst ECS control circuit configured to generate an internal burst ECS command for performing the ECS operation every set period based on a burst ECS command and an ECS end flag. The memory device further includes an ECS address generation circuit configured to generate an ECS address for the ECS operation by counting an input of the auto ECS command or the internal burst ECS command and to generate the ECS end flag based on a value of the ECS address.

Abstract: A method for managing memory leaks in a memory device includes grouping, by a garbage collection system, a plurality of similar memory allocations of the memory device into one or more Unique Fixed Identifiers (UFIs); identifying, by the garbage collection system, one of the one or more UFIs having a highest accumulated memory size and adding each of the plurality of memory allocations in the identified one of the one or more UFIs into a Potential Leak Candidate List (PLCL); identifying, by the garbage collection system, the memory leaks in the memory device by identifying unreferenced memory addresses associated with the plurality of memory allocations in the PLCL; and releasing, by the garbage collection system, the identified unreferenced memory addresses associated with the plurality of memory allocations corresponding to the memory leaks into the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Abstract: According to one general aspect, a non-transitory computer readable medium includes instructions that, when executed by at least one processor, cause a computing device to read a string of a log file for an application, where the log file comprises multiple strings of log data, compare the string to signatures stored in a memory to find a matching signature, where each of the signatures is encoded with a signature identifier (ID), determine a deviation between the string and the matching signature, encode the string with the signature identifier (ID) of the matching signature and the deviation, and transfer the string to a destination computing device using the signature identifier (ID) of the matching signature, the deviation, and a timestamp of the string.

Abstract: An electronic device for diagnosing a fault of a plurality of external devices is disclosed. The electronic device comprises a communication unit and a processor.

Abstract: Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.

Abstract: A stuck-at fault mitigation method for resistive random access memory (ReRAM)-based deep learning accelerators, includes: confirming a distorted output value (Y0) due to a stuck-at fault (SAF) by using a correction data set in a pre-trained deep learning network, by means of ReRAM-based deep learning accelerator hardware; updating an average (?) and a standard deviation (?) of a batch normalization (BN) layer by using the distorted output value (Y0), by means of the ReRAM-based deep learning accelerator hardware; folding the batch normalization (BN) layer in which the average (?) and the standard deviation (?) are updated into a convolution layer or a fully-connected layer, by means of the ReRAM-based deep learning accelerator hardware; and deriving a normal output value (Y1) by using the deep learning network in which the batch normalization (BN) layer is folded, by means of the ReRAM-based deep learning accelerator hardware.

Abstract: A data storage device includes a memory device having a plurality of blocks and a controller coupled to the memory device. The controller is configured to determine that an uncorrectable error correction code (UECC) failure has occurred to a block of the plurality of blocks, enable a UECC anti-strike mechanism, and erase the block. The UECC anti-strike mechanism comprises converting a read failure associated with the block to an erase failure. The controller is further configured to retire the block upon determining that the erase is unsuccessful.

Abstract: Facilitating outlier object detection in tiered storage systems is provided herein. A system can comprise a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can comprise determining respective parameters associated with objects of a group of objects of a tiered storage system. The respective parameters can comprise at least one of a size, an access percentage, or a cost. The operations also can comprise using the respective parameters associated with the objects of the group of objects as inputs and performing data clustering on the group of objects, resulting in at least one data cluster. Further, the operations can comprise selecting at least one object from the group of objects as at least one outlier object within the tiered storage system based on the at least one data cluster.

Abstract: In one embodiment, a system for managing a virtualization environment comprises a plurality of host machines, one or more virtual disks comprising a plurality of storage devices, a virtualized file server (VFS) comprising a plurality of file server virtual machines (FSVMs), wherein each of the FSVMs is running on one of the host machines and conducts I/O transactions with the one or more virtual disks, and a virtualized file server self-healing system configured to identify one or more corrupt units of stored data at one or more levels of a storage hierarchy associated with the storage devices, wherein the levels comprise one or more of file level, filesystem level, and storage level, and when data corruption is detected, cause each FSVM on which at least a portion of the unit of stored data is located to recover the unit of stored data.

Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.

Abstract: A method includes monitoring temperature characteristics for a plurality of memory components of a memory sub-system and determining that a temperature characteristic corresponding to at least one of the memory components has reached a threshold temperature. The method further includes determining a data reliability parameter for the at least one of the memory components that has reached the threshold temperature, determining whether the determined data reliability parameter is below a threshold data reliability parameter value for the at least one of the memory components that has reached the threshold temperature, and, based on determining that the data reliability parameter for the at least one of the memory components that has reached the threshold temperature is below the threshold data reliability parameter value, refraining from performing a thermal throttling operation.

Abstract: A memory system is provided. The memory system includes at least one memory device, and a controller configured to control the at least one memory device, wherein the controller includes: an error correction circuit configured to correct an error in data read from the at least one memory device, a codeword error counter configured to obtain a syndrome of a current codeword error based on a codeword error occurring in the error correction circuit, and to obtain a weighted codeword error count value by comparing the obtained syndrome with a previous syndrome, and an alert device configured to generate a warning signal for preventing an uncorrectable error of the at least one memory device according to the weighted codeword error count value.

Abstract: A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits. A first OTP register is used to change the scrambling of the secret key value whenever a lifecycle event occurs. A second OTP register is used to undo the change in the scrambling of the secret key. A third OTP register is used to affect a permanent change to the scrambling of the secret key. The scrambled values of the secret key (whether changed or unchanged) are used as seeds to produce keys for cryptographic operations by a device.

Abstract: A method, computer program product, and computer system are provided. An operating system (OS) receives a status at completion of a cryptographic adjunct process (AP) instruction directed to an AP message queue on a cryptographic AP. The status includes a return code, a reason code, a queue full indicator, a queue empty indicator, and the count of enqueued request messages on the AP message queue. The OS determines a number of lost request messages on the AP message queue, based on a count of enqueued request messages on the AP message queue received in the status. The OS re-enqueues the number of lost request messages to the AP message queue. The OS recovers the number of lost request messages on the AP message queue.

Abstract: An information processing apparatus includes a fan that cools a first processor, a dust-proof bezel that prevents dust from entering a casing, a memory, and a second processor coupled to the memory. The second processor is configured to measure a temperature of the first processor and an air volume of an air flow which passes through the dust-proof bezel, compare a registered air volume to the measured air volume when the temperature matches a registered temperature included in comparison information stored in the memory. The registered air volume being included in the comparison information in association with the matched temperature and the comparison information including a registered temperature of the first processor and a registered air volume of an air flow generated by the fan in association with each other. The second processor determines an abnormality in the dust-proof bezel based on a comparison result.

Abstract: A storage device is disclosed. A first storage media may store data. The first storage media may be of a first storage type and may be organized into at least two blocks. A second storage media may also store data. The second storage media may be of a second storage type different from the first type, and may also be organized into at least two blocks. A controller may manage reading data from and writing data to the first storage media and the second storage media. Metadata storage may store device-based log data for errors in the storage device. The drive-based log data may include a first log data for the first storage media and a second log data for the second storage media. An identification circuit may identify a suspect block in the at least two blocks in the first storage media and the second storage media, responsive to the device-based log data.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.

Abstract: Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute device) are disclosed herein. One or more storage events in the data storage subsystem are captured for a specified time period. Statistics are determined from the captured storage events. A visualization of the storage events and statistics for the specified time period is generated.