Memory Or Storage Device Component Fault Patents (Class 714/42)
  • Patent number: 10380058
    Abstract: Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 13, 2019
    Assignee: Oracle International Corporation
    Inventors: David A. Brown, Daniel Fowler, Rishabh Jain, Erik Schlanger, Michael Duller
  • Patent number: 10365839
    Abstract: According to certain aspects, an information management cell can include at least one secondary storage computing device configured to conduct primary data generated by at least one client computing device to a secondary storage device(s) as part of secondary copy operations, wherein the secondary storage computing device normally operates to conduct primary data to the secondary storage device(s) for storage as a secondary copy in a first secondary copy file format, at the direction of a main storage manager; and can include a failover storage manager configured to activate in response to loss of connectivity between the cell and the main storage manager, and instruct a secondary copy application to perform a secondary copy operation in which the primary data generated by the at least one client computing device is stored as a secondary copy in a second secondary copy file format different than the first secondary copy file format.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Parag Gokhale, Rajiv Kottomtharayil, Amey Vijaykumar Karandikar, Manoj Kumar Vijayan
  • Patent number: 10331191
    Abstract: Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 25, 2019
    Assignee: Empire Technology Development, LLC
    Inventor: Miodrag Potkonjak
  • Patent number: 10331902
    Abstract: Techniques for providing data loss prevention, including data exfiltration prevention and crypto-ransomware prevention, are provided. In some embodiments, a slack-space file system is created by using a modified packing algorithm to increase and/or optimize an amount of slack space created by files stored in a standard file system. A program for accessing and indexing the slack-space file system may be stored, and requests by a user to store data on a storage medium of a computer system may cause the information to be stored in the slack-space file system, where it may be protected from destructive malware that operates solely on the standard file system. In some embodiments, sensitive information may be hidden by storing the information in an alternate data stream of a file and by replacing the information in the unnamed data stream of the file with non-sensitive information that may appear to be sensitive.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: NOBLIS, INC.
    Inventors: Matthew K. Monaco, Daniel Negron, Brian Satira
  • Patent number: 10324782
    Abstract: A hiccup management scheme for use within a storage system can maintain low latency on client I/O when a storage device is temporarily unavailable. In some embodiments, a storage using uses double parity data protection can tolerate concurrent hiccups by up to two storage devices within a storage array.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC Corporation
    Inventors: Eli Dorfman, Tal Ben-Moshe, David Krakov, Noa Cohen, Niko Farhi, Roman Vainbrand
  • Patent number: 10324780
    Abstract: For efficient data system error recovery, an error threshold is dynamically adjusted from a default error threshold to one of a plurality of error threshold values comprising at least high threshold values, medium threshold values, and low threshold values, for a particular error associated with an event object indicating a responsive action for handling the particular error in a data system. The responsive action to the event object comprises determining whether the error threshold needs to be adjusted for the particular error, and if it is determined the error threshold for the particular error does not need adjustment, the default error threshold is used.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herve G. P. Andre, Larry Juarez, Brian A. Rinaldi, Todd C. Sorenson, Liang H. Wu
  • Patent number: 10297335
    Abstract: Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: John S. Dodson, Marc A. Gollub, Warren E. Maule, Brad W. Michael
  • Patent number: 10289489
    Abstract: Technology is provided for updating a data set at a data storage system. In an example storage system, the system stores a data set in a plurality of data storage devices. The system stores parity data at a plurality of parity devices. The system receives update data from a client system for a first section of the data set. The system generates updated parity data based on an original version of the first section of the data set and the update data. The system transmits update parity data to the plurality of parity devices. The system receives update notifications from a plurality of parity devices. The system determines that update notifications have been received from at least a threshold number of parity devices in the plurality of parity devices. In response, the system updates the first section of the data set at the leader data storage device.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: May 14, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Arman Fazeli Chaghooshi, Lluis Pamies-Juarez, Cyril Guyot, Robert Eugeniu Mateescu
  • Patent number: 10284645
    Abstract: Various systems and methods for backing up multiplexed backup data streams from a Network Attached Storage (NAS) device to a sequential access media device are disclosed. One such method involves creating multiple identities of the sequential access media device on a server. A portion of a memory of the server is allocated to each respective identity of the sequential access media device. A backup data stream from the NAS device is written to each allocated portion of the memory. Data written to each allocated portion of the memory is multiplexed for transmission to the sequential access media device for storage.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: May 7, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Alioune Thiam
  • Patent number: 10282265
    Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas P. Grosser, Gerrit Koch, Ralf Winkelmann
  • Patent number: 10248561
    Abstract: The disclosed embodiments provide a system that detects anomalous events in a virtual machine. During operation, the system obtains time-series garbage-collection (GC) data collected during execution of a virtual machine in a computer system. Next, the system generates one or more seasonal features from the time-series GC data. The system then uses a sequential-analysis technique to analyze the time-series GC data and the one or more seasonal features for an anomaly in the GC activity of the virtual machine. Finally, the system stores an indication of a potential out-of-memory (OOM) event for the virtual machine based at least in part on identifying the anomaly in the GC activity of the virtual machine.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Dustin R. Garvey, Sampanna S. Salunke, Lik Wong, Xuemei Gao, Yongqiang Zhang, Eric S. Chan, Kenny C. Gross
  • Patent number: 10228990
    Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 12, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yiwei Song, Nian Niles Yang, James Fitzpatrick
  • Patent number: 10224115
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • Patent number: 10169152
    Abstract: Data recovery following the loss of a volume manager is described, wherein a volume manager receives a command, and location information and credentials to access a distributed storage. The data to be recovered may include one or more data files stored as one or more discrete portions. Each portion includes metadata, including at least a file ID tag. The volume manager retrieves each portion of data from the distributed storage and records, in an index, the location that each portion of data was retrieved from. The volume manager reads and stores the file ID tag with the associated location of the attached portion of data in the distributed storage in the volume manager index.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Murilo O. Araujo, Ricardo M. Matinata, Rafael P. Sene
  • Patent number: 10169130
    Abstract: Tailoring diagnostic information specific to current activity of multiple threads within a computer system. A request to dump system state is received. A system dump is created, including main memory and system state information. The system dump is stored to a database. In response to a request to format the system dump, the system dump is loaded from the database, whereby a virtual memory image of system state at system dump time is created. The virtual memory image and system state information is scanned to identify tasks that were running, tasks that have failed due to an error, and tasks that were suspended at system dump time. State information and control blocks associated with the identified tasks are collected from the system dump and collated based on task number. The database is updated with a formatted system dump, including the state information and control blocks associated with the identified tasks.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Edward A. Addison, Darren R. Beard, William J. Bulfin, Peggy A. DeVal, James A. Harrison, Manuela Mandelli, John S. Tilling, Andrew Wright
  • Patent number: 10168958
    Abstract: An object is to make it possible to add a vendor-unique command at the time at which addition of a vendor-unique command becomes necessary later even in the case where the device side does not have a dedicate pin for updating in communication control based on a SATA standard. An information processing system that performs data communication between a host and a device in conformity with the SATA standard, and the host transmits a setup command to which information on an undefined command is written to the device, and the device: has a command table for commands in conformity with the SATA standard, in which a command code to identify each command and information on a transfer protocol of each command are described; and makes the undefined command available between the host and the device by writing information on the undefined command to the command table in accordance with the received setup command.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuyuki Yokota
  • Patent number: 10157002
    Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues with the processing module determining an end-of-life memory level for the memory device. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Jason K. Resch, Timothy W. Markison, Ilya Volvovski, Manish Motwani
  • Patent number: 10157021
    Abstract: A method includes obtaining a set of pending transaction information from a set of storage units regarding a plurality of pending transactions. A pending transaction information includes information regarding an encoded data slice and a computing device issuing a data access request. The method further includes identifying an incomplete transaction based on the set of pending transaction information. The method further includes determining whether to complete the incomplete transaction based on information regarding the requesting computing device. The method further includes, when the incomplete transaction is not to be completed, instructing the storage units to discard a corresponding data access request associated with the incomplete transaction.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Ravi V. Khadiwala
  • Patent number: 10152373
    Abstract: Methods of operating a memory, including receiving first data to be written to an array of memory cells of the memory, receiving error correction code (ECC) data corresponding to the first data, and receiving a flag having a value. Such methods further include storing the first data, the ECC data and the flag to the array of memory cells without performing error correction on the first data using the ECC data if the flag has a first value, and if the flag has a second value different than the first value and the first data does not contain an error. Such methods further include performing error correction on the first data using the ECC data, and storing corrected first data, the ECC data and the flag to the array of memory cells if the flag has the second value and the first data contains an error.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 10146279
    Abstract: A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 4, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dmitry Vyshetsky
  • Patent number: 10095565
    Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: October 9, 2018
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
  • Patent number: 10095867
    Abstract: For an antivirus scan during a data scrub operation, the antivirus scan is concurrently performed as an overlap with the data scrub operation, wherein the data scrub operation periodically inspects and corrects memory errors. The antivirus scan concurrently performing as an overlap with the data scrub operation is increased if a reduction in disk access by a host application is detected.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lawrence C. Blount
  • Patent number: 10089036
    Abstract: A method begins by a processing modules of a storage unit (SU) of a dispersed storage network (DSN) determining to migrate a set of encoded data slices from the first storage format to a second storage format. The method continues with the SU selecting the second storage format for the set of EDSs and selecting a second DSN memory configured to store the set of EDSs based on the second storage format. The method continues with the SU determining a first migration rate and migrating a first subset of the set of EDSs from the first DSN memory to the second DSN memory. The method continues with the SU monitoring activity associated with the DSN memory, selecting a second migration rate based on the activity associated with the at least one of the first DSN memory or the second DSN memory, and migrating a second subset of the set of EDSs based on the second migration rate.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Asimuddin Kazi, Joseph M. Kaczmarek, Jason K. Resch
  • Patent number: 10083225
    Abstract: In one embodiment, a system includes at least one processor and logic integrated with and/or executable by the at least one processor, the logic configured to create a first base record in a keyed index of a database, the first base record including a first unique key and a first data record, wherein the first data record includes at least one sub key and at least one first value, each sub key being correlated with a different one of the at least one first value in a sub key/value pair, and create one or more alternate key records in the database, each of the alternate key records including one of the at least one sub key which is correlated with the first base record and the first unique key of the first base record. More embodiments of systems, methods, and computer program products for providing alternate keys are also presented.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventor: Terri A. Menendez
  • Patent number: 10083081
    Abstract: A method includes detecting a storage error regarding an encoded data slice. The method further includes determining failure mode information regarding a set of storage units. The method further includes determining, based on the failure mode information, whether to use a data-based rebuilding protocol or a zero information gain rebuilding protocol for rebuilding the encoded data slice. The method further includes, when the zero information gain rebuilding protocol is to be used to rebuild the encoded data slice retrieving zero information gain partial encoded data slices from one or more storage servers of the set of storage servers; and rebuilding the encoded data slices based on the zero information gain partial encoded data slices.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: S. Christopher Gladwin, Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Patent number: 10073447
    Abstract: In industrial machine abnormality diagnosis, if the machine is diagnosed to have abnormality, then sensor data from the machine needs to be sent to a management center for causal analysis. However, since machines operated at a remote site cannot always communicate with a management center, it has been found that, in some cases, sensor data that has failed to be sent from a machine remains in the memory of the machine, resulting in lack of available memory capacity. In view of this, the present invention determines beforehand whether the diagnosed machine will run out of available memory capacity before the completion of sending the amount of sensor data required for causal analysis for the machine, and instructs a maintenance person to recover memory.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uchida, Hideaki Suzuki, Junsuke Fujiwara, Tomoaki Hiruta, Munetoshi Unuma
  • Patent number: 10037149
    Abstract: Implementations disclosed herein provide for a storage system including an on-disk read cache and a variety of read cache management techniques. According to one implementation, a storage device controller time-sequentially reads a series of non-contiguous data blocks storing a data sequence in a read cache of a magnetic disk, the data sequence identified by a requested sequence of logical block addresses (LBAs). The controller determines that read requests for the data sequence satisfy at least one predetermined access frequency criterion and, responsive to the determination, the controller re-writes data of the data sequence to a series of contiguous data blocks in the read cache.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: July 31, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Alexey V. Nazarov, Andrew Michael Kowles
  • Patent number: 10019366
    Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Robert H. Beers, Ching-Tsun Chou, Robert J. Safranek, James Vash
  • Patent number: 10014024
    Abstract: Embodiments of the present invention provide a drive storage system, method, and computer program process for automatically replacing drives. In one embodiment, one or more computer processors receive a request for a new drive. One or more computer processors direct an exchange robot to obtain the new drive from a drive repository and to proceed to a location of a used drive. One or more computer processors then direct the exchange robot to remove the used drive from the location and to insert the new drive into the location of the used drive.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Uwe Fiebrich-Kandler, Frank Krick, Thorsten Muehge, Erik Rueger
  • Patent number: 10007568
    Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Paul F. Lecocq, John A. Schumann
  • Patent number: 10007508
    Abstract: According to one embodiment, upon reception of a command and an archive file for updating first firmware, a controller selects first information corresponding to information for identifying the memory system from a plurality of first information included in the header. The controller acquires second information included in the selected first information, and acquires one of a plurality of second firmware included in the archive file based on the acquired second information, to update the first firmware by the acquired second firmware.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 26, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kentaro Sugino, Hiroaki Tanaka, Ayumu Anzai
  • Patent number: 9983818
    Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Jiezhi Chen, Yuuichiro Mitani, Tetsufumi Tanamoto, Takao Marukame
  • Patent number: 9977894
    Abstract: Methods, systems, and computer program products for selecting a virtual machine to perform a task corresponding to a client request and performing the task at the virtual machine. After performing the task at the virtual machine, an indicator corresponding to a shutdown of the virtual machine is detected. After detecting the indicator and prior to the shutdown of the virtual machine, a memory space is preserved corresponding to the virtual machine. The preserved memory space is then scanned for malware.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 22, 2018
    Assignee: RED HAT, INC.
    Inventor: David Gilbert
  • Patent number: 9971648
    Abstract: A system, computer program product, and computer-executable method of managing parity data of a Redundant Array of Independent Disks (RAID) on a data storage system, where the data storage system stores a first set of parity data and retains metadata associated with the first set of parity data, the system, computer program product, and computer-executable method including allocating a set of locations on the data storage system for a second set of parity data, processing the second set of parity data, and updating the metadata associated with the first set of parity data.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 15, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Tal Ben-Moshe, Niko Farhi, Lior Kamran
  • Patent number: 9959929
    Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 1, 2018
    Assignee: Micron Technology, Inc.
    Inventor: David Resnick
  • Patent number: 9946616
    Abstract: A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a RAID controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a RAID group.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 17, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Saito, Junji Ogawa, Hiroaki Akutsu, Hideyuki Koseki, Atsushi Kawamura
  • Patent number: 9934085
    Abstract: A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 3, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe-Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan, Robert Schreiber, Norman Paul Jouppi
  • Patent number: 9864698
    Abstract: A method, system, and computer program product for resolving cache lookup of large pages with variable granularity are provided in the illustrative embodiments. A number of unused bits in an available number of bits is identified. The available number of bits is configured to address a page of data in memory, wherein the page exceeding a threshold size, and the page comprising a set of parts. The unused bits are mapped to the plurality of parts such that a value of the unused bits corresponds to existence of a subset of the set of parts in a memory. A virtual address is translated to a physical address of a requested part in the set of parts. A determination is made, using the unused bits, whether the requested part exists in the memory.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ahmed Gheith, Eric Van Hensbergen, James Xenidis
  • Patent number: 9859019
    Abstract: A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deepak I. Hanagandi, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 9841921
    Abstract: Migrating data in a storage array that includes a plurality of storage devices, including: detecting, by the storage array, an occurrence of a storage device evacuation event associated with one or more source storage devices; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage array, one or more target storage devices for receiving data stored on the one or more source storage devices; reducing, by the storage array, write access to the one or more source storage devices; and migrating the data stored on the one or more source storage devices to the one or more target storage devices.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: December 12, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Andrew Kleinerman, Benjamin Scholbrock, Taher Vohra, Xiaohui Wang
  • Patent number: 9823968
    Abstract: Variable Redundancy Distributed (VRD) RAID controller in a data storage environment contains embedded RAID logic permitting to choose and compute a desired redundancy coding scheme from a plurality thereof pre-programmed and embedded in a Compute Engine in the VRD RAID controller. “Write” or “Read” requests which are received from data generating entities, contain information identifying a type of the redundancy coding scheme of interest. The controller decodes the request, and automatically applies the desired computation to the incoming data without burdening the CPU with the computational activity. The variable redundancy computational ability of the subject systems provides an extremely versatile and flexible tool for RAID operations.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: November 21, 2017
    Assignee: DataDirect Networks, Inc.
    Inventors: Thomas E. Fugini, Michael J. Piszczek, William J Harker, Jason M. Cope, Pavan Kumar Uppu
  • Patent number: 9804921
    Abstract: A nonvolatile memory apparatus is provided with a nonvolatile memory including a plurality of blocks each being a recording area of the data and a unit of erasing of the data, and a controller for controlling writing or reading of the data to/from the nonvolatile memory. Each of the blocks includes pages each being a unit of reading of the data. The controller, when data of a first page is read in response to the data read request from the external apparatus, reads data of an other page other than the first page in a block from which the data is read, and calculates a number of errors of the data in the other page, and rewrites the data into an other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 31, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Masato Suto
  • Patent number: 9792170
    Abstract: Techniques are provided for correcting the operational state of a multi-process system without disrupting any running processes. A library providing error correction and logging functionality is statically linked to modules in the system. A script in the library loads a package file having a patch for returning an error state to a normal state. The script issues commands to invoke functions in the patch. Once the error state has returned to a normal state, the script issues commands to remove the package file from the system.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 17, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Kashyap Merchant, Srinivas Pitta
  • Patent number: 9785377
    Abstract: Methods, apparatuses, systems, and devices are described for determining use of areas of a disk drive. In one method, a score of an area node of the disk drive may be increased each time the area node is accessed during a time interval of a series of time intervals. When each time interval elapses, each existing score of the area nodes (e.g., scores of area nodes that have non-zero scores) may be decreased. Further, after being decreased, each existing score may be saved. In such a manner, a time series analysis of data accesses may be implemented. The increases in score may account for the number of accesses during a given interval, and the decreases in score may account for time passage (e.g., time-weighting the scores). Thus, more frequent accesses and more recent accesses result in higher accumulated scores for the corresponding area nodes.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: October 10, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Junghwan Shin, Suhwan Kim, Dong Hyuck Shin
  • Patent number: 9742752
    Abstract: A user terminal stores security information for each of a plurality of files during a backup of the files. The user terminal also stores information regarding the configuration settings of one or more terminals from which a user may access the plurality of files. During a restore of the files to a remote user terminal, the user terminal at which the restore command was issued utilizes the saved security information to emulate the remote terminal as a virtual endpoint for the files. The user terminal determines whether the user is authorized to access the files within the virtual endpoint based on the saved security information, and restores the files to the remote terminal if the user is authorized for access to the files within the virtual endpoint.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 22, 2017
    Assignee: CA, Inc.
    Inventors: Vijaya Kumar Pothireddy, Aravind Kumar Banduchode
  • Patent number: 9720845
    Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 9716361
    Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Shaowu Huang, Beom-Taek Lee
  • Patent number: 9704597
    Abstract: A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Masashi Oya
  • Patent number: 9697138
    Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 9690651
    Abstract: A method is provided for controlling a redundant array of independent disks (RAID). The method comprises a computer system writing data to a RAID and reading data from the RAID, wherein the RAID includes a controller and a plurality of data storage devices, including a flash data storage device. The method further comprises the controller detecting whether or not the flash data storage device is in read-only mode, and the controller preventing attempts to write data to the flash data storage device in response to detecting that the flash data storage device is in read-only mode. Optionally, when the flash data storage device is in read-only mode, the controller may redirect writes intended for the flash data storage device to empty data storage space on another data storage device or cache memory, or modify the parity stripe of a major stripe in view of the data intended to be written.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 27, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Christopher J. Hardee, Srihari V. Angaluri, Adam Roberts