Memory Or Storage Device Component Fault Patents (Class 714/42)
  • Patent number: 11429283
    Abstract: Example implementations relate to determining a device wear-rate. An example system for determining a device wear-rate can include a plurality of filter drivers to: monitor system requests for I/O associated with a device of the system and transmit information associated with the system requests to a filter manager. The system can also include the filter manager to catalog the information, a service to collate the information across a plurality of machine configurations and workloads, and a processor to determine a wear-rate of the device based on an analysis of the collated information.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: August 30, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christoph J. Graham, Thomas J. Flynn, Virginia Quance Herrera
  • Patent number: 11409458
    Abstract: A device such as a network-attachable data transfer device may be configured to operate in a cluster to coordinate the storage of data. A first manifest may be generated inventorying a first set of data successfully transferred to the data transfer device from a data source. A second manifest may be generated inventorying a second set of data successfully transferred from the data transfer device to a data destination. The first manifest may be compared with the second manifest to determine a transfer status of one or more data objects. The transfer status may indicate one or more data objects successfully transferred to the data destination from the data source. The one or more objects may be processed according to the transfer status.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Colin Laird Lazier
  • Patent number: 11403189
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes determining that a particular primary disk of a capacity object of a storage system has failed, wherein the capacity comprises a plurality of segments, and wherein the each segment comprises: a plurality of primary columns each corresponding to a respective primary disk of the capacity object, and a plurality of parity columns each corresponding to a respective parity disk of the capacity object; and resynchronizing, for each segment of one or more segments of the capacity object, the primary column of the segment corresponding to the particular primary disk using i) the primary columns of the segment corresponding to each other primary disk of the capacity object, ii) one or more parity columns of the segment, and iii) the column summaries of the segment.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: August 2, 2022
    Assignee: VMware, Inc.
    Inventors: Wenguang Wang, Enning Xiang, Vamsi Gunturu, Eric Knauft, Pascal Renauld
  • Patent number: 11403096
    Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Phillip G. Hays, Craig M. Cutler, Andrew J. Rees
  • Patent number: 11403036
    Abstract: A method comprising: receiving, by a first storage node, an instruction to designate a first device file as the first storage node's primary device file for accessing a storage device designating, by the first storage node, the first device file as the first storage node's primary device file for accessing the storage device, the first device file being designated as the first storage node's primary device file for accessing the storage device in response to the first instruction; receiving, at the first storage node, an I/O command that is associated with the storage device; making a first attempt to complete the I/O command by using the first device file, detecting, by the first storage node, an error that is generated in response to the first attempt; designating, by the first storage node, a second device file as the first storage node's primary device file for accessing the storage device.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 2, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Alex Soukhman
  • Patent number: 11379318
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes receiving, by a first storage subsystem, a plurality of write requests corresponding to respective meta data blocks, wherein the first storage subsystem comprises a meta object; storing, by the first storage subsystem and for each write request, in each disk of the meta object, a version of the corresponding meta data block; determining that a particular disk of the meta object has failed; determining whether one or more valid versions of the meta data block are stored in respective other disks of the meta object; and in response to determining that one or more valid versions of the meta data block are stored in respective other disks of the meta object, resynchronizing the meta data block in the particular disk.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 5, 2022
    Assignee: VMware, Inc.
    Inventors: Wenguang Wang, Vamsi Gunturu, Eric Knauft
  • Patent number: 11379330
    Abstract: Embodiments of information handling systems (IHSs) and computer-implemented methods are provided herein for testing system memory (or another volatile memory component) of an IHS. In the disclosed embodiments, memory testing is performed automatically: (a) during the pre-boot phase each time a new page of memory is allocated for the first time after a system boot, and (b) during OS runtime each time a read command is received and/or an event is detected. By proactively testing each page of memory, as the page is allocated but before information is stored therein, the systems and methods disclosed herein prevent “bad” memory pages from being used.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Dell Products L.P.
    Inventors: Craig L. Chaiken, Siva Subramaniam Rajan
  • Patent number: 11372555
    Abstract: A method and system may reconstruct data in a smart storage array where upon detection of data inconsistency, an application of the system is notified and affected data strips are rebuilt. When an initiator detects stripe corruption, the initiator may report the strip corruption to storage. The storage may lock the strip for I/O operations. Initiators may determine recovery scenarios for rebuilding the data strips and send the scenarios to storage. At storage, initiator replies may be collected, and a rebuild option with the highest votes may be automatically determined for a reconstruction operation. Once the reconstruction operation is completed, the rebuilt stripe may be unlocked and data operations may recommence.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Asaf Porat-Stoler, Constantine Gavrilov, Christopher M. Dennett, Rivka Mayraz Matosevich, Sergey Marenkov, Jonathan Fischer-Toubol, Afief Halumi
  • Patent number: 11366721
    Abstract: Systems and methods to throttle a universal backup host are described. The system executes a job, at a backup host, to back up a file set from a source host including fetching metadata from the source host. The system identifies a first operation set from operation sets, the operation set including a first operation. The system communicates, in parallel, requests for metadata items, over a network, to the source host, receives responses, and processes the responses by utilizing threads from a thread pool. The system generates latencies, counts the number of requests, and stores the latencies and number of requests in samples. The system aggregates the samples responsive to a timeout. The system resizes the thread pool based on the aggregating. Finally, the system backs up the file set from the source host based on the metadata.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: June 21, 2022
    Assignee: Rubrik, Inc.
    Inventors: Haihong Wang, Gopikrishnan Aditya Suresh
  • Patent number: 11366155
    Abstract: A chip testing device and a chip testing system are provided. The chip testing system includes a chip testing device and a plurality of environment control apparatuses. A plurality of electrical connection sockets are disposed on one side of a circuit board, and a plurality of testing modules are disposed on another side of the circuit board. A first fixing member and a second fixing member fix the electrical connection sockets on one side of the circuit board, and no screwing members are required to be screwed between the electrical connection sockets and the circuit board. Each of the electrical connection sockets with a chip disposed thereon can be disposed in a high temperature environment or a low temperature environment for testing along with the chip testing device, so that each of the chips does not need to be detached repeatedly.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 21, 2022
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11361840
    Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to a host, and a controller. The controller is configured to carry out writing of data that is received through the communication interface at a physical location of the nonvolatile memory when a write command associated with the data is received through the communication interface, control the communication interface to return a first notification upon determining that the writing of data at the physical location of the nonvolatile memory has completed, and control the communication interface to return a second notification a predetermined period of time after the first notification has been returned.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 14, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 11349924
    Abstract: In a storage system with multiple storage arrays configured to replicate a storage object, storage management applications are configured to exchange communications via private data replication links by encoding the communications as XML files and writing the files to their local storage array under a shared operating system. Other storage management applications poll their local storage arrays, discover the files, and then decode and read the communications. The communications may include messages, requests, and responses. Topics of interest may be specified in messages. Specific storage arrays may be designated as targets of requests. Responses are sent by encoding the responses as XML files and writing the files to respective local storage arrays under a shared operating system.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: May 31, 2022
    Assignee: Dell Products L.P.
    Inventor: Aaron Twohig
  • Patent number: 11327110
    Abstract: A chip testing system includes a central control device, a chip mounting apparatus, a plurality of environment control apparatus, a classification apparatus, and a transferring apparatus. The central control device is configured to control the chip mounting apparatus to dispose a plurality of chips onto a chip testing device. Each of the environment control apparatus includes a plurality of accommodating chambers that are independent from each other. Each of the accommodating chambers is provided with a temperature adjusting device. The central control device is configured to control the transferring apparatus to place the chip testing device into one of the accommodating chambers. When the chip testing device carrying the chips is arranged in the corresponding accommodating chamber, the central control device is configured to control an operation of the corresponding temperature adjusting device, so that the chips are in an environment of a predetermined temperature.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: May 10, 2022
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11317504
    Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: April 26, 2022
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Yu-Chieh Wei, Yen-Chen Chen, Yu-Ching Hung
  • Patent number: 11301450
    Abstract: Techniques are provided for maintaining timestamp parity during a transition replay phase to a synchronous state. During a transition logging phase where metadata operations executed by a primary node are logged into a metadata log and regions modified by data operations executed by the primary node are tracked within a dirty region log, a close stream operation to close a stream associated with a basefile of the primary node is identified. A determination is made as to whether the dirty region log comprises an entry for the stream indicating that a write data operation previously modified the stream. In an example, in response to the dirty region log comprising the entry, an indicator is set to specify that the stream was deleted by the close stream operation. In another example, a modify timestamp of the basefile is logged into the metadata log for subsequent replication to the secondary node.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 12, 2022
    Assignee: NetApp, Inc.
    Inventors: Krishna Murthy Chandraiah Setty Narasingarayanapeta, Preetham Kudgi Shenoy
  • Patent number: 11301162
    Abstract: Techniques are provided for processing user input/output (I/O) write requests in a fault-tolerant data storage system (e.g., a RAID storage system) by selecting between performing a degraded write operation or a write operation to spare capacity, when the fault-tolerant data storage system is operating in a degraded mode. A method includes receiving a user I/O write request comprising data to be written to a RAID array operating in a degraded mode, and determining whether spare capacity has been allocated for rebuilding missing data of an inaccessible storage device of the RAID array and whether a missing data block, which is associated with I/O write request, has been rebuilt to the spare capacity. A degraded write operation is performed without using the spare capacity, when the missing data block, which is associated with the data of the I/O write request, has not been rebuilt to the allocated spare capacity.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 12, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rivka Matosevich, Yosef Shatsky, Doron Tal
  • Patent number: 11302410
    Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11264109
    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
  • Patent number: 11263134
    Abstract: A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Mustafa N. Kaynak, Shane Nowell
  • Patent number: 11263081
    Abstract: A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at successive points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 1, 2022
    Assignee: Graphcore Limited
    Inventors: David Lacey, Daniel John Pelham Wilkinson
  • Patent number: 11255904
    Abstract: A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: February 22, 2022
    Inventors: Min-Woo Kim, Chang-Ho Lee, Jin-Ho Choi
  • Patent number: 11212935
    Abstract: Mechanisms are provided for cabling a set of enclosures. Using a set of cables that comprises eight physical layers (PHYs), the set of enclosures are coupled together such that: for a first enclosure and each intermediate enclosure in the set of enclosures, at least four PHYs of the eight PHYs terminate within a Serial Attached Small Computer System Interface (SCSI) (SAS) expander of the first enclosure and a SAS expander of each intermediate enclosure white passing through a remaining four PHYs of the eight PHYs without connecting to the respective SAS expander; and, for a last enclosure in the set of enclosures, all of the eight PHYs terminate in the SAS expander of the last enclosure.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: December 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Daniel S. Critchley, Gordon D. Hutchison, Gareth P. Jones, Jonathan W. L. Short
  • Patent number: 11210194
    Abstract: An instruction to perform load testing is sent to a mobile device where an application running on the mobile device determines whether the mobile device is in a state where load testing is permitted. In response to receiving the instruction, the application running on the mobile device performs load testing on a web server if the mobile device is in the state where load testing is permitted. Performance information associated with the load testing is received from the application running on the mobile device and the performance information associated with the load testing is displayed.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 28, 2021
    Assignee: Neocortix, Inc.
    Inventors: Donald Lloyd Watts, Dmitry Moskalchuk
  • Patent number: 11204835
    Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 21, 2021
    Assignee: SuperMem, Inc.
    Inventors: Yu Lu, Chieh-yu Lin
  • Patent number: 11199836
    Abstract: A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Greslehner-Nimmervoll, Rainer Findenig, Christian Schmid
  • Patent number: 11193971
    Abstract: A chip testing method for being implemented by a chip testing system includes: a chip mounting step implemented by using a chip mounting apparatus to respectively dispose a plurality of chips onto electrical connection sockets of a chip testing device; a moving-in step implemented by transferring the chip testing device carrying the chips into one of accommodating chambers of an environment control apparatus; a temperature adjusting step implemented by controlling a temperature adjusting device of the one of the accommodating chambers so that the chips are in an environment having a predetermined temperature; and a testing step implemented by providing electricity to the chip testing device, so that each testing module of the chip testing device performs a predetermined testing process on the chips on the corresponding electrical connection sockets connected thereto.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 7, 2021
    Assignee: ONE TEST SYSTEMS
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11183266
    Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 23, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: David Hulton, Tamara Schmitz, Jonathan D. Harms, Jeremy Chritz, Kevin Majerus
  • Patent number: 11144203
    Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Allan Porterfield
  • Patent number: 11132312
    Abstract: To control initialization of a nonvolatile memory device, before assembling a memory system including a first nonvolatile memory device and a second nonvolatile memory device, information data for initialization of the first nonvolatile memory device are stored in the first nonvolatile memory device. After assembling the memory system, the information data are moved from the first nonvolatile memory device to the second nonvolatile memory device. The first nonvolatile memory device is initialized based on the information data stored in the second nonvolatile memory device. An initialization time of the first nonvolatile memory device is reduced efficiently by moving the information data from the first nonvolatile memory device to the second nonvolatile memory device having the rapid speed of the reading operation and using the information data read from the second nonvolatile memory device.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinyoung Kim, Jaeduk Yu
  • Patent number: 11132255
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 11119838
    Abstract: Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, Camille C. Raad
  • Patent number: 11119853
    Abstract: A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Su Jin Lim
  • Patent number: 11099776
    Abstract: A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 11099757
    Abstract: A memory system includes a memory device including a plurality of memory blocks capable of storing data, and a controller configured to determine an attribute of data stored in a memory block during an operating period. A duration of the operating period is changeable based on a parameter regarding the plurality of memory blocks. The duration of the operating period is adjusted in order to increase the accuracy of a determination of a usage pattern regarding the memory device.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11080136
    Abstract: A computer-implemented method for dropped write error detection is proposed. In the method, a read request for a stride stored in an array of storage drives is received. The stride includes segments of a data and a first parity associated with the data spreading across the storage drives in the array of the storage drives. In response to the read request being a predefined sequential read request and a state of the stride being a first state, a parity check is performed on the stride. The first state indicates that no parity check has been performed after the data is written into the array of storage drives. The state of the stride is changed to a second state, and the second state is different with the first state.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gang Lyu, Jun Gu, Hong Zhou
  • Patent number: 11080444
    Abstract: Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manoj Kumar, David J. Roberts, Apurva Kalia
  • Patent number: 11080124
    Abstract: An information handling system includes a memory controller with an error logger, and a DIMM coupled to the memory controller via a memory channel. The DIMM includes a non-volatile memory device mapped to include event blocks that store error information associated with memory events occurring the memory controller, the DIMM, and the memory channel. Each event block includes a flag field and a data field. The error logger receives an indication that a memory event has occurred, reads first flag information from a flag field of an event block, determines whether the event block is locked based upon the first flag information, and if the event block is not locked, then writes second flag information to the flag field and writes event information to a data field of the event block. The event information describes the memory event.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 3, 2021
    Assignee: Dell Products, L.P.
    Inventors: Mark Dykstra, Amit Shah, Yuwei Cai
  • Patent number: 11080125
    Abstract: A method of clustering call stacks from a memory dumps resulting from out-of-memory errors includes accessing a memory dump resulting from an out-of-memory error; identifying call stacks in the memory dump that are associated with the out-of-memory error; accessing call stacks from one or more other memory dumps that were determined to be associated with other out-of-memory errors; generating clusters of call stacks based on a similarity score; and providing a cluster for an analysis of the out-of-memory error.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 3, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Santhosh Raj
  • Patent number: 11068339
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Patent number: 11068337
    Abstract: A data processing apparatus includes a processor; and a direct memory access (DMA) controller coupled to the processor, the DMA controller including a control circuit that controls a DMA transfer of data, an error detection circuit that performs an error detection on the data based on a character assigned in association with the data to output a result of the error detection to the control circuit, and a diagnosis circuit that disconnects between the control circuit and the error detection circuit to diagnose an operation of the error detection circuit and provide a diagnosis result to the processor.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Shinya Miyata
  • Patent number: 11055167
    Abstract: Techniques for remapping portions of a plurality of non-volatile memory (NVM) dice forming a memory domain. A processing device partitions each NVM die into subslice elements comprising respective physical portions of NVM having proximal disturb relationships. The NVM allocation has user subslice elements and spare subslice elements. For the NVM dice forming the memory domain, the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for the memory domain. Identified user subslice elements having the highest error rates, remap to spare subslice elements of the memory domain that were not identified as having the highest error rates to remove subslice element or elements having highest error rates. At least one user subslice element is remapped from a first die of the memory domain to a second die of the memory domain.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: July 6, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Patent number: 11056198
    Abstract: A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish R. Singidi, Shane Nowell, Vamsi Pavan Rayaprolu, Sampath K. Ratnam
  • Patent number: 11036543
    Abstract: Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Robert Charles Swanson, Christopher James BeSerra
  • Patent number: 11023315
    Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 1, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Mike Jadon, Craig Robertson, Robert Lercari
  • Patent number: 11010245
    Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Seow-Fong Lim, Ngatik Cheung, Chi-Shun Lin
  • Patent number: 11010242
    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-hyung Song, Jangseok Choi
  • Patent number: 11012246
    Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Wei-Min Chan, Chien-Chen Lin
  • Patent number: 11010234
    Abstract: A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: San-Ha Park
  • Patent number: 11011249
    Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corporation
    Inventors: Amanulla Khan, Kelly Yang, Lianrui Zhang, Himakiran Kodihalli, Thenappan Nachiappan, Sreekar Sreesailam
  • Patent number: 10997017
    Abstract: Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Yu Cai, Chenrong Xiong, Fan Zhang, Naveen Kumar, Aman Bhatia, Xuanxuan Lu