Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: In one embodiment, a tape drive includes a reserved data buffer and logic integrated with and/or executable by a processor. The logic is configured to read a data set from a medium and store a first portion of the data set to the reserved data buffer in response to a determination that the first portion of the data set is correctable using C2 error correction code (ECC). The logic is also configured to replace any stored row of a non-C2-correctable portion of the data set stored to the reserved data buffer with a corresponding row of the data set read from the medium in response to a determination that the stored row of the non-C2-correctable portion of the data set has an equal amount or more C1-correctable error therein than the corresponding row of the data set read from the medium.

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: An electronic device includes: a shelf where a first slot and a second slot are formed; a plurality of kinds of electronic circuit boards including a first-side protrusion portion and a second-side protrusion portion, and an arrangement pattern of the first-side protrusion portion and the second-side protrusion is different from each other; when an electronic circuit board having the first-side protrusion portion into the first slot, the first abutment member abut the first-side protrusion portion of the first position and rotate from a first angle position to a second angle position; a second abutment member installed at the first slot and rotatable around an axis of the first direction, and when an electronic circuit board having the first-side protrusion portion into the first slot, the second abutment member abut the first-side protrusion portion of the second position and rotate from the first angle position to the second angle position.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: A method begins by independently executing a first write transaction in a dispersed storage network (DSN) to a particular write verification step of a multiple step write process, wherein the first write transaction has a first transaction identifier. The method continues by independently executing a second write transaction in the DSN to the particular write verification step, wherein the second write transaction has a second transaction identifier, and wherein subject matter of the first write transaction is related to subject matter of the second write transaction. The method continues by dependently finalizing the multiple step write process for each of the first and second write transactions utilizing the first and second transaction identifiers when each of the first and second write transactions have reached the particular write verification step.

Abstract: An apparatus for compute and networking operation in a rack-mounted device are provided herein. An exemplary apparatus may include a compute substrate, a networking substrate, and a bridge substrate. The compute substrate may include a processor, and a memory communicatively coupled to the processor. The networking substrate may be separate from the compute substrate and include control processor, and an Ethernet switch communicatively coupled to the control processor. The bridge substrate may be communicatively coupled to the compute substrate and the networking substrate, and include at least two high-speed signal traces, the high-speed signal traces being at least one differential pair, the high-speed signal traces being communicatively coupled to the compute substrate and the networking substrate.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: A method, system, and/or computer program product encodes diagnostic data in an error message for a computer program. In response to an error in the processing of a computer program, a predetermined set of diagnostic data associated with the error is selected. The predetermined set of diagnostic data is encoded in an image, and the image is displayed in association with an error message for the error.

Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. The control circuitry is configured to select a pending write request from an entry of the command buffer and send the selected write request to the memory. The selected write request is a partial write request having first write data stored in the entry. Sending the selected write request includes performing a read-modify-write (RMW), wherein the control circuitry is configured to, after a read operation of the RMW, update the pending write request in the entry from a partial write request to a full write request.

Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

Abstract: A technique for protecting stored information from read disturbance includes receiving a first write request to a solid-state device (SSD) in a storage pool that employs an erasure code. The first write request has an associated identifier and associated data. In response to receiving the first write request, the first write request is assigned to two or more SSD blocks of the SSD device based on the identifier. Pages of the associated data are then written to the assigned SSD blocks, such that each SSD block holds data associated with only a single identifier.

Abstract: A transceiver and a transceiver operating method are disclosed. The transceiver is coupled to a bus. The transceiver includes a receiving unit, a transmitting unit, and a detection unit. The receiving unit is coupled to the bus. The transmitting unit is coupled to the bus. The detection unit is coupled to the receiving unit and the transmitting unit respectively. The detection unit receives a first input signal, a receiver enabling signal, and a transmitter enabling signal respectively and selectively enhances the first input signal and the transmitter enabling signal according to a result of comparing the receiver enabling signal and the transmitter enabling signal. Then, the detection unit transmits the enhanced first input signal and transmitter enabling signal to the bus through the transmitting unit.

Abstract: An image-forming apparatus to process a job includes volatile memory, non-volatile memory, a judging unit, a calculating unit, a defining unit, and a controller. The volatile memory stores a generated error log using a memory area. The non-volatile memory stores information for identifying an overwrite restricted error. The judging unit judges whether a generated error is a particular error. The calculating unit calculates remaining memory which is changed by a subsequent error log being written secured, with a position where a particular error log is written in the volatile memory as a reference, where the error is the particular error. The defining unit defines an acquisition level of an error log in a stepwise manner based on the calculated remaining memory. The controller outputs an error log to an apparatus according to the defined acquisition level being a particular level at which an error log has to be output.

Abstract: Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.

Abstract: Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.

Abstract: According to one general aspect, an apparatus may include a trace control register, a first output path, and a second output path. The trace control register may be configured to receive one or more signals output by a combinatorial logic block. The trace control register may include a first register portion configured to capture the one or more signals. The trace control register may include a second register portion configured to capture whether an event occurred within the combinatorial logic block. The occurrence of the event is determined by at least a portion of the one or more signals having a predetermined state. The first output path configured to select between a plurality of captured signals provided by respective trace control registers. The second output path configured to output one or more captured events provided by one or more respective trace control registers.

Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: Statistical wear leveling is described that may be particularly useful for non-volatile system memory. In one embodiment, the invention includes a wear level move state machine to select an active block based on a wear criteria, to move the contents of the selected active block to a block from a free block list, and to move the selected active block to an unused block list, a free block list expansion state machine to take a block from a target free block list, to move the contents of the block to a block from the unused block list, and to move the block taken from the target block list to a free block list, and a target free block generation state machine to select blocks from the unused block list and to move the selected blocks to the target free block list.

Abstract: A controller includes an address generator that sets a plurality of different paths, each connecting an information processing apparatus connected to a storage apparatus via a network, first and second storage mediums, and the controller, and generates a second address that is different from a first address used for a communication with the information processing apparatus via the network; an access monitor that determines that no access has been issued for a certain time duration from the information processing apparatus to the first or second storage medium; an access issuing unit that issues a test access to the first and second storage mediums on one of the paths, using the second address; and an access decoder that converts the test access to an access including the first address, receives a result of the access including the first address from the first or second storage mediums, and checks for an error.

Abstract: A computer system has a managing server for managing one or more managed nodes. The managed nodes have media encoded with test executables executable on their respective nodes. The test executables can check configuration data for the node and/or check whether external resources are accessible from the node. The managing server issues commands to run the test executables and collects test results returned by the test executables.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Disclosed is a method for adjustably controlling a light by concurrently tracking and controlling one or more lighting devices and apparatus thereof. The light device is connected to a control unit and is provided with at least one power switch. The control unit is provided for recognizing a switch operating code and for performing an adjustable controlling or an operating of each lighting device. Therefore, the present invention can provide more convenience and completeness of lighting configuration.

Abstract: A data storage system, according to certain aspects, automatically determines the accuracy of replication data when performing data backup operations. For instance, the system performs data backup using replication data rather than source data to reduce the processing load on the source system. The backup data is then associated with the source data as if the backup had been performed on the source data. If the replication system fails, then backing up replication data results in backup data that does not accurately reflect the source data. The system automatically determines the accuracy of replication data during data backup.

Abstract: An apparatus includes: a media; a head over the media; a head actuation motor coupled to the head; control circuitry, coupled to the head actuation motor, configured to position the head; and an environmental sensor, coupled to the control circuitry, configured to measure an environmental condition; wherein the control circuitry is further configured to: perform a background task; and adjust a frequency of the background task based on the magnitude of the environmental condition.

Abstract: Techniques are provided to trace packet descriptors. A received packet may be identified. A packet descriptor associated with the received packet may be created. A trace indicator in the packet descriptor may be set. The presence of a packet descriptor with the trace indicator set may be logged by a detector.

Abstract: In one aspect, a method includes receiving a request to access a virtual volume snapshot, preparing to bind the virtual volume snapshot, intercepting a command to prepare bind of the virtual volume snapshot, rolling back to a point in time corresponding to the requested virtual volume snapshot and generating a virtual volume snapshot in a storage array.

Abstract: System and method are disclosed for managing storage space of a magnetic storage device. The system may read data from a sector of the storage space and determine whether the data are successfully read from the sector. If it is determined that the data are not successfully read from the sector, the system may retrieve an address of the sector. The system may further determine whether the sector is subject to media fatigue based on the address. If it is determined that the sector is subject to media fatigue, the system may reallocate the sector subject to media fatigue to a spare sector.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: Embodiments of systems and methods for archive verification are disclosed. More specifically, embodiments of this archive verification can comprise loading media into a drive and reading data from the media to verify that the media and data on the media can be read. In one embodiment, media can be loaded into a drive and read according to a verification policy. As part of verifying that media and data on media can be read, read errors or other verification data associated with media can be obtained. Using this verification data a result for the media may be determined.

Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

Abstract: Embodiments are directed towards managing data storage that may experience a data failure. If a repair event is associated with a data storage failure, a new repair task may be generated and added to a task list. A priority value for each repair task in the task list may be determined based in part on the mean-time-to-data-loss (MTTDL) value associated with each repair task in the task list such that a lower MTTDL may indicate a higher priority value over a lower MTTDL. One or more repair tasks may be promoted to become active repair tasks based on the priority value the repair tasks such that the promoted repair tasks have a higher priority that than other repair tasks in the task list, if any. Each active repair task may be executed to repair one or more associated the storage failures.

Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

Abstract: An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.

Abstract: The relative health of data storage drives may be determined based, at least in some aspects, on data access information and/or other drive operation information. In some examples, upon receiving the operation information from a computing device, a health level of a drive may be determined. The health level determination may be based at least in part on operating information received from a client entity. Additionally, a storage space allocation instruction or operation may be determined for execution. The allocation instruction or operation determined to be performed may be based at least in part on the determined health level.

Abstract: Systems, methods, and computer storage mediums are provided for mitigating damage to data caused by a computer process having a corrupted pointer. An exemplary method includes receiving a pointer to a memory address. The pointer is received in conjunction with a command of the computer process to access data stored at the memory address, where the data is intended to be stored in a memory segment that allows for read-only access. The memory segment that includes the memory address is analyzed to determine a modification state for the memory segment, where the modification state indicates the type of access that the memory segment allows. The computer process is halted when the modification state indicates that the memory segment allows for other than read-only access.

Abstract: A maintenance operation instance collection apparatus includes: a storage unit that includes a maintenance operation instance database in which operation information obtained from a device via a sensor and maintenance information on a measure to deal with the operation information corresponding thereto are stored in association with each other; and a control unit that receives an input of new operation information, receives an input of new maintenance information, searches the maintenance operation instance database using the newly-received maintenance information as a search key, acquires searched operation information, compares the newly-received operation information to the acquired operation information, determines whether or not the newly-received operation information is close to the acquired operation information in such a degree of satisfying a prescribed criterion, and, if the newly-received operation information is not determined to be close to the acquired operation information, prompts a re-input

Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Abstract: An integrated circuit including a first interface, a decoder, and a controller. The first interface is configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory. The decoder is configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory. The first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory.

Abstract: An apparatus can include a circuit board; a processor mounted to the circuit board; a storage subsystem accessible by the processor; random access memory accessible by the processor; a network interface; and a controller mounted to the circuit board and operatively coupled to the network interface where the controller includes circuitry to capture values stored in the random access memory, the values being associated with a state of the apparatus, and circuitry to transmit the values via the network interface. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

Abstract: Disclosed is a non-mounted storage test device based on FPGA, which comprises a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.

Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.