Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: A system of remote nodes may be divided into sets of partner nodes. One remote node becomes a partner of another remote node. As partners, the nodes agree to monitor each other's health and report anomalies, such as a failure of one of the nodes, to a monitoring server. The nodes do so using a persistent communication link, such as an open socket. Using the described techniques, the monitoring load of a system is distributed in part away from the monitoring server and to the nodes themselves. This may reduce the resources required of the monitoring server. At the same time, since nodes are now being monitored by partner nodes that are likely to be closer than the monitoring server, and/or on account of the monitoring being performed via a persistent communication link, certain failures can be detected in real-time or near real-time.

Abstract: Provided are a reconfigurable processor and a method of operating the reconfigurable processor. In the method, configuration data is requested to access based on virtual addresses, and accessing of the configuration data by using a processor core is controlled to read the configuration data from addresses of a configuration memory mapped to the virtual addresses.

Abstract: A method is provided for controlling a redundant array of independent disks (RAID). The method comprises a computer system writing data to a RAID and reading data from the RAID, wherein the RAID includes a controller and a plurality of data storage devices, including a flash data storage device. The method further comprises the controller detecting whether or not the flash data storage device is in read-only mode, and the controller preventing attempts to write data to the flash data storage device in response to detecting that the flash data storage device is in read-only mode. Optionally, when the flash data storage device is in read-only mode, the controller may redirect writes intended for the flash data storage device to empty data storage space on another data storage device or cache memory, or modify the parity stripe of a major stripe in view of the data intended to be written.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: A computer program product for managing replication configurations includes program instructions to receive a replication configuration for replicating data, wherein the replication configuration defines at least a target table in a target database based on a source table in a source database. The program instructions initialize a federated view, wherein the federated view is based on at least the source table in the source database as defined in the replication configuration. The program instructions utilize the federated view to satisfy requesting applications, where requesting applications obtain data from the federated view. The program instructions to, responsive to determining the replication of data is in spec, utilize the target table in the target database to satisfy requesting applications.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Automated modification of configuration settings for an IC (IC) includes receiving, within a data processing system, desired data for a configuration setting of an IC, reading stored data for the configuration setting. A determination is made using the data processing system that the configuration setting is static and that the stored data differs from the desired data. Responsive to the determination, configuration data including the desired data is provided from the data processing system to the IC. At least a portion of a boot process of the IC is automatically initiated, wherein the boot process uses the configuration data.

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Abstract: An information processing apparatus includes a monitoring unit that monitors a reception of a power-on instruction from a second control device among the plurality of control devices, and a prevention unit that prevents an issue of the power-on instruction to the second control device when the monitoring unit detects the power-on instruction from the second control device. Therefore, the control device can prevent the occurrence of unintended power-on operations.

Abstract: Systems and methods for backing up and restoring virtual machines in a cluster environment. Proxy nodes in the cluster are configured with agents. The agents are configured to perform backup operations and restore operations for virtual machines operating in the cluster. During a backup operation or during a restore operation, a load associated with the backup/restore operation is distributed across at least some of the proxy nodes. The proxy nodes can backup/restore virtual machines on any of the nodes in the cluster.

Abstract: Disclosed are a method and device for implementing memory migration, which relate to computer technology and are invented for solving the problem that the existing operating process for memory migration is relatively complicated. The technical solution provided in the embodiments of the present application includes: the basic input-output system of a computer migrating the data in the memory to be migrated to a first unavailable memory in the operating system of the computer when migrating the memory to be migrated and the basic input-output system storing the mapping relationship between the memory to be migrated and the physical address of the first unavailable memory. The embodiments of the present application can be applied to ordinary computer systems and computer systems under the NUMA architecture.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: For recovering from a RAID array failure in the deduplication repository, creating a new backup volume using a synchronized FC backup of the source production volume residing on an alternative RAID array.

Abstract: Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: A server includes: a first data storage device that stores therein data for use in service provided by the server; a backup data storage device that stores therein backup data for data stored in a second data storage device of another server; a service provision unit that provides the service by using the data stored in the first data storage device and by using the backup data stored in the backup data storage device; an update information creation unit that creates update information representing a content of the updating of the first data storage device; an update information transmission unit that transmits the created update information to the another server; and an update information reception unit that receives update information which is transmitted from the another server, and reflects the content of updating of the second data storage device on the backup data stored in the backup data storage device.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: Digital objects are stored and accessed within a fixed content storage cluster by using a page mapping table and a pages index. A stream is read from the cluster by using a portion of its unique identifier as a key into the page mapping table. The page mapping table indicates a node holding a pages index indicating where the stream is stored. A stream is written to the cluster by storing the stream on any suitable node and then updating a pages index stored within the cluster. The cluster recovers from a node failure by first replicating streams from the failed node and reallocating a page mapping table to create a new pages index. The remaining nodes send records of the unique identifiers corresponding to objects they hold to the new pages index. A node is added to the cluster by reallocating a page mapping table.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: In one embodiment, a tape drive includes a reserved data buffer and logic integrated with and/or executable by a processor. The logic is configured to read a data set from a medium and store a first portion of the data set to the reserved data buffer in response to a determination that the first portion of the data set is correctable using C2 error correction code (ECC). The logic is also configured to replace any stored row of a non-C2-correctable portion of the data set stored to the reserved data buffer with a corresponding row of the data set read from the medium in response to a determination that the stored row of the non-C2-correctable portion of the data set has an equal amount or more C1-correctable error therein than the corresponding row of the data set read from the medium.

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: An electronic device includes: a shelf where a first slot and a second slot are formed; a plurality of kinds of electronic circuit boards including a first-side protrusion portion and a second-side protrusion portion, and an arrangement pattern of the first-side protrusion portion and the second-side protrusion is different from each other; when an electronic circuit board having the first-side protrusion portion into the first slot, the first abutment member abut the first-side protrusion portion of the first position and rotate from a first angle position to a second angle position; a second abutment member installed at the first slot and rotatable around an axis of the first direction, and when an electronic circuit board having the first-side protrusion portion into the first slot, the second abutment member abut the first-side protrusion portion of the second position and rotate from the first angle position to the second angle position.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: A method begins by independently executing a first write transaction in a dispersed storage network (DSN) to a particular write verification step of a multiple step write process, wherein the first write transaction has a first transaction identifier. The method continues by independently executing a second write transaction in the DSN to the particular write verification step, wherein the second write transaction has a second transaction identifier, and wherein subject matter of the first write transaction is related to subject matter of the second write transaction. The method continues by dependently finalizing the multiple step write process for each of the first and second write transactions utilizing the first and second transaction identifiers when each of the first and second write transactions have reached the particular write verification step.

Abstract: An apparatus for compute and networking operation in a rack-mounted device are provided herein. An exemplary apparatus may include a compute substrate, a networking substrate, and a bridge substrate. The compute substrate may include a processor, and a memory communicatively coupled to the processor. The networking substrate may be separate from the compute substrate and include control processor, and an Ethernet switch communicatively coupled to the control processor. The bridge substrate may be communicatively coupled to the compute substrate and the networking substrate, and include at least two high-speed signal traces, the high-speed signal traces being at least one differential pair, the high-speed signal traces being communicatively coupled to the compute substrate and the networking substrate.

Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Abstract: A method, system, and/or computer program product encodes diagnostic data in an error message for a computer program. In response to an error in the processing of a computer program, a predetermined set of diagnostic data associated with the error is selected. The predetermined set of diagnostic data is encoded in an image, and the image is displayed in association with an error message for the error.

Abstract: A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: A data processing system includes a command buffer and control circuitry. The command buffer is configured to store pending write requests to a memory in which each pending write request has corresponding write data. The control circuitry is configured to select a pending write request from an entry of the command buffer and send the selected write request to the memory. The selected write request is a partial write request having first write data stored in the entry. Sending the selected write request includes performing a read-modify-write (RMW), wherein the control circuitry is configured to, after a read operation of the RMW, update the pending write request in the entry from a partial write request to a full write request.

Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

Abstract: A technique for protecting stored information from read disturbance includes receiving a first write request to a solid-state device (SSD) in a storage pool that employs an erasure code. The first write request has an associated identifier and associated data. In response to receiving the first write request, the first write request is assigned to two or more SSD blocks of the SSD device based on the identifier. Pages of the associated data are then written to the assigned SSD blocks, such that each SSD block holds data associated with only a single identifier.

Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

Abstract: A transceiver and a transceiver operating method are disclosed. The transceiver is coupled to a bus. The transceiver includes a receiving unit, a transmitting unit, and a detection unit. The receiving unit is coupled to the bus. The transmitting unit is coupled to the bus. The detection unit is coupled to the receiving unit and the transmitting unit respectively. The detection unit receives a first input signal, a receiver enabling signal, and a transmitter enabling signal respectively and selectively enhances the first input signal and the transmitter enabling signal according to a result of comparing the receiver enabling signal and the transmitter enabling signal. Then, the detection unit transmits the enhanced first input signal and transmitter enabling signal to the bus through the transmitting unit.

Abstract: Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.

Abstract: An image-forming apparatus to process a job includes volatile memory, non-volatile memory, a judging unit, a calculating unit, a defining unit, and a controller. The volatile memory stores a generated error log using a memory area. The non-volatile memory stores information for identifying an overwrite restricted error. The judging unit judges whether a generated error is a particular error. The calculating unit calculates remaining memory which is changed by a subsequent error log being written secured, with a position where a particular error log is written in the volatile memory as a reference, where the error is the particular error. The defining unit defines an acquisition level of an error log in a stepwise manner based on the calculated remaining memory. The controller outputs an error log to an apparatus according to the defined acquisition level being a particular level at which an error log has to be output.

Abstract: Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.

Abstract: According to one general aspect, an apparatus may include a trace control register, a first output path, and a second output path. The trace control register may be configured to receive one or more signals output by a combinatorial logic block. The trace control register may include a first register portion configured to capture the one or more signals. The trace control register may include a second register portion configured to capture whether an event occurred within the combinatorial logic block. The occurrence of the event is determined by at least a portion of the one or more signals having a predetermined state. The first output path configured to select between a plurality of captured signals provided by respective trace control registers. The second output path configured to output one or more captured events provided by one or more respective trace control registers.

Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: Statistical wear leveling is described that may be particularly useful for non-volatile system memory. In one embodiment, the invention includes a wear level move state machine to select an active block based on a wear criteria, to move the contents of the selected active block to a block from a free block list, and to move the selected active block to an unused block list, a free block list expansion state machine to take a block from a target free block list, to move the contents of the block to a block from the unused block list, and to move the block taken from the target block list to a free block list, and a target free block generation state machine to select blocks from the unused block list and to move the selected blocks to the target free block list.

Abstract: A controller includes an address generator that sets a plurality of different paths, each connecting an information processing apparatus connected to a storage apparatus via a network, first and second storage mediums, and the controller, and generates a second address that is different from a first address used for a communication with the information processing apparatus via the network; an access monitor that determines that no access has been issued for a certain time duration from the information processing apparatus to the first or second storage medium; an access issuing unit that issues a test access to the first and second storage mediums on one of the paths, using the second address; and an access decoder that converts the test access to an access including the first address, receives a result of the access including the first address from the first or second storage mediums, and checks for an error.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: Disclosed is a method for adjustably controlling a light by concurrently tracking and controlling one or more lighting devices and apparatus thereof. The light device is connected to a control unit and is provided with at least one power switch. The control unit is provided for recognizing a switch operating code and for performing an adjustable controlling or an operating of each lighting device. Therefore, the present invention can provide more convenience and completeness of lighting configuration.

Abstract: A computer system has a managing server for managing one or more managed nodes. The managed nodes have media encoded with test executables executable on their respective nodes. The test executables can check configuration data for the node and/or check whether external resources are accessible from the node. The managing server issues commands to run the test executables and collects test results returned by the test executables.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: A data storage system, according to certain aspects, automatically determines the accuracy of replication data when performing data backup operations. For instance, the system performs data backup using replication data rather than source data to reduce the processing load on the source system. The backup data is then associated with the source data as if the backup had been performed on the source data. If the replication system fails, then backing up replication data results in backup data that does not accurately reflect the source data. The system automatically determines the accuracy of replication data during data backup.

Abstract: An apparatus includes: a media; a head over the media; a head actuation motor coupled to the head; control circuitry, coupled to the head actuation motor, configured to position the head; and an environmental sensor, coupled to the control circuitry, configured to measure an environmental condition; wherein the control circuitry is further configured to: perform a background task; and adjust a frequency of the background task based on the magnitude of the environmental condition.