Timing Error (e.g., Watchdog Timer Time-out) Patents (Class 714/55)
  • Patent number: 10271193
    Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 23, 2019
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS GMBH
    Inventors: Thierry Meziache, Pierre Rizzo, Alexandre Charles, Juergen Boehler
  • Patent number: 10191793
    Abstract: A microprocessor comprises a timer capable of resetting the device and a plurality of hardware registers (4) arranged logically so that a collective predetermined state of the registers (4) prevents the device from resetting. The device further comprises software (2) with a plurality of functions arranged to place said registers (4) in said predetermined state if each of said functions has executed properly.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 29, 2019
    Assignee: Nordic Semiconductor ASA
    Inventors: Lasse Olsen, Joar Rusten, Arne W. Venas
  • Patent number: 10148470
    Abstract: A method includes receiving a data signal over a multi-input multi-output (MIMO) channel. The method further includes equalizing the data signal, by an adaptive equalizer circuit having an associated target, to provide an equalized output of the data signal. As part of the method, taps of the equalizer circuit and coefficients of the target are estimated. A constraint is imposed on the coefficients of the target as part of the estimation of the coefficients of the target. A similar minimization process is used with constraint imposed on whitening filter taps associated with a DDNP detector in the MIMO channel.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 4, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Belkacem Derras, Raman Venkataramani, William M. Radich
  • Patent number: 10055004
    Abstract: A redundant system is provided with a redundant failure detection configuration, and thereby is enabled to precisely detect a failure occurrence, and reliably execute a necessary system switching operation. In a redundant system 10, each of power supply mechanisms 200 for computers 150, 180 redundantly provided includes a processor 204 configured to: monitor a write process in which predetermined information from another apparatus 300 or another mechanism 112 of the corresponding computer 150 or 180 is written to a storage 201 of the power supply mechanism 200; execute an operation of powering off or resetting a power supply device 230 if the write process is not in conformity with a predetermined rule; and after the execution of the operation, give an instruction to perform a fail-over operation to the other computer out of the computers 150, 180.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 21, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Omata, Nobutaka Okamoto, Takafumi Jinsenji
  • Patent number: 10006455
    Abstract: There is provided a drive control apparatus that can maintain a drive control system to be in a safe state even in a case where operational abnormality of avoiding a normal reset of a control processor or operational abnormality of avoiding solution even after resetting the control processor occurs in the control processor. The control processor includes an actuator control processing unit configured to generate a control signal for a drive circuit being a control target apparatus and an actuator, and a diagnosis processing unit configure to diagnosing the actuator control processing unit. The diagnosis processing unit cyclically outputs a reset signal to WDT in a case where the operation of the control processor is normal. The WDT continuously outputs a cutoff signal for cutting off a supply of the control signal from the control processor to the control target apparatus when the cyclic reset signal stops.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 26, 2018
    Assignee: FUJI ELECTRIC CO., LTD
    Inventors: Hirokazu Tajima, Hiroji Nishida
  • Patent number: 9898722
    Abstract: Systems and methods for processing custom structured tags at a self-service terminal are disclosed. Custom structured tags received by a self-service terminal can include information to identify one or more devices attached to the terminal and identify one or more types of data to be obtained from a user by use of the attached devices. In some embodiments, a browser can natively interpret the custom structured tags. The self-service terminal can also be configured to receive and decode structured tags identifying or more actions to be performed by the device, such as printing a transaction record or dispensing currency.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: February 20, 2018
    Assignee: NCR Corporation
    Inventor: Wolf-Dieter Rossmann
  • Patent number: 9727345
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 9720761
    Abstract: Disclosed are a method, a device, and a computer readable storage medium for detecting and processing a system fault. The method includes: an interrupt service routine sending a first stage kicking dog signal, and receiving a second stage kicking dog signal for a system detection task (S101); and when task dead loop or task abnormity is detected, performing system abnormity processing according to a preset processing policy, wherein when the interrupt service routine fails to receive the second stage kicking dog signal within a set period of time, the interrupt service routine stops sending the first stage kicking dog signal, and the system reboots (S102).
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: August 1, 2017
    Assignee: ZTE CORPORATION
    Inventors: Guangbo Yu, Huaiyun Zhu, Jing Qiu
  • Patent number: 9672111
    Abstract: A load control backup signal generating circuit for supplying a backup control signal to a switch of a load connected to an output of a control processor in a case that abnormality occurs in the control processor, includes a first input terminal that receives a constant period signal that is output periodically from the control processor when the control processor is normal, a constant period signal monitoring section that monitors a state of the constant period signal for identifying whether a length of the time during which a high or low level state of the constant period signal continues is longer than a predetermined time, and that outputs the signal corresponding to a result of the identification, and a backup signal output section that outputs the backup control signal when the output of the constant period signal monitoring section satisfies a predetermined condition.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 6, 2017
    Assignee: Yazaki Corporation
    Inventor: Kazuhisa Wataru
  • Patent number: 9665429
    Abstract: A method begins by a computing device sending a set of redundant dispersed storage error encoding write requests regarding a data object to a set of dispersed storage (DS) processing modules. The method continues with the set of DS processing modules dispersed storage error encoding the data object to produce a group of pluralities of sets of encoded data slices. The method continues with a set of storage units temporarily storing the group of pluralities of sets of encoded data slices. The method continues with the set of storage units permanently storing encoded data slices of the group of pluralities of sets of encoded data slices based on successful execution of a storage verification process to produce a plurality of sets of encoded data slices.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 9602099
    Abstract: An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 21, 2017
    Inventors: Jiong-Guang Su, Hung-Wen Chou
  • Patent number: 9563494
    Abstract: The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. A capture mechanism is configured to write a second state value to each bit of the status register that is associated with an entity that is presently associated with a first type of entity status information, in response to a detection that the trigger data pattern is written to the status register.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 7, 2017
    Assignee: NXP USA, Inc.
    Inventors: William C. Moyer, Michael Kardonik
  • Patent number: 9513330
    Abstract: In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Mladenko Vukic, Kalyan C. Kolluru
  • Patent number: 9455976
    Abstract: A network-based appliance includes a mechanism to erase data on the appliance's local storage. The appliance's normal system reset operation is overridden to enable a local user to place the appliance into a safe mode during which remote erasure of the storage is permitted, provided that mode is entered within a first time period following initiation of a system reset. If the appliance is placed in the mode within the time period, it can then receive commands to wipe the local storage. Once the safe mode is entered by detecting one or more actions of a local user, preferably the appliance data itself is wiped by another person or entity that is remote from the device. Thus, physical (local) presence to the appliance is necessary to place the device in the safe mode, while non-physical (remote) presence with respect to the appliance enables actual wiping of the storage device.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ivan Matthew Milman, Ronald Dwayne Martin, Kalpesh Hira
  • Patent number: 9430314
    Abstract: A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 30, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sunil Atri, Cliff Zitlaw
  • Patent number: 9430310
    Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: August 30, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideo Isogai
  • Patent number: 9400490
    Abstract: A method automatically recovers from a fault situation in a production plant and provides production resources and a manufacturing execution system having a production modeler for modeling the production resources into a plant model and a production scheduler to schedule operations of the modeled production resources. A production controller executes the production process and a fault manager detects fault situations and automatically decides a corrective action. A production resource runs an application for the operation of the production resource and a fault analysis agent provides categorized error situations and checks operational data representing the operation of the production resource against the categorized error situations and when, an error situation occurs, forwards an error event to the fault manager. The error events are collected and then analyzed by a neural network system to assign the error event to an error category. A corrective action is executed on the production resource.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: July 26, 2016
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Andrea Turolla
  • Patent number: 9367377
    Abstract: An apparatus and method for monitoring multiple micro-cores enable one watchdog to monitor a plurality of micro-cores. The multiple micro-core monitoring apparatus includes: a plurality of micro-cores that periodically output clear signals having different pulse waves; and a watchdog that respectively receives the clear signals having different pulse waves so as to determine presence or absence of an error in the micro-cores, and reset an erroneous micro-core.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: June 14, 2016
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Hyundai Autron Company, Ltd.
    Inventors: Choong Seob Park, Hyung Ju Lee, Hak Mo Yoo, Ji Haeng Lee, Doo Jin Jang, Kang Hee Cho, Si Kwang Lee
  • Patent number: 9348684
    Abstract: An in-vehicle electronic control device for diagnosing the details of an abnormality of a microcomputer appropriately is provided. A monitoring function for detecting a malfunction by monitoring input/output of a main function of a hardware part and a monitoring function for detecting an abnormality by monitoring the calculating result of a main function in a software part are provided in a microcomputer. The main function to be monitored is implemented with a different structure than the malfunction/abnormality monitoring function. Furthermore, a malfunction processing circuit for monitoring an abnormality of the microcomputer is provided outside the microcomputer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: May 24, 2016
    Assignee: NSK Ltd.
    Inventors: Yuho Aoki, Shuji Endo, Kenichi Okamoto
  • Patent number: 9304844
    Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kapil Bansal, Girish Bhat, Subodh Singh, Victor Wong, Pradeep Atur
  • Patent number: 9298556
    Abstract: An advantageous watchdog function deduces faulty operation of a graphics processing unit from historical-indicating parameters while also accommodating more active testing performed by an application. When a GPU fault is detected, the example non-limiting technology rapidly resets the GPU during an interframe time so the GPU is ready to process new frame instructions or display lists and avoids missing or skipping further frames.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: March 29, 2016
    Assignee: NINTENDO CO., LTD.
    Inventor: Carl Mueller
  • Patent number: 9116740
    Abstract: A method and system for generating a heartbeat of a process including at least one machine configured to perform a process cycle consisting of a plurality of timed events performed in a process sequence under an identified condition includes determining the duration of each of the timed events during the process cycle performed under the identified condition, ordering the durations of the plurality of timed events in the process sequence, and generating a heartbeat defined by the ordered durations of a process cycle. The identified condition may be one of a design intent, baseline, learnt, known, current or prior condition. The variance of the heartbeat between a first and at least a second identified condition may be analyzed to monitor and/or control the process or machine. The system may display the process heartbeat information and may generate a message in response to the heartbeat and/or variance thereof.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: August 25, 2015
    Assignee: BEET, LLC.
    Inventor: David J. Wang
  • Patent number: 9100274
    Abstract: A configurable advertisement count and skew timer in a virtual router can be used to improve the speed with which a backup virtual router assumes the role of master upon the master router's failure. Enhanced VRRP packets having a type other than one may be used to cause MAC address movement from a failed master router to a backup router assuming the role of master router without placing an undue load on other routers in the network, such as by dropping the enhanced VRRP packets having a type other than one without processing the packets in the control plane of a receiving virtual router.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: August 4, 2015
    Assignee: Juniper Networks, Inc.
    Inventor: Sandip Kumar Ghosh
  • Publication number: 20150135021
    Abstract: Context captured with sensors of an information handling system is applied to selectively lock access to currently unlocked information, with conditions for locking access based upon the context. Nervous states enforce locking of selected information based upon the confidence of the security of the information under sensed external conditions. Increased sensitivity for locking access includes reduced timeouts to a lock command, increased response to sensed conditions, and more rapid response where unlocked access is to sensitive information.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: DELL PRODUCTS L.P.
    Inventors: Charles D. Robison, Liam B. Quinn, Rocco Ancona, Roman Joel Pacheco
  • Patent number: 9032258
    Abstract: Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies AG
    Inventors: Richard Knight, Simon Brewerton
  • Publication number: 20150127997
    Abstract: This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 7, 2015
    Inventor: Gary L. Swoboda
  • Publication number: 20150113340
    Abstract: Embodiments of the present invention provide a method for implementing a heartbeat service of a high availability cluster, including: writing, by a server, heartbeat counting information to a disk array, where the heartbeat counting information includes a write heartbeat message sequence number, a read peer heartbeat message sequence number, active-standby state information, a heartbeat message, and a heartbeat message length of the server, so that one or more corresponding servers read the heartbeat counting information, in the disk array, of the server; and reading heartbeat counting information, which is written by the one or more corresponding servers to the disk array, of the one or more corresponding servers, and repeating the write operation and the read operation. Correspondingly, the embodiments of the present invention further provide a server, which solves a spit-brain problem, and improves data security.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 23, 2015
    Inventor: Junli GAO
  • Publication number: 20150095724
    Abstract: The present invention provides a watchdog apparatus in which a main MCU and a sub MCU are connected by SPI communication, including: a token generating unit which generates a seed value and generates at least two tokens using the seed value; a watchdog signal generating unit which generates a watchdog signal corresponding to the generated token; a signal determining unit which determines whether the generated watchdog signal is in a normal state and thus provides an advantageous effect which may detect an abnormality of the MCU only using a software logic without providing an additional configuration.
    Type: Application
    Filed: September 4, 2014
    Publication date: April 2, 2015
    Inventor: Jaehyun PARK
  • Patent number: 8996927
    Abstract: An electronic control device includes: a processing unit that performs a predetermined process in accordance with a program; a watchdog timer that includes a time counter reset by a pulse signal output at a given period from the processing unit and outputs a signal having levels inverted depending on whether an overflow occurs; and a latch circuit that latches the signal output from the watchdog timer and outputs a signal obtained through the latching as a first output enable signal. The processing unit stops the output of the pulse signal, when diagnosing a malfunction of the watchdog timer, and diagnoses the malfunction of the watchdog timer based on the first output enable signal output from the latch circuit, after stopping the output of the pulse signal.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 31, 2015
    Assignees: Keihin Corporation, Honda Motor Co., Ltd.
    Inventors: Taku Yoshikawa, Takeshi Yamada, Shinichi Daibo, Yuichi Kobata
  • Publication number: 20150089307
    Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.
    Type: Application
    Filed: November 28, 2014
    Publication date: March 26, 2015
    Inventor: Hideo Isogai
  • Publication number: 20150089302
    Abstract: Methods and apparatus to provide failure detection are disclosed herein. An example method to synchronize data operations between multiple workload units in a computing device to facilitate failure detection includes identifying a number of first data operations to write data from a computing node in a first workload unit to locations that are not in a local cache of the computing node and are not in a memory of the first workload unit, the first data operations corresponding to a set of computing instructions that are assigned to the first workload unit and, when a flag in the first workload unit has been set to a first value, synchronizing the first data operations with second data operations by a second workload unit.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 26, 2015
    Inventors: Joshua Bruce Fryman, Allan Knies
  • Patent number: 8984352
    Abstract: [This invention] inhibits the response time of the storage control apparatus from being longer even if the response time of the storage apparatus is long. The disk adapter (DKA), receiving a read message from the channel adapter (CHA), sets the timeout time in accordance with specified conditions, and tries to read data from the storage apparatus 4. As the timeout time, either the normal value or the shortened value is selected. If a timeout error occurs, the read job is reset, and correction read is started.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: March 17, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Eiju Katsuragi
  • Patent number: 8977889
    Abstract: A method for decreasing the risk of monitoring data failing to be stored includes periodically sending a test message from the monitoring device to a Networked Storage Device, NSD, generating an NSD fail signal in the monitoring device if events following the sending of the test message indicates that the NSD is not operating properly, and sending, in response to the NSD fail signal, a fail message from the monitoring device for detection outside housing of monitoring device.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Axis AB
    Inventors: Ola Angelsmark, Fredrik Nyberg, Bjarne Rosengren
  • Patent number: 8977911
    Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Michael Sheets, David G. Wright
  • Publication number: 20150067414
    Abstract: Described herein are techniques for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventors: Ashutosh Tripathi, Vikas Gupta, Bob Fozard, Tomasz Barszczak
  • Publication number: 20150067413
    Abstract: Described herein are methods for transitioning control between a first and second controller of a storage system. In such transition, the first controller transmits a message to a memory element shared by the first and second controllers, the message capable of notifying the second controller of an imminent failure of the first controller. The second controller receives the message from the shared memory element, the message notifying the second controller of an imminent failure of the first controller. Subsequent to transmitting the message to the shared memory element, the first controller becomes unavailable to facilitate access to the storage devices of the storage system. Subsequent to receiving the message from the shared memory element, the second controller becomes available to facilitate access to the storage devices of the storage system.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Ashutosh Tripathi, Vikas Gupta, Bob Fozard, Tomasz Barszczak
  • Patent number: 8972802
    Abstract: A method, system and computer program product for providing high availability to a hybrid application server environment containing non-Java® containers. Each hybrid application server in the cluster includes a Java® container and a non-Java® container hosting Java® and non-Java® applications, respectively. Upon detecting the non-Java® container becoming unavailable (failing), an object, such as an MBean, identifies and deactivates those Java® application(s) that are dependent on the non-Java® application(s) deployed in the unavailable non-Java® container using dependency information stored in an application framework. The deactivated Java® application(s) are marked as being unavailable. A routing agent continues to send requests to those Java® application(s) that are not marked as being unavailable within that hybrid application server containing the unavailable non-Java® container.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amith N. Kashyap, Rohit D. Kelapure, Hariharan N. Venkitachalam
  • Patent number: 8972803
    Abstract: Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been invoked to process a transaction. A forward progress counter is monitored to determine whether the component is processing the transaction, wherein the forward progress counter increments at determined intervals when the component is processing the transaction. A test transaction is executed for the component when a determination is made that the forward progress counter has not incremented for a threshold fault period. A fault alarm indicator is generated based on the determination that the forward progress counter has not incremented for the threshold fault period.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Alcatel Lucent
    Inventor: Kevin W. McKiou
  • Publication number: 20150052407
    Abstract: A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Inventor: Takashi FUCHIGAMI
  • Publication number: 20150033085
    Abstract: Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventors: Mihai-Alexandru Ionescu, Christoph Schroers, Davide Cassata, Hubert Fischer, Wolfgang Horn
  • Patent number: 8943303
    Abstract: A method of monitoring a processing circuit is disclosed. The processing circuit is operable, in a normal operation mode, to generate a sequence of trigger commands, with at least one trigger command of the sequence of trigger commands including time information. At least one window sequence with a closed window period and an open window period is generated such that the duration of the closed window period and/or the open window period is defined, at least in part, by the time information. It is detected if one trigger command is received within the open window period of the at least one sequence.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies AG
    Inventors: Martin Kaltenegger, Michael Hausmann
  • Patent number: 8928479
    Abstract: An automatic alarm system is described that is triggered by the lack of event at one or more portable remote unit(s). The system includes an electromagnetic interface from a plurality of portable units to a central command and monitoring element. This automatic triggering of an alarm condition adds security to the users of the system since it is not always feasible to explicitly trigger an alarm when in danger.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: January 6, 2015
    Inventors: Troy Gonsalves, Geoffrey Vanderkooy, Philip Thomas, Robert Young
  • Patent number: 8930777
    Abstract: A method for operating an electronic device that is supplied with electric power by a continuous energy accumulator. A predetermined ending of the first program is monitored in a program step by a second program. If the first program is not switched off as predetermined, the second program generates an error message which is displayed immediately when the device is switched on again.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: January 6, 2015
    Assignee: Continental Automotive GmbH
    Inventors: Wolfgang Bay, Michael Henninger
  • Publication number: 20150006978
    Abstract: A memory 225 stores the log information of respective cores 116 to 118. If an abnormality occurs in any core, each core writes the log information, being stored in the memory 225, thereof into a backup storage device 126. Thus, the log information of cores other than the core in which the abnormality occurs can be saved in the backup storage device 126.
    Type: Application
    Filed: February 13, 2012
    Publication date: January 1, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Toshiro Tokunaga, Shinichi Ochiai
  • Patent number: 8909997
    Abstract: A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Fuchigami
  • Patent number: 8909995
    Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: December 9, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kazumasa Ozawa
  • Patent number: 8904245
    Abstract: Upon receiving a particular data unit by a receiving layer of a wireless device, it is detected that a previous data unit earlier in sequence to the particular data unit has not yet been received by the receiving layer. A timer is started in response to the detecting, where the timer has a time-out period that is variable dependent upon a parameter associated with receipt of the particular data unit. Upon expiration of the timer based on the timeout period, the receiving layer generates an error indication.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: December 2, 2014
    Assignee: Apple Inc.
    Inventors: Narendra Tilwani, Sairamesh Nammi
  • Patent number: 8887004
    Abstract: According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki Terayama
  • Patent number: 8862911
    Abstract: An information processing apparatus includes a processing unit, a power supply control unit configured to control powering on and off of the processing unit, and a controller unit configured to access the processing unit irrespective of a power supply state of the processing unit. The power supply control unit powers off a processing unit that is not in use, powers on a processing unit that is accessed by the controller unit, and outputs a predetermined control signal to the controller unit. The controller unit recognizes that an error occurs in a case where, after accessing a processing unit, the controller unit does not receive a response from the accessed processing unit until a time-out time elapses, and delays recognizing the error when the control signal is received.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Aoyagi
  • Patent number: 8862938
    Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: October 14, 2014
    Assignee: General Electric Company
    Inventor: Manyphay Souvannarath