Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: A method, apparatus and system for improving failover within a high-availability computer system are provided. The method includes obtaining one or more parameters associated with at least one resource of any of the first cluster, second cluster and high-availability computer system. The method also includes detecting, as a function of the parameters, one or more anomalies of any of the first cluster, second cluster and high-availability computer system, wherein the at least one anomaly is a type that impacts the failover. These anomalies may include anomalies within the first and/or second clusters (“intra-cluster anomalies”) and/or anomalies among the first and second clusters (“inter-cluster anomalies”). The method further includes generating an alert in response to detecting one or more of the anomalies.

Abstract: Upon receiving a particular data unit by a receiving layer of a wireless device, it is detected that a previous data unit earlier in sequence to the particular data unit has not yet been received by the receiving layer. A timer is started in response to the detecting, where the timer has a time-out period that is variable dependent upon a parameter associated with receipt of the particular data unit. Upon expiration of the timer based on the timeout period, the receiving layer generates an error indication.

Abstract: Embodiments of the present invention provide a system that leverages the Operational Support System(s) (OSS) and Business Support system(s) (BSS) of a (e.g., public) computing Cloud with a service to automate virtual instance restarts. For example, under embodiments of the present invention, a failed virtual instance is detected within the Cloud computing environment, and a request for a new virtual instance is received in response thereto. Upon receiving the request, an entitlement of a user associated with the failed virtual instance will be tested. Specifically, a set of authentication calls and checks are deployed in accordance herewith to ensure the integrity of the requests, as well as the authorization of the requester for the resource use. Assuming testing is passed, a countdown timer associated with the failed virtual instance will be decreased. When the countdown timer reaches a predetermined threshold (e.g.

Abstract: There is provided a method for operating a basic input/output system (BIOS) of a pay-as-you go computer system. In one example embodiment, the method includes periodically resetting a watchdog timer, wherein failure to reset the watchdog timer indicates a security violation. In another example embodiment, the method also includes comparing a first time count representing motherboard use time with a second time count representing hard drive use time to determine if a security violation has occurred. There is also provided a pay-as-you-go computer system having a BIOS configured to determine if a hard drive is password protected. In an example embodiment, the BIOS is configured to calculate a password to unlock the hard drive if the hard drive is password protected.

Abstract: An apparatus, and an associated method, reports when incidence of email or other data-message communication of a wireless network system. An analyzer analyzes logged information and determines the incidence, such as by calculating a ratio, of delayed versus timely message communications. If the ratio, or other indication, is beyond a threshold, a reporter generates a report to alert the high incidence of delayed communications.

Abstract: Systems and methods are disclosed for automated notification systems. A representative system, among others, can be summarized as follows. A host computer system, or base station, is designed to monitor travel data corresponding to a mobile thing and to initiate a notification communication to a personal communications device (PCD) indicating travel status of the mobile thing (MT) to a remote computer system. The remote computer system, within or associated with the PCD, is designed to detect a failure to receive the notification communication and to cause one or more tasks to be performed based upon the notification communication failure.

Abstract: Techniques for monitoring distributed software health and membership of nodes and software components operating in a compute cluster are disclosed. In one embodiment, each node in the compute cluster operates a watchdog monitoring component in addition to software operating components. The watchdogs are provided with a list of all nodes in a compute cluster that identifies every node's neighboring nodes. Each watchdog checks the health of one of its neighboring node, ensuring that this neighboring node is healthy and is operating successfully. Additionally, each watchdog verifies the cluster membership of its other neighboring nodes to ensure that the cluster is operating an adequate number of operating nodes, and that an adequate number of watchdogs are present in the cluster. If an unhealthy or non-member node is identified, the watchdog may initiate corrective action and attempt to restore the node to a correct operational state.

Abstract: In an example embodiment, a method is provided for scheduling a check to detect anomalies in a computing system. An average time between the anomalies that are detectable by the check is identified and additionally, a runtime of the check is identified. A frequency of the check is then calculated based on the average time between the anomalies and the runtime of the check, and execution of the check may be scheduled based on the calculated frequency.

Abstract: The invention provides for software fault detection. A software process tracks its own progress. In the event the timer times out, a handler checks the progress. If the progress meets a fault criterion, a fault response is executed.

Abstract: An application attempts to use a first protocol stack to send a first message to a server. After attempting to send the first message to the server, the application attempts to use a second protocol stack to send a second message to the server. After attempting to send the second message to the server, the application performs a timeout activity before a timeout period for the second message expires when the first message timed out. Alternatively, when the timeout period for the second message expires and the first message did not time out, the application performs the timeout activity. When the client device received a response to the second message from the server before the timeout period for the second message expires, the application performs a different activity.

Abstract: A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset.

Abstract: A computing system is provided and includes first computing resources representing a fraction of total computing resources, second computing resources representing at least a partial remainder of the total computing resources except for the first computing resources, and a memory unit. The memory unit includes a computer-readable medium having computer-readable executable instructions stored thereon that are accessible to at least the second computing resources. When executed, the executable instructions cause the second computing resources to monitor a process running on the first computing resources in accordance with pre-selected parameters, to determine that a potential lock or wait situation that impedes the process is in effect from a result of the monitoring and to execute an action in response to the potential lock or wait situation.

Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation.

Abstract: A multi-CPU system including plural CPUs, comprising a failure state detection unit for detecting a failure in an operating program, and a recovery unit for determining, when the failure state detection unit has detected a failure, whether or not recovery of data involved in the failure is possible on the basis of content of the detected failure, and for recovering the data when recovery is determined to be possible.

Abstract: An electronic device and wireless base station for maintaining a persistent connection are provided. In an embodiment, a system includes an electronic device that connects to a web-server via a physical link that is bandwidth-constrained. The physical link also includes a wireless base station and at least one network address translation (“NAT”) router that is configured to terminate idle connections between the client and the web-server. One of the electronic device and the wireless base station is configured to send keep-alive packets to the web-server in order to reduce the likelihood of the NAT router terminating the connection. The keep-alive packets are sent on a variable basis that is intended to reduce bandwidth consumption while ensuring that the NAT router does not deem the connection idle and terminate the connection.

Abstract: A method for intelligently reporting errors is disclosed herein. In one embodiment, such a method includes detecting an error and determining whether the error belongs to an error group. Such an error group may include errors that together are an indicator of a potentially more serious error or condition. The method may further determine whether all errors in the error group have occurred within a specified time period. If all errors in the error group have occurred within the specified time period, the method automatically sends a notification to an administrator or other hardware or software-based system so that the problem or error can be addressed. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.

Abstract: An electronic control device according to an embodiment of the present invention includes an arithmetic device such as a microcomputer having a watchdog timer circuit, and a runaway monitoring circuit which monitors the arithmetic device for an operational failure by receiving a pulse output from the arithmetic device, in which the watchdog timer circuit or the runaway monitoring circuit detects occurrence of a failure of the arithmetic device according to the state (high level or low level) of an indication signal (wakeup signal) which shows the operational state of the arithmetic device.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A method for operating a system, as well as a computer program and a computer program product for executing the method. In the method for operating a system, which includes a plurality of control units, in the event that a special state exists for one of the control units, at least one of the other control units is informed about it.

Abstract: A system and method for distributed fault detection. In an exemplary method, unplanned application exits and crashes may be detected at a node local level. Further, application hangs may be detected using at least one of a script and a binary at the node local level. Also, node crashes and operating system crashes may be detected using node to node heart-beating.

Abstract: An RTC, having a crystal oscillator of different characteristics from those of a crystal oscillator, is provided, and the pulse period of the pulse signal from the RTC and the pulse signal based on the crystal oscillator are compared to detect a fault in the crystal oscillator. As a result, even if, for example, located in a high temperature environment, the degrees to the decrease in frequency will be different, thus making it possible to detect reliably a fault in the crystal oscillator.

Abstract: Embodiments of the present invention provide a system that leverages the Operational Support System(s) (OSS) and Business Support system(s) (BSS) of a (e.g., public) computing Cloud with a service to automate virtual instance restarts. For example, under embodiments of the present invention, a failed virtual instance is detected within the Cloud computing environment, and a request for a new virtual instance is received in response thereto. Upon receiving the request, an entitlement of a user associated with the failed virtual instance will be tested. Specifically, a set of authentication calls and checks are deployed in accordance herewith to ensure the integrity of the requests, as well as the authorization of the requester for the resource use. Assuming testing is passed, a countdown timer associated with the failed virtual instance will be decreased. When the countdown timer reaches a predetermined threshold (e.g.

Abstract: An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides serial communications with a host device through a USB data channel. The burst controller is coupled to the USB core. The burst controller detects an EFT/B event and automatically reconnects the USB core to the host device in response to recognition of a suspend state of the USB core by the host device.

Abstract: A method and system for identifying runaway software agents operating in a computer system is disclosed. An operating window is defined for an agent. The operating window specifies the maximum desired operating time for the agent. When an agent begins operation, its start time is recorded. At a later time, a measurement is made comparing the start time and current measurement time to the operating window. If the comparison indicates that the agent has exceeded the operating window, the agent is identified as a runaway agent. The computer system processes data associated with the runaway agent and displays it to a user interface such as a monitor.

Abstract: A printer comprising a reception unit for receiving a command or data sent from a host computer, a timer for counting elapsed time after the command or data is received, and an error detection unit for reporting that the host computer is in an error state when the command or data from the host computer is not received within a predetermined time after the timer starts counting the elapsed time.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input module, a watchdog control module, and a frequency increasing module. The input module inputs an initial frequency of a CPU to the frequency generator to adjust a real-time frequency of the CPU. The watchdog control module sends a counter signal to the watchdog timer in a preset time interval. The watchdog timer receives the counter signal. If the watchdog timer does not receive the counter signal within the preset time, the watchdog timer outputs a reset signal to restart the computer. The frequency increasing module adds a preset increment to the real-time frequency to obtain a newly adjusted frequency, and provides the newly adjusted frequency to the frequency generator to adjust the real-time frequency.

Abstract: A program product is embedded in a media accessible by a computer operative to request a plurality of program tasks for wakeup so as to execute the plurality of program tasks in a predetermined schedule. The program product causes at least one of the computer and another computer to execute the instructions of measuring a delay period between a request of at least one of a plurality of program tasks and a wakeup thereof. The instructions include comparing the measured delay period with a predetermined first timeout value, thus determining whether at least one of the plurality of tasks is abnormally executed by the computer based on the comparison result.

Abstract: An electronic device and method for detecting operative states of components in the electronic device includes determining a selected component of the electronic device, and setting a threshold time of the selected component. In response to the electronic device detecting a first interrupt instruction from the selected component, a timer of the electronic device is enabled to time the threshold time. Upon the condition that the threshold time elapses, the selected component is determined to be in an abnormal state. Then the selected component is restarted and initialized.

Abstract: In one embodiment, a method comprises executing respective workload management processes within a plurality of computing compartments to allocate at least processor resources to applications executed within the plurality of computing compartments, selecting a master workload management process to reallocate processor resources between the plurality of computing compartments in response to requests from the workload management processes to receive additional resources, monitoring operations of the master workload management process by the other workload management processes, detecting, by the other workload management processes, when the master workload management process becomes inoperable, and selecting a replacement master workload management process by the other workload management processes in response to the detecting.

Abstract: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and outputs of the primary instance and gates those inputs to the backup instance once a given input has been processed. The outputs of the backup instance are then compared with the outputs of the primary instance to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup instance to take over for the primary instance in a fault situation wherein the primary and backup instances are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment.

Abstract: A restoration device for restoring a system when the BIOS falls in a stall failure includes a first watchdog timer and a second watchdog timer, a setter for setting timer values respectively in the first watchdog timer and in the second watchdog timer, a suspender for suspending the decrement of the timer value of the first watchdog timer when the BIOS is started and also execution of a BIOS process is started, a switch for switching the BIOS data region for starting when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a resetter for resetting the system when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a suspender for suspending the decrement of the timer value of the second watchdog timer when the BIOS of the system starts and a resetter for resetting the system when the timer value of the second watchdog timer becomes equal to 0 or a prescribed number.

Abstract: A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path.

Abstract: Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states. Also described are applications for stabilization of operating systems and other hardware or software configurations, apparatus and methods for ensuring eventual invariance of software executed by a processor, and apparatus and methods for enforcing fixed software configurations.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met, and recovering in a recovering step back from any of the nx escalation levels to a previous level or mode, if a de-escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.

Abstract: A timer circuit for a mobile communication terminal includes a counter operating under a reference clock, a storage unit that stores a timer timeout time corresponding to a time measurement request when receiving the time measurement request from a CPU, and a comparator 104 that generates an interruption signal to the CPU 120 when the time corresponding to the output value of the counter is coincident with the timer timeout time stored in the storage unit. The storage unit stores a plurality of sets of timer timeout time corresponding to a plurality of time measurement requests, and a stored timer timeout time which is closest to the time corresponding to the output value of the counter is set to the timer timeout time to be compared by the comparator.

Abstract: An exemplary power supply system and method for a motherboard includes a power circuit providing power for a south bridge, and a controller having first and second transistors. An input terminal of the power circuit is connected to a power supply. An output terminal of the power circuit is connected to a reset pin of the south bridge. A first terminal of the first transistor is configured for receiving a control signal from the south bridge. A second terminal of the first transistor is connected to a first terminal of the second transistor. A second terminal of the second transistor is connected to the reset pin of the south bridge. Each of the first and second transistors has a third terminal grounded.

Abstract: A semiconductor manufacturing apparatus includes a first program on a controller and a second program on an interface board between the controller and controlled devices. Both of the programs update their own counters and exchange their counter values with each other, serving as bi-directional software watchdog timers (WDT). If a counter value of the first program on the controller sent to the second program on the interface board is determined to be abnormal by the second program, the second program on the interface board sends commands to the controlled devices to terminate output so that the apparatus is navigated to a safe mode. The first program similarly monitors the counter values of the second program for anomalies. This bi-directional software WDT can be implemented as add-on to software programs that already exist in the controller and the interface board, therefore, this implementation does not incur extra cost of hardware of the apparatus.

Abstract: Automatic resetting of a group of multiple processors in an electronic device wherein the processors are arranged in either a cascade chain or master-slave configuration. Upon the receipt of an originating reset signal by any one of the multiple processors the remaining processors are reset upon receipt of a forced reset signal generated by one of the processors in the group. The system states prior to the originating reset of each processor is refreshed to ensure compatible synchronization of system states and thus proper communication among the processors.

Abstract: A mobile telephone accesses an application server and application software is launched in the server. The application software is run on the application server based upon instructions from the mobile telephone and the result is displayed on the mobile telephone. If the mobile telephone and application server are disconnected and a fixed period of time elapses, the application software that has been launched in the application server is terminated. Since the application server can be allocated to software launched by mobile telephones other than the above-mentioned mobile telephone, the application server can be utilized more efficiently.

Abstract: A method begins by a processing module dispersed storage error encoding data to produce a set of encoded data slices and sending a set of write request messages to a set of dispersed storage (DS) units, wherein each of the set of write request messages includes an encoded data slice of the set of encoded data slices. The method continues with the processing module determining whether a pillar width number of favorable write response messages has been received within a write acknowledgement (ACK) time period. The method continues with the processing module executing a retry write process to at least one DS unit of the set of DS units from which a favorable write response message was not received during the write ACK time period when the pillar width number of favorable write response messages has not been received within the write ACK time period.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time.

Abstract: Provided are a communication system and a method of restoring the communication system. The communication system includes a master device for transmitting a reference clock through a clock line, transmitting and receiving data through a data line, and requesting and receiving input data and error detection data, and a slave device for detecting human touch input data, transmitting and receiving the data in synchronization with the reference clock or generating and transmitting the input data, and transmitting the error detection data in response to the request for error detection data. Here, the master device compares stored error detection data with the received error detection data and initializes the slave device when the stored error detection data is not the same as the received error detection data.

Abstract: A method of identifying a valid version of a data value and voting on separate instances of the data value is described. A processor receives an instance of the data value generated by one processor and a transmitted version of that generated instance transmitted by another processor and compares the received values to validate them. The processor further determines an agreed version of the data value from a comparison of the validated instances. As a result a simple and robust voting system is provided.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.