Replacement Of Failed Memory Device Patents (Class 714/6.32)
  • Patent number: 11966608
    Abstract: A memory controller with improved data reliability and a memory system including the same are provided, and an operating method of the memory controller includes, based on deterioration information indicating a location of a deterioration region in the plurality of blocks, with respect to data stored in a first block, copying user data of a RAID to a normal region other than the deterioration region of a second block; copying parity data of the RAID among the data stored in the first block to the deterioration region of the second block; and updating mapping information between data constituting one RAID and transmitting the mapping information to the memory device. The deterioration information includes information regarding one or more word lines at specific locations included in the deterioration region in the plurality of blocks.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dohyeon Park, Dongeun Shin, Wansoo Choi
  • Patent number: 11966307
    Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Sohan Shetty, Akhil Kaushik
  • Patent number: 11954062
    Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.
    Type: Grant
    Filed: March 14, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Niranjan Cooray, Subramaniam Maiyuran, Altug Koker, Prasoonkumar Surti, Varghese George, Valentin Andrei, Abhishek Appu, Guadalupe Garcia, Pattabhiraman K, Sungye Kim, Sanjay Kumar, Pratik Marolia, Elmoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, William Sadler, Lakshminarayanan Striramassarma
  • Patent number: 11947422
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: April 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kenichiro Yoshii, Shinichi Kanno
  • Patent number: 11928101
    Abstract: Methods and systems are provided for migrating data between systems without downtime. User requests may be handled adaptively during migration of data records from a first record system to a second record system, to maintain access to the data during the migration. The handling may include receiving a user request; determining at least one data record associated with the received user request; determining if a copy of the data record in the first record system is still active; and if the copy of the data record in the first record system is still active, forwarding the user request to the first record system. The user request may be forwarded to the second record system if the copy of the data record in the first record system is not active, and a retry mechanism may be used if the user request is not handled by the second record system.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 12, 2024
    Assignee: TRANSFORM SR BRANDS LLC
    Inventors: Espen Zachrisen, Tariq Afeef, Ganesh Venkatachalam, Vinayak Subray Hegde
  • Patent number: 11907070
    Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Eric Busta, Michael L. Golden, Sean M. O′Mullan, James Wingfield, Keith A. Kasprak, Russell Schreiber, Michael Estlick
  • Patent number: 11892971
    Abstract: A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 6, 2024
    Assignee: International Business Machines Corporation
    Inventors: John C. Elliott, Gary W. Batchelor, Enrique Q. Garcia, Ronald D. Martens, Todd C. Sorenson
  • Patent number: 11874760
    Abstract: A method for managing a performance for at least one use case in a software application. The method includes: executing, for a first instance, a plurality of statements pertaining to a given use case on a target database, the plurality of statements being a part of the software application; collecting first performance metrics pertaining to the first instance of execution of the given use case; executing, for a second instance, the plurality of statements on the target database; collecting second performance metrics pertaining to the second instance of execution of the given use case; comparing the first performance metrics and the second performance metrics to determine difference therebetween; and executing at least one alarm action when the difference is greater than a predefined threshold.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 16, 2024
    Assignee: Lermik Oy
    Inventor: Mikko Larkela
  • Patent number: 11836353
    Abstract: Techniques reconstruct a storage system. A first extent access load and a second extent access load of a first malfunctioning extent and a second malfunctioning extent in a malfunctioning storage device in the storage system are acquired, respectively. The first malfunctioning extent is selected as a source extent in response to determining that the first extent access load is lower than the second extent access load. Among multiple idle extents in the storage system, a set of destination extents that can be used as a reconstruction destination of the source extent are generated. A destination extent is selected from the set of destination extents as the reconstruction destination of the source extent. It is possible to preferentially select a reconstruction destination for a malfunctioning extent with a low access load, thereby increasing the reconstruction speed of the storage system.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 5, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Huijuan Fan, Chi Chen
  • Patent number: 11829269
    Abstract: One or more aspects of the present disclosure relate to recovering at least one failed disk. In embodiments, determining a storage reserve capacity allocated for recovering at least one storage device of a storage array is determined. Zero or more storage portions from each storage device of at least one storage cluster for disk recovery are adaptively assigned based on the storage reserve capacity. The failing and/or failed disk using the assigned storage portions is recovered in response to detecting a failing and/or failed disk.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Kuolin Hua, Kunxiu Gao
  • Patent number: 11803444
    Abstract: Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: October 31, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Joseph Harold Steinmetz, William Richard Akin
  • Patent number: 11797689
    Abstract: Systems and methods for enabling reliable transactions of data communications are provided. A processing device according to one embodiment includes a management interface and a security module. The management interface is configured to initialize a transaction having a plurality of transaction elements. The transaction is a unit of work including a set of one or more logically related data elements or functions for accomplishing a single task. The management interface is further configured to determine at least one expected value for at least one transaction element and to compare at least one actual value with the at least one expected value to obtain a comparison element. The security module is configured to execute security processes based on the comparison element.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 24, 2023
    Assignee: CLOUD BROKER IP INNOVATION, LLC
    Inventor: Ariel Silverstone
  • Patent number: 11789815
    Abstract: A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 17, 2023
    Inventor: Ho Youn Kim
  • Patent number: 11783884
    Abstract: A memory system includes: a memory controller suitable for: generating a first target address by sampling an active address according to an active command, providing the active address together with the active command, and providing a first target refresh command together with the first target address; and a memory device suitable for: generating a second target address by sampling the active address according to the active command, performing a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and performing the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11785087
    Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: October 10, 2023
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Daniel Marcovitch, Richard Graham
  • Patent number: 11782630
    Abstract: A method and a computer system for asymmetric replication of data are provided. Storage of a set of data is organized as a first copy and as a second copy in non-volatile storage. The second copy is reliable and stored so as to be readable at a speed slower than for the first copy. A read instruction regarding the set of data is received and performed preferentially via the first copy such that the asymmetric replication achieves enhanced performance speed. A request to execute a write operation is received. The write operation is executed to the first copy and to the second copy. In response to determining that the write operation to the first copy was unsuccessful, a label for the first copy is set as stale.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Frank Schmuck, Owen T. Anderson, Deepavali M. Bhagwat, Enci Zhong, Felipe Knop, John Lewars, Hai Zhong Zhou, D Scott Guthridge
  • Patent number: 11770448
    Abstract: A method begins by a computing device of a dispersed storage network (DSN) selectively bringing online and taking offline storage units of a set of storage units of the DSN. When bringing a first storage unit of the set of storage units online in accordance with the selectively bringing online and taking offline storage units, the method continues with the computing device determining a rebuilding approach of the first storage unit. The method continues with the computing device bringing the first storage unit online in accordance with the rebuilding approach.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 26, 2023
    Assignee: PURE STORAGE, INC.
    Inventor: Andrew G. Peake
  • Patent number: 11741048
    Abstract: Embodiments presented herein disclose techniques for capturing a snapshot of a file system object (e.g., a file or a directory) that is associated with a write journal having outstanding data. A bridge process in a storage server receives a request to capture a snapshot of a file system object. The snapshot is a backup of a state of the file system object in a given point in time. Upon determining that the file system object has one or more outstanding updates recorded in a write journal, the bridge process generates a copy of the write journal. The bridge process captures the snapshot of the file system object. The bridge process also associates the copy of the write journal with the snapshot of the file system object.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: August 29, 2023
    Assignee: Cohesity, Inc.
    Inventor: Apurv Gupta
  • Patent number: 11740973
    Abstract: An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: August 29, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Matthew B. Smittle, Jama Ismail Barreh, Robert T. Golla
  • Patent number: 11704193
    Abstract: A system-on-chip (SoC) can include a processor, a network controller configured to provide a network interface, and a memory controller configured to perform memory scrubbing. A memory patrol driver executing on the processor can initiate direct memory access (DMA) transfers to read successive portions of the memory by configuring corresponding DMA descriptors at a certain time interval. The network controller can perform each DMA transfer to read a corresponding portion of the memory, which can cause the memory controller to scrub the corresponding portion of the memory. The scrubbed data is sent to the network controller, which is discarded by the network controller.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: July 18, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Talel Shenhar, Ronen Krupnik, Barak Wasserstrom
  • Patent number: 11704206
    Abstract: A host is configured to communicate with a storage controller over a first storage area network. A request is transmitted from the host to the storage controller to provide read diagnostic parameters of a second storage area network that is used to mirror data controlled by the storage controller to another storage controller. The host receives the read diagnostic parameters of the second storage area network from the storage controller.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: July 18, 2023
    Assignee: INTERATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dale F. Riedy, Scott B. Compton, Susan K. Candelaria, Roger G. Hathorn, Harry M. Yudenfriend
  • Patent number: 11698843
    Abstract: Described herein is a method, system, and non-transitory computer readable medium for helping customers in accessing data through an application from a replica database, detecting whether the replica database, zone of availability of the replica database, or geographical region encompassing the zone of availability is experiencing an outage or other failure, and re-routing traffic to a backup replica database accordingly. To assess the status of the database, metrics are pushed in a secure manner from a private subnet to a public-facing monitoring agent, achieving a clear segregation of private subnet and public facing components. Further, circuit-breaker logic is included for preventing failure during updating DNS addresses during the re-routing process.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: July 11, 2023
    Assignee: Capital One Services, LLC
    Inventors: Kasi Reddy Sangala, Shah Sidi, Sampath Kumar Kasilingam, Paul Ly
  • Patent number: 11693734
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: July 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Kenichiro Yoshii, Shinichi Kanno
  • Patent number: 11682429
    Abstract: The technology disclosed herein pertains to a system and method for managing write failures in a disc drive. Implementations disclosed herein provide a method including monitoring write fault events per sector for a storage device, in response to a write fault event, updating a write fault repeat count table, wherein the repeat count table tracks a number of write fault repeat counts per sector, comparing a write fault repeat count for a sector to a predetermined threshold write fault repeat count, and in response to determining that the write fault repeat count for a sector is above the predetermined threshold write fault repeat count, performing a write-reassign operation.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: June 20, 2023
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Qiang Bi, Jian Qiang, WenXiang Xie
  • Patent number: 11656935
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: May 23, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanguhn Cha, Hoyoung Song, Myungkyu Lee, Sunghye Cho
  • Patent number: 11650794
    Abstract: An electronic control apparatus includes a first arithmetic processor and a second arithmetic processor that is communicably connected to the first arithmetic processor. The second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state after outputting a request signal that requests a program rewriting to the first arithmetic processor, and (ii) release the rewriting wait state and shift to a program rewriting process after a predetermined wait time that allows the first arithmetic processor to shift to the program rewriting process elapses after outputting the request signal.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: May 16, 2023
    Assignee: DENSO TEN Limited
    Inventors: Dongliang Fan, Hironori Yohata, Shigeto Umeyama
  • Patent number: 11630726
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may completely scan each of one or more target memory blocks among the plurality of memory blocks, once in each scan period to detect an error in data stored in the corresponding target memory block and may block an attempted second scan of each target memory block in a scan period in which the corresponding target memory block has already been scanned until the scan period is completed.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: April 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Tae Ha Kim, Jee Yul Kim, Hyeong Ju Na, Kwan Su Lee
  • Patent number: 11596117
    Abstract: A system (100) for controlling garden equipment by operating a garden equipment control device (110), the system (100) comprising: a first module (120) configured to pair with the garden equipment control device (110) over a first network (N1), where the first module (120) is configured to control the garden equipment control device (110) when paired therewith; a second module (200) configured to wirelessly communicate with the garden equipment control device (110) over a second network (N2), wherein the second module (200) is connected to the garden equipment control device (110) through a gateway (210); and a controller associated with the garden equipment control device (110), wherein the controller is configured to check whether the garden equipment control device (110) is paired with the gateway (210); characterized in that: wherein when the controller determines that the garden equipment control device (110) is paired with the gateway (210): the second module (200) is enabled to control the garden equip
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: March 7, 2023
    Assignee: HUSQVARNA AB
    Inventors: Dennis Koehler, Martin Lienhard
  • Patent number: 11600358
    Abstract: Managing a temperature of a memory element of an information handling system, the method comprising: identifying a lower temperature boundary of the memory element; determining an initial temperature of the memory element; determining whether the initial temperature is less than the lower temperature boundary; in response to determining that the initial temperature is less than the lower temperature boundary: performing a series of repeated burst refresh operations at the memory element; after performing the series of repeated burst refreshes operations, determining an updated temperature of memory element; determining whether the updated temperature is less than the lower temperature boundary; and in response to determining that the updated temperature is greater than the lower temperature boundary, performing a normal boot of the memory element.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: March 7, 2023
    Assignee: Dell Products L.P.
    Inventors: Jordan Chin, Isaac Qin Wang
  • Patent number: 11588690
    Abstract: A network device includes one or more processors and a memory storing firmware that when executed by the one or more processors causes the network device to perform operations including executing the firmware according to a configuration file, wherein the executing includes receiving one or more commands updating the configuration file to become a modified configuration file; and executing the firmware according to the modified configuration file. Wherein executing the firmware according to the modified configuration file includes: extracting a mode from the modified configuration file, the mode indicating a condition, a set of parameters, and a rule mapping the condition to an action; evaluating the condition based on one or more parameter values associated with the set of parameters; and in response to determining that the condition has been met, performing the action, wherein performing the action modifies how a resource is distributed at a location.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 21, 2023
    Assignee: ITRON, INC.
    Inventors: Ryan Matthew Wilson, Eric Donald White, Kevin Richard Crouse
  • Patent number: 11579975
    Abstract: Techniques manage a redundant array of independent disks. In such a technique, a response time of a first storage device in the RAID is compared to a first threshold. In response to the response time of the first storage device exceeding the first threshold, the first storage device is configured as a pseudo-degraded storage device, such that the pseudo-degraded storage device is responsive to write requests only.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 14, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jianbin Kang, Jian Gao, Geng Han
  • Patent number: 11550768
    Abstract: Systems, methods, and computer-readable media are disclosed for an improved database. The systems, methods, and computer-readable media described herein may enhance the response time of databases and improve user experiences. In an example method described herein, a database monitoring system may receive instructions to perform one or more data monitoring operations comprising counting an occurrence of a first value within at least a portion of items stored in a database. The method may include determining a length of a first window of time and fetching, from a first location of a data store of the database, data indicative of a total count of the occurrence of the first value at a time associated with the beginning of the first window of time. In turn, the monitoring system may store data representing the first count in the first memory.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: January 10, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Vineeth Chandran Poovathikkal, Sangeeth Divakaran, David John Edwards, Jr., Jebaraj Moses, Sumit Kumar Sultania
  • Patent number: 11527302
    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: December 13, 2022
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema
  • Patent number: 11513898
    Abstract: A distributed storage system includes a plurality of nodes comprising a first node, wherein a total number of nodes in the distributed storage system is represented by n, wherein a file stored in the distributed storage system is recovered from a subset of a number of nodes represented by k upon a file failure on a node in the distributed storage system, and wherein a failed node in the plurality of nodes is recovered from a number of helper nodes of the plurality of nodes represented by d. Upon detecting a failure in the first node, each helper node of the number of helper nodes is configured to determine a repair-encoder matrix, multiply a content matrix by the repair-encoder matrix to obtain a repair matrix, extract each linearly independent column of the repair matrix, and send the linearly independent columns of the repair matrix to the first node.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 29, 2022
    Assignee: Regents of the University of Minnesota
    Inventors: Mehran Elyasi, Soheil Mohajer
  • Patent number: 11513896
    Abstract: Techniques manage data of a Redundant Array of Independent Disks (RAID). Such techniques involve: obtaining a first parity of checksum pair, which is determined based on a first checksum when user data of data disks in the RAID are predetermined values; determining, based on current checksums of the data disks in the RAID, a second parity of checksum pair of the RAID, the first parity of checksum pair and the second parity of checksum pair respectively comprising a row parity of checksum and a diagonal parity of checksum; and determining, based on the first parity of checksum pair and the second parity of checksum pair, a third parity of checksum pair for updating parity data of parity disks of the RAID.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jianbin Kang, Jibing Dong, Hongpo Gao
  • Patent number: 11494260
    Abstract: A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 8, 2022
    Assignee: Etron Technology, Inc.
    Inventors: Ho-Yin Chen, Ting-Feng Chang, Chun-Chia Chen
  • Patent number: 11481275
    Abstract: Techniques involve: determining, according to a determination that a performance level of a target storage unit is lower than a threshold level, whether idle disk slices that can be used for reconstructing malfunctioning disk slices in the target storage unit exist in a slice pool; determining a priority of the target storage unit according to a determination that the idle disk slices do not exist; and selecting replacing disk slices for reconstructing the malfunctioning disk slices from available storage units based at least in part on the priority, wherein the available storage units have performance levels not lower than the threshold level. In this way, data loss due to the off-line of storage units is prevented; and meanwhile, the performance of the entire storage system can be globally stabilized.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Baote Zhuo, Chun Ma, Hongpo Gao, Jibing Dong, Jianbin Kang, Jian Gao
  • Patent number: 11474900
    Abstract: Method and system are provided for dynamic rebuild capability in redundant array of independent disks (RAID) arrays using compressing drives. The method includes providing an array including a physical rebuild area for the multiple drives of the array and dynamically adjusting a number of allocated rebuild zones available within the rebuild area, wherein each allocated rebuild zone has capacity to store a drive rebuild based on a current physical usage of the multiple drives of the array.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Michael O'Rourke, Gemma Izen, Mark Keith Elliott, Daniel Paul Dent, Dominic Tomkins, Alastair Cooper
  • Patent number: 11463542
    Abstract: A method of replacing an original server in a network by a new server is disclosed. Each of the original server and the new server includes at least a baseboard management controller (BMC). The BMC can generate a set of data including at least one configuration data relating to a hardware of the original server. Further, the BMC of the original server can configure at least one hardware of the original server according to the set of data, the new server, and configure at least one hardware of the new server according to the set of data.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 4, 2022
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Li Jun Gu, Shao Hua Li, Xiao Le Shang, Zhao Li Wang
  • Patent number: 11463520
    Abstract: Examples described herein relate to systems and methods for storing content items. The methods may be implemented by a computer comprising a processor, primary storage device, secondary storage, device and network interface. The primary storage device may receive, via the network interface, a plurality of content items responsive to respective requests from clients. The plurality of content items may be distributed, via the network interface, from the primary storage device to clients responsive to the respective requests from the clients. The processor may generate a dynamic priority list for the content items based on the respective requests from the clients over time, and may write, based on the dynamic priority list, only a subset of the content items to the secondary storage device.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 4, 2022
    Assignee: Level 3 Communications, LLC
    Inventor: William Crowder
  • Patent number: 11455218
    Abstract: A main memory includes unit memory regions, a redundancy memory region for replacing one or more of the unit memory regions, an address wrapper for generating an address increase/decrease control signal in first and second address wrapping modes, a column decoder for sequentially selecting memory cells in a faulty memory region where a fault has occurred, among the unit memory regions in the first address wrapping mode, and sequentially selecting redundancy memory cells in the redundancy memory region in the second address wrapping mode, based on a column address and the address increase/decrease control signal, and a data input/output circuit for outputting data read from the faulty memory region as backup data to a temporary memory in the first address wrapping mode, and outputting the backup data as restoration data to the redundancy memory region in the second address wrapping mode.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun-Ju Yoon
  • Patent number: 11455259
    Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module that receive, using dedicated processing circuitry implemented in a memory module, a first data object and a second data object. The memory module performs pre-processing of the first data object and post-processing of the second data object.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 11449432
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 20, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Naveen Bhoria, Timothy David Anderson, Pete Michael Hippleheuser
  • Patent number: 11442826
    Abstract: A method for reducing incidents of data loss in redundant arrays of independent disks (RAIDs) having the same RAID level is disclosed. In one embodiment, such a method identifies, in a data storage environment, a set of RAIDs having a common RAID level. The method also identifies, in the set of RAIDs, higher risk storage drives having a failure risk above a threshold and lower risk storage drives having a failure risk below the threshold. The method swaps, within the RAIDs, higher risk storage drives with lower risk storage drives to more evenly distribute higher risk storage drives across the RAIDs. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 15, 2019
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Brian A. Rinaldi
  • Patent number: 11429301
    Abstract: Methods, systems, and computer programs encoded on computer storage medium, performing, at first time, a calibration and configuration of a data contextual migration model, including: identifying contextual data associated with contextual inputs to a IHS, the contextual data including user contextual data, environmental context data, and system telemetry contextual data; training, based on the contextual data, the data contextual migration model, including: tagging, for each data block of a plurality of data blocks, the data block with identifiers indicating a store location of the data block; storing, based on the identifier associated with each data block, the data block at a local data store of the information handling system, at a remote data store of a remote server computing system, or both; generating a configuration policy including configuration rules, the configuration rules for prioritizing pre-loading of a subset of the data blocks to be provided at the information handling system.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 30, 2022
    Assignee: Dell Products L.P.
    Inventors: Lee B. Zaretsky, Michael S. Gatson
  • Patent number: 11416236
    Abstract: Embodiments of the present disclosure include systems and methods for efficient over-the-air updating of firmware having compressed and uncompressed segments. The method includes receiving a first update to the firmware via a radio, wherein the first update includes a first uncompressed segment and a first compressed segment, receiving a second update to the firmware, wherein the second update corresponds to the first compressed segment, compressing the second update to generate a compressed second update, applying the first update to the firmware, and applying the compressed second update to the firmware to generate an updated firmware.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 16, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Nieyan Geng, Gurvinder Singh Chhabra, Chenyang Liu, Chuguang He
  • Patent number: 11403224
    Abstract: A method and system for managing a buffer device in a storage system. The method comprising determining a first priority for a first queue included in the buffer device, the first queue comprising at least one data page associated with a first storage device in the storage system; in at least one round, in response to the first priority not satisfying a first predetermined condition, updating the first priority according to a first updating rule, the first updating rule making the updated first priority much closer to the first predetermined condition than the first priority; and in response to the first priority satisfying the first predetermined condition, flushing data in a data page in the first queue to the first storage device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 2, 2022
    Assignee: EMC IP Holding Company, LLC
    Inventors: Xinlei Xu, Jian Gao, Yousheng Liu, Changyu Feng, Geng Han
  • Patent number: 11397647
    Abstract: Embodiments of the present disclosure provide a hot backup system, a hot backup method, and a computer device. The hot backup system includes a centralized management module, a master server, a slave server and a delay server. The master server is configured to receive a write instruction sent by the centralized management module, and write first data to a database of the master server based on the write instruction. The slave server is configured to perform data synchronization with the master server in real time, receive a read instruction sent by the centralized management module, and send second data read based on the read instruction to the centralized management module to cause the centralized management module to send the second data to the service server.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: July 26, 2022
    Assignee: Apollo Intelligent Driving Technology (Beijing) Co., Ltd.
    Inventors: Bing Xiang, Xiaoliang Cong
  • Patent number: 11385977
    Abstract: In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: July 12, 2022
    Assignee: HITACHI, LTD.
    Inventors: Teruaki Sakata, Teppei Hirotsu
  • Patent number: 11379324
    Abstract: Undo logging for persistent memory transactions may permit concurrent transactions to write to the same persistent object. After an undo log record has been written, a single persist barrier may be issued. The tail pointer of the undo log may be updated after the persist barrier, and without another persist barrier, so the tail update may be persisted when the next log record is written and persisted. Undo logging for persistent memory transactions may rely on inferring the tail of an undo log after a failure rather than relying on a guaranteed correct tail pointer based on persisting the tail after every append. Additionally, transaction version numbers and checksum information may be stored to the undo log enabling failure recovery.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 5, 2022
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Margo I. Seltzer, Steve Byan