Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

Abstract: Aspects of the disclosure are directed to a low-latency, low-overhead fault tolerant remote memory framework, which packs similar-size in-memory objects into individual page-aligned spans and applies erasure coding on these spans. The framework fully utilizes efficient one-sided remote memory accesses (RMAs) to swap spans in and out using minimal network input/outputs (I/Os), with compaction techniques that reduce remote memory fragmentation. The framework can achieve lower tail latency and higher application performance compared to other fault tolerance solutions, at the cost of potentially more memory usage.

Abstract: A method for authorizing I/O (input/output) commands in a storage cluster is provided. The method includes generating a token responsive to an I/O command, wherein the token is specific to assignment of a storage node of the storage cluster. The method includes verifying the I/O command using the token, wherein the token includes a signature confirming validity of the token and wherein the token is revocable.

Abstract: A system includes a first processing device and a second processing device, each of which is coupled to a NIC implemented with an RDMA interface. The NICs are capable of rendezvous flows of RDMA write exchange. In an example where the first NIC is at the sender side and the second NIC is at the receiver side, a rendezvous flow is initiated by an execution of a RDMA write operation by the second NIC. The second NIC provides at least an address of a buffer in the second processing device to the first NIC through the RDMA write operation. Then the first NIC initiates a RDMA write operation to send data in a buffer in the first processing device to the second NIC. The second NIC may acknowledge receipt of the data with the second NIC. The second NIC can update a CI of the WQE based on the acknowledgement.

Abstract: Disclosed herein is a server management apparatus, comprising: a server information acquisition unit configured to acquire configuration information and identifier information of a plurality of servers that constitute a network; a script generation unit configured to generate a script for booting each server for each of the plurality of servers based on the configuration information and the identifier information of the plurality of servers acquired; a remote disk setting unit configured to write the script generated by the script generation unit to a remote disk to be mounted on each of the plurality of servers to set the remote disk; and a command issuance unit configured to issue, to each of the plurality of servers via the network, a command to mount the remote disk set by the remote disk setting unit on a corresponding server.

Abstract: Provided are a method and system for balancing and optimizing a primary placement group, and a device and a storage medium. The method includes: determining a theoretical average value; determining a weight corresponding to each object-based storage device based on an actual capacity occupied by the object-based storage device and the theoretical average value; determining the number of expected balanced primary placement groups based on the total number of current primary placement groups and the weight corresponding to the object-based storage device; obtaining a corresponding base value based on an address of each placement group and an address of the object-based storage device, and determining the placement group as a primary placement group in a case where the base value is less than a preset value; and repeating a previous operation until the number of the determined primary placement groups reaches the number of the expected balanced primary placement groups.

Abstract: A server system including a plurality of servers achieves redundancy on a per process basis. A first server and a second server execute a plurality of processes in parallel. Processes (B1-1, B2-1, and Br-1) in the first server are active processes, and processes (B1-2, B2-2, and Br-2) in the second server are standby processes. The active process periodically transmits an operation notification notifying normal operation, to the standby process. When no longer receiving an operation notification from the active process, the standby process switches an operation mode of the standby process from a standby mode to an active mode and starts provision of service of the process. The process switching is performed on a per process basis instead of on a per server basis.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Abstract: A method of tracking flash memory in a storage system is provided. The method includes initializing a bad blocks threshold value and marking one or more planes or logical unit numbers (LUNs) of flash memory as bad, responsive to determining that bad blocks in the one or more planes or LUNs meet the bad blocks threshold value. The method includes adjusting the bad blocks threshold value, responsive to exceeding a threshold number or rate of retiring planes or LUNs of flash memory, and repeating the marking and the adjusting, with the bad blocks threshold value capped at a maximum threshold value.

Abstract: In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)th word line and ith RAID parity data to obtain (i+1)th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, the (i+1)th RAID parity data overwriting the ith RAID parity data, i being a positive integer greater than or equal to 1.

Abstract: Systems and methods for performing data protection operations in a containerized application. A sidecar application is associated with or attached to a main application. The sidecar application has access to the resources of the main application. Backup requests are handled by the sidecar so that the application, which may be stateful, can be placed in a consistent state prior to performing the backup operation. The backup operation is then performed on the consistent application or on the data that is quiesced.

Abstract: Examples of implementing a communication session within a cluster computing environment are described. In an example, a communication session, initially being established by a first application server instance is continued through a second application server instance. Thereafter, a mid-session request received from a communication network may be directed to the second application server instance, wherein the mid-session request pertains to the communication session.

Abstract: In one embodiment, a method for operating a system for management of implantable medical devices (IMDs), comprises: conducting communications sessions with a plurality of clinician programmer devices, wherein some of the communication sessions occur while the plurality of clinician programmer devices are engaged in respective programming sessions with IMDs; conducting communications sessions with a plurality of patient controller devices, wherein he communication sessions with the patient controller devices include communication of data pertaining to offline programming of IMDs; reconciling programming session data received from the plurality of clinician programmer devices with programming session data received from patient controller devices to identify instances of unauthorized IMD programming; and distributing revocation data to patient controller devices to be downloaded to corresponding IMDs, wherein the revocation data identifies cryptographic keys that are no longer trusted.

Abstract: The disclosed technology enables quicker initialization of a new master node for a cluster when a previous master node fails by tracking node state in the cluster prior to being designated the new master node. In a particular example, a method includes, in a first node, designated as a current master node for the cluster, managing the cluster based on states of the nodes determined by the first node. While the first node is designated the master node, the method includes each of the nodes collecting, and storing locally, the states of the nodes. In response to a failure of the first node, the method includes selecting a second node of the nodes a new master node. Upon being designated the new master node, the method includes the second node managing the cluster of nodes based on the states of the nodes that the second node collected and stored locally.

Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

Abstract: Disclosed is a storage system that performs a drive data layout change while maintaining I/O functionality. The storage system creates a redundancy group for forming a redundant configuration of data to be stored in a storage drive, and stores data of the redundancy group in a plurality of the storage drives. A processor in a storage node discards data stored in a unit storage area, recovers the discarded data according to a changed data format, and re-stores the recovered data in the storage drive. The processor in the storage node performs an I/O process on the data to be discarded during a data format change, by achieving recovery based on the data of the redundancy group that is stored in an area other than the unit storage area where the data format is to be changed.

Abstract: An illustrative method includes determining, by a data protection system, that a dataset stored by a first storage system is possibly being targeted by a security threat while a data synchronization setting for the first storage system is enabled such that the dataset stored by the first storage system is synchronously replicated to a second storage system; and disabling, by the data protection system based on the determining that the dataset stored by the first storage system is possibly being targeted by the security threat, the data synchronization setting to prevent the dataset stored by the first storage system from being synchronously replicated to the second storage system.

Abstract: Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

Abstract: A method may include transferring data between a host and a first storage device through a first storage interface, transferring data between the host and a second storage device through a second storage interface, and transferring data between the first storage device and the second storage device through a peer-to-peer channel. A storage system may include a host interface, a first storage device having a first storage interface coupled to the host interface, a second storage device having a second storage interface coupled to the host interface, and a peer-to-peer bus coupled between the first and second storage devices. A storage device may include a storage medium, a storage device controller coupled to the storage medium, a storage interface coupled to the storage device controller, and a peer-to-peer interface coupled to the storage device controller.

Abstract: A method of data clearing of a hard disk comprises search a last target logic block of a target hard disk according to a predetermined sequence. Stored data in the target logic block is read for determining whether the stored data includes disk array information. The stored data of the target logic block is cleared while the stored data includes the disk array information. By accurately clearing minimum data, a data clearing process of the target hard disk is completed. By comparing with the full disk format manner, an effective of data clearing is improved. An apparatus and a computer readable storage medium applying the method are also disclosed.

Abstract: The present disclosure provides example memory fault handling method, computer device, and computer-readable storage medium. One example method includes starting fault analysis for a memory at a first moment, where the fault analysis includes obtaining a current fault analysis result of the memory by analyzing historical fault information, the historical fault information includes fault information of the memory accumulated in a historical time period, and the historical time period is a time period before the first moment or a time period before the first moment and including the first moment. Fault recovery is started for the memory based on the current fault analysis result of the memory.

Abstract: A method may include transferring data between a host and a first storage device through a first storage interface, transferring data between the host and a second storage device through a second storage interface, and transferring data between the first storage device and the second storage device through a peer-to-peer channel. A storage system may include a host interface, a first storage device having a first storage interface coupled to the host interface, a second storage device having a second storage interface coupled to the host interface, and a peer-to-peer bus coupled between the first and second storage devices. A storage device may include a storage medium, a storage device controller coupled to the storage medium, a storage interface coupled to the storage device controller, and a peer-to-peer interface coupled to the storage device controller.

Abstract: A method for hot swapping a memory includes the following: in response to a triggering operation of a replacement key of an abnormal memory, data on the abnormal memory is copied to an idle memory when a system is powered on; and the abnormal memory is powered off and replaced with a new memory after the data is copied; and in response to the triggering operation of a power on key of the new memory, the new memory is powered on. A method for hot swapping a memory in the case where a system is not powered off is provided.

Abstract: A memory controller with improved data reliability and a memory system including the same are provided, and an operating method of the memory controller includes, based on deterioration information indicating a location of a deterioration region in the plurality of blocks, with respect to data stored in a first block, copying user data of a RAID to a normal region other than the deterioration region of a second block; copying parity data of the RAID among the data stored in the first block to the deterioration region of the second block; and updating mapping information between data constituting one RAID and transmitting the mapping information to the memory device. The deterioration information includes information regarding one or more word lines at specific locations included in the deterioration region in the plurality of blocks.

Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: Methods and systems are provided for migrating data between systems without downtime. User requests may be handled adaptively during migration of data records from a first record system to a second record system, to maintain access to the data during the migration. The handling may include receiving a user request; determining at least one data record associated with the received user request; determining if a copy of the data record in the first record system is still active; and if the copy of the data record in the first record system is still active, forwarding the user request to the first record system. The user request may be forwarded to the second record system if the copy of the data record in the first record system is not active, and a retry mechanism may be used if the user request is not handled by the second record system.

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

Abstract: A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.

Abstract: A method for managing a performance for at least one use case in a software application. The method includes: executing, for a first instance, a plurality of statements pertaining to a given use case on a target database, the plurality of statements being a part of the software application; collecting first performance metrics pertaining to the first instance of execution of the given use case; executing, for a second instance, the plurality of statements on the target database; collecting second performance metrics pertaining to the second instance of execution of the given use case; comparing the first performance metrics and the second performance metrics to determine difference therebetween; and executing at least one alarm action when the difference is greater than a predefined threshold.

Abstract: Techniques reconstruct a storage system. A first extent access load and a second extent access load of a first malfunctioning extent and a second malfunctioning extent in a malfunctioning storage device in the storage system are acquired, respectively. The first malfunctioning extent is selected as a source extent in response to determining that the first extent access load is lower than the second extent access load. Among multiple idle extents in the storage system, a set of destination extents that can be used as a reconstruction destination of the source extent are generated. A destination extent is selected from the set of destination extents as the reconstruction destination of the source extent. It is possible to preferentially select a reconstruction destination for a malfunctioning extent with a low access load, thereby increasing the reconstruction speed of the storage system.

Abstract: One or more aspects of the present disclosure relate to recovering at least one failed disk. In embodiments, determining a storage reserve capacity allocated for recovering at least one storage device of a storage array is determined. Zero or more storage portions from each storage device of at least one storage cluster for disk recovery are adaptively assigned based on the storage reserve capacity. The failing and/or failed disk using the assigned storage portions is recovered in response to detecting a failing and/or failed disk.

Abstract: Exemplary methods, apparatuses, and systems include detecting a failure of a first memory subsystem of a plurality of memory subsystems. A first recovery instruction is sent to a second memory subsystem of the plurality of memory subsystems. The first recovery instruction directs the second memory subsystem to recover a first subset of data stored by the first memory subsystem. A second recovery instruction is sent to a third memory subsystem of the plurality of memory subsystems. The second recovery instruction directs the third memory subsystem to rebuild a second subset of data stored by the first memory subsystem. The first and second subsets of data differ from one another.

Abstract: Systems and methods for enabling reliable transactions of data communications are provided. A processing device according to one embodiment includes a management interface and a security module. The management interface is configured to initialize a transaction having a plurality of transaction elements. The transaction is a unit of work including a set of one or more logically related data elements or functions for accomplishing a single task. The management interface is further configured to determine at least one expected value for at least one transaction element and to compare at least one actual value with the at least one expected value to obtain a comparison element. The security module is configured to execute security processes based on the comparison element.

Abstract: A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors.

Abstract: A method and a computer system for asymmetric replication of data are provided. Storage of a set of data is organized as a first copy and as a second copy in non-volatile storage. The second copy is reliable and stored so as to be readable at a speed slower than for the first copy. A read instruction regarding the set of data is received and performed preferentially via the first copy such that the asymmetric replication achieves enhanced performance speed. A request to execute a write operation is received. The write operation is executed to the first copy and to the second copy. In response to determining that the write operation to the first copy was unsuccessful, a label for the first copy is set as stale.

Abstract: A memory system includes: a memory controller suitable for: generating a first target address by sampling an active address according to an active command, providing the active address together with the active command, and providing a first target refresh command together with the first target address; and a memory device suitable for: generating a second target address by sampling the active address according to the active command, performing a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command, and performing the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

Abstract: A method begins by a computing device of a dispersed storage network (DSN) selectively bringing online and taking offline storage units of a set of storage units of the DSN. When bringing a first storage unit of the set of storage units online in accordance with the selectively bringing online and taking offline storage units, the method continues with the computing device determining a rebuilding approach of the first storage unit. The method continues with the computing device bringing the first storage unit online in accordance with the rebuilding approach.

Abstract: An instruction storage circuit within a processor that includes an instruction memory and a memory control circuit. The instruction memory is configured to store instructions of a program for the processor. The memory control circuit is configured to receive a particular instruction from the instruction memory, detect a data integrity error in the particular instruction, and generate and store a corrected version of the particular instruction in an error storage circuit within the instruction memory. A flush of an execution pipeline may be performed in response to the error. In response to a refetch of the particular instruction after the pipeline flush, the instruction storage circuit may be configured to cause the particular instruction to be provided from the error storage circuit to the execution pipeline to permit forward progress of the processor.

Abstract: Embodiments presented herein disclose techniques for capturing a snapshot of a file system object (e.g., a file or a directory) that is associated with a write journal having outstanding data. A bridge process in a storage server receives a request to capture a snapshot of a file system object. The snapshot is a backup of a state of the file system object in a given point in time. Upon determining that the file system object has one or more outstanding updates recorded in a write journal, the bridge process generates a copy of the write journal. The bridge process captures the snapshot of the file system object. The bridge process also associates the copy of the write journal with the snapshot of the file system object.

Abstract: A host is configured to communicate with a storage controller over a first storage area network. A request is transmitted from the host to the storage controller to provide read diagnostic parameters of a second storage area network that is used to mirror data controlled by the storage controller to another storage controller. The host receives the read diagnostic parameters of the second storage area network from the storage controller.

Abstract: A system-on-chip (SoC) can include a processor, a network controller configured to provide a network interface, and a memory controller configured to perform memory scrubbing. A memory patrol driver executing on the processor can initiate direct memory access (DMA) transfers to read successive portions of the memory by configuring corresponding DMA descriptors at a certain time interval. The network controller can perform each DMA transfer to read a corresponding portion of the memory, which can cause the memory controller to scrub the corresponding portion of the memory. The scrubbed data is sent to the network controller, which is discarded by the network controller.

Abstract: Described herein is a method, system, and non-transitory computer readable medium for helping customers in accessing data through an application from a replica database, detecting whether the replica database, zone of availability of the replica database, or geographical region encompassing the zone of availability is experiencing an outage or other failure, and re-routing traffic to a backup replica database accordingly. To assess the status of the database, metrics are pushed in a secure manner from a private subnet to a public-facing monitoring agent, achieving a clear segregation of private subnet and public facing components. Further, circuit-breaker logic is included for preventing failure during updating DNS addresses during the re-routing process.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Abstract: The technology disclosed herein pertains to a system and method for managing write failures in a disc drive. Implementations disclosed herein provide a method including monitoring write fault events per sector for a storage device, in response to a write fault event, updating a write fault repeat count table, wherein the repeat count table tracks a number of write fault repeat counts per sector, comparing a write fault repeat count for a sector to a predetermined threshold write fault repeat count, and in response to determining that the write fault repeat count for a sector is above the predetermined threshold write fault repeat count, performing a write-reassign operation.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

Abstract: An electronic control apparatus includes a first arithmetic processor and a second arithmetic processor that is communicably connected to the first arithmetic processor. The second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state after outputting a request signal that requests a program rewriting to the first arithmetic processor, and (ii) release the rewriting wait state and shift to a program rewriting process after a predetermined wait time that allows the first arithmetic processor to shift to the program rewriting process elapses after outputting the request signal.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may completely scan each of one or more target memory blocks among the plurality of memory blocks, once in each scan period to detect an error in data stored in the corresponding target memory block and may block an attempted second scan of each target memory block in a scan period in which the corresponding target memory block has already been scanned until the scan period is completed.