Of Memory Patents (Class 714/6.1)
  • Patent number: 10915380
    Abstract: A method for coordinating management of operation risks in a distributed storage network (DSN) that includes multiple distributed computing systems including DSN memories begins with a global coordinating unit receiving messages including metadata from managing units associated with the multiple distributed computing systems. The method continues with the global coordinating unit determining, based on the metadata, that storage units in one or more of the distributed computing systems are executing or planning to execute an operation that could result in data loss or data outage. The method continues with the global coordinating unit transmitting an alert, including a command to halt the operation at the affected distributed computing systems.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick A. Tamborski, Bart R. Cilfone, Alan M. Frazier, Sanjaya Kumar
  • Patent number: 10879660
    Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 29, 2020
    Assignee: Dell Products, L.P.
    Inventors: Isaac Qin Wang, Jing Zhang
  • Patent number: 10866854
    Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 15, 2020
    Assignee: ARTERIS, INC.
    Inventor: Parimal Gaikwad
  • Patent number: 10832639
    Abstract: A method and an apparatus for generating a signature representative of the content of a region of an array of data in a data processing system, where the region of the array of data comprising plural data positions, and each data position having an associated data value or values. A data value or values for a data position of the region of the data array is/are generated. The data value or values for the data position of the region of the data array is/are written to storage that stores the region of the data array as it is being generated. A signature representative of the content of the region of the data array is generated in parallel with the data value or values for the data position of the region of the data array being written to the storage.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 10, 2020
    Assignee: ARM Limited
    Inventors: Toni Viki Brkic, Jakob Axel Fries, Reimar Gisbert Döffinger
  • Patent number: 10831613
    Abstract: Provided are a computer program product, system, and method for replicating a source data set to a target data store. A point-in-time copy of the source data set is generated having a data structure identifying the data in the source data set as of a point-in-time. A restore operation is initiated to copy the source data set represented by the point-in-time copy to a restored copy of the source data set consistent with the source data set. The source data set records are transferred from the restored copy to the target data store in the target storage.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Cadarette, Robert S. Gensler, Jr., Joseph L. Kidd, Robert D. Love, Terri A. Menendez, Austin J. Willoughby
  • Patent number: 10817369
    Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 27, 2020
    Assignee: ARM Limited
    Inventors: Reiley Jeyapaul, Balaji Venu, Xabier Iturbe, Emre Özer, Antony John Penton
  • Patent number: 10809920
    Abstract: First information about regions of storage space in a storage environment available for a volume is provided to a service provider, with the storage environment being external to the service provider. The service provider is notified that information usable to locate a storage destination of a portion of the volume is unavailable. Second information that includes the storage destination in the storage environment is obtained from the service provider. A data operation is performed at the storage destination, with the storage destination determined based at least in part from the second information.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Marc Stephen Olson, Christopher Magee Greenwood, Anthony Nicholas Liguori, James Michael Thompson, Surya Prakash Dhoolam, Marc John Brooker, Danny Wei
  • Patent number: 10769040
    Abstract: A computer implemented method for replication includes registering a first database system with a second database system and performing a failback operation on the first database system. The failback operation includes opening a snapshot that includes data known to have existed on the first database system and the second database system at a first time. Transaction log information is requested from the second database system. The transaction log information corresponds to transactions performed on the second database system beginning with the first time. The transaction log information is applied to the snapshot data on the first database system. Related apparatus, systems, techniques and articles are also described.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 8, 2020
    Assignee: SAP SE
    Inventors: Reiner Singer, Werner Thesing
  • Patent number: 10740203
    Abstract: A plurality of tracks that are to be copied to a backup volume are aggregated in a container data structure. The plurality of tracks are stored physically contiguously in a single Redundant Array of Independent Disks (RAID) stride. Mapping metadata is updated in the backup volume to indicate how logical tracks of the backup volume correspond to physical tracks stored in the RAID stride.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Theresa M. Brown, Kevin Lin, Dave Fei, Gail Spear, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 10699796
    Abstract: Examples herein disclose selecting a row of data among multiple rows of data for validation of a repair to the selected row of data. The examples here disclose validating the repair to the selected row of data.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Eric L. Pope, Lidia Warnes
  • Patent number: 10678679
    Abstract: A system, method, and computer program product are provided for automated API regression testing with a business flow sense/customer journey. In operation, a system identifies one or more environments for which to perform one or more testing activities. The system discovers an application programming interface (API) architecture associated with the one or more environments by tracing all unique combinations of business flows and/or customer journeys on production and discovering all API paths for each of the business flows. The system stores and categorizes information associated with the API architecture in at least one API dictionary, based on the machine learning. The system automatically recommends relevant API test cases associated with the API architecture for performing API testing on the one or more environments, using the information associated with the API architecture from the API dictionary as a reference.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: June 9, 2020
    Assignee: AMDOCS DEVELOPMENT LIMITED
    Inventors: Prashant Vijay Sonawale, Dror Avrilingi, Yasmin Bel Klein
  • Patent number: 10657102
    Abstract: One embodiment provides a method for re-balancing data and metadata across multiple sub-file systems of a file system. The method includes determining sub-file systems including an amount of data that exceeds a threshold. At least one cell in the sub-file systems is identified as a candidate for re-balancing. A re-balance process is performed on the at least one cell that includes performing a flush operation to flush dirty data from file system buffers, copying an inode table for an independent set of files in the at least one cell to a destination sub-file system, notifying an allocation manager for the destination sub-file system of a new storage pool to manage, and performing an un-quiesce operation on I/O operations to each element in the at least one cell.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Deepavali M. Bhagwat, Marc Eshel, Dean Hildebrand, Manoj P. Naik, Wayne A. Sawdon, Frank B. Schmuck, Renu Tewari
  • Patent number: 10645002
    Abstract: A network sensor that features a data store and a packet processing engine. In communication with the data store, the packet processing engine comprises (1) a cache management logic and (2) deduplication logic. The cache management logic is configured to analyze packets to determine whether (a) a packet under analysis include duplicated data and (b) content of the packet is targeted for storage in a same continuous logical storage area as the duplicated data. The deduplication logic, when activated by the cache management logic, is configured to generate a deduplication reference for insertion into the packet prior to storage.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 5, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ramsundar Janakiraman, Prasad Palkar, Mohan Parthasarathy, Brijesh Nambiar, Giri Gopalan, Shankar Subramaniam, Suhas Shetty, Steven Alexander
  • Patent number: 10635537
    Abstract: A method for preventing data loss in a RAID includes monitoring storage drives making up a RAID. The method individually tests a storage drive of the RAID by subjecting the storage drive to a stress workload test. This stress workload test may be designed to place additional stress on the storage drive while refraining from adding stress to other storage drives in the RAID. In the event the storage drive fails the stress workload test (e.g., the storage drive cannot adequately handle the additional workload or generates errors in response to the additional workload), the method replaces the storage drive with a spare storage drive and rebuilds the RAID. In certain embodiments, the method tests the storage drive with greater frequency as the age of the storage drive increases. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Clint A. Hardy, Karl A. Nielsen, Brian A. Rinaldi
  • Patent number: 10628364
    Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hojun Shim
  • Patent number: 10621162
    Abstract: Techniques are provided for storage tier verification checks. A determination is made that a mount operation of an aggregate of a set of volumes stored within a multi-tier storage environment has completed. A first metafile and a second metafile are maintained to track information related to the storage of objects of a volume of the aggregate within a remote object store that is a tier of the multi-tier storage environment. A distributed verification is performed between the first metafile and the second metafile to identify an inconsistency. Accordingly, the first metafile and the second metafile are reconciled to address the inconsistency so that storage information within the first metafile and the second metafile are consistent.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 14, 2020
    Assignee: NetApp Inc.
    Inventors: Kayuri Hasmukh Patel, Qinghua Zheng, Sumith Makam, Kevin Daniel Varghese, Yuvraj Ajaykumar Patel, Sateesh Kumar Pola, Sharmi Suresh Kumar Nair, Mihir Gorecha
  • Patent number: 10616144
    Abstract: A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 7, 2020
    Assignee: Cavium, LLC
    Inventor: Enrique Musoll
  • Patent number: 10614098
    Abstract: A system and method for determining consensus within a distributed database are provided. According to one aspect, a protocol is provided that reduces or eliminates heartbeat communication between nodes of a replica set. Nodes may communicate liveness information using existing database commands and metadata associated with the database commands. According to another aspect, improved systems and methods are provided for detection of node failures and election of a new primary node.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 7, 2020
    Assignee: MongoDB, Inc.
    Inventors: Eliot Horowitz, Andrew Michalski Schwerin, Siyuan Zhou, Eric Andrew Milkie
  • Patent number: 10614905
    Abstract: A system for testing memory and a method thereof are disclosed. In the system, a physical address range of at least one memory module is converted into a logical address range of the memory, and a read and write test is performed on the memory according to the logical address range of the memory, and an error message corresponding to the memory is detected during the read and write test, and a logical address contained in the error message is converted into a physical address of the memory module corresponding to the logical address, so as to improve test coverage and validity of memory test, and effectively determine the problematic memory module, thereby achieving the technical effect of preventing the test program from being closed by the operating system.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: April 7, 2020
    Assignee: INVENTEC (PUDONG) TECHNOLOGY CORPORATION
    Inventor: Yen Li
  • Patent number: 10592438
    Abstract: Technologies are disclosed herein that allow configuration of firmware by a firmware configuration device connected to a target computer. The firmware configuration device may emulate keystroke and/or mouse movement data to transmit firmware configuration data to the target computer. The target computer can also transmit status information and/or commands through keyboard status light signals.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 17, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Kai Yau, Muthu Kumar Sathiyanesan
  • Patent number: 10592329
    Abstract: A fault tolerant operating method and an electronic device using the same are provided. The method includes: performing a first procedure by a first executive file installed in the electronic device; when an error occurs to cause the first procedure to abort, sending an aborted notification to a fault tolerant module by an operating system (OS) and obtaining an aborted address information of the first procedure by the fault tolerant module; and sending the aborted address information to the OS by the fault tolerant module, such that the OS calls the first executive file to continue executing the first procedure based on the aborted address information.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 17, 2020
    Assignee: Acer Incorporated
    Inventor: Kuan-Ju Chen
  • Patent number: 10567507
    Abstract: A message processing method and apparatus on a cloud computing platform, and a message processing system on a cloud computing platform are provided. In the message processing method, after an input request message sent to an active server and a standby server is received, the input request message is sent to all active servers and standby servers. After input response messages returned by the active server and the standby server are received, one of the input response messages is sent to an external device.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 18, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Jian Zhu
  • Patent number: 10496295
    Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes includes a first plurality of storage nodes configured to communicate together as a first storage cluster and a second plurality of storage nodes configured to communicate together as a second storage cluster. Each of the first and second pluralities of storage nodes has nonvolatile solid-state memory for user data storage and each of the first and second pluralities of storage nodes is configured to distribute user data and metadata associated with the user data throughout a respective plurality of storage nodes such that a respective storage cluster maintains ability to read the user data, using erasure coding, despite a loss of one or more of the respective plurality of storage nodes.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 3, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Par Botes, John Colgrove, John Hayes
  • Patent number: 10459792
    Abstract: A method for a dispersed storage network begins by receiving one or more revisions of a data object for storage within a time frame and facilitating, for each revision of the one or more revisions, storage of the revision in the selected primary storage target including at least some encoded data slices of each set of encoded data slices of a plurality of sets of encoded data slices are stored in the selected primary storage target and, for each of the revisions, facilitating subsequent storage of remaining encoded data slices of each set of encoded data slices that were not stored in the selected primary storage target, and determining to store the remaining encoded data slices in another storage target, identifying a most recently stored revision of the data object and facilitating storage of the remaining encoded data slices of the most recently stored revision in the other storage target.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 29, 2019
    Assignee: PURE STORAGE, INC.
    Inventor: Jason K. Resch
  • Patent number: 10437675
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices comprises one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. Each one of the plurality of failure resilient address spaces is organized into a plurality of stripes. Each one or more stripes of the plurality of stripes is part of a respective one of a plurality of forward error correction (FEC) protection domains. Each of the plurality of stripes may comprise a plurality of storage blocks. Each block of a particular one of the plurality of stripes may reside on a different one of the plurality of storage devices.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 8, 2019
    Assignee: Weka.IO Ltd.
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
  • Patent number: 10382446
    Abstract: A computerized method of managing a computer remote session operation, comprising providing a server for hosting application execution; configuring a number of predefined user accounts with low security permissions on said server, where said user accounts are not tied to any specific real user; Whenever a remote user requests to start a remote session, finding an available user account not currently in use on said computer, allocating it for the remote session and marking it as unavailable for subsequent session requests; Generating a one-time password for said user account; Communicating the assigned user account identifier and temporary password to client component on the user's side, either directly or through an intermediate broker, causing the client component to connect to the server using said user account identifier and temporary password; and, upon termination of the remote session, deleting the assigned user account's data and marking it as available again.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 13, 2019
    Assignee: Cameyo Inc.
    Inventor: Eyal Dotan
  • Patent number: 10360193
    Abstract: A system and method for archiving and analyzing data are disclosed. The system receives event data associated with a process; responsive to receiving the event data, determines process data associated with the process; generates process metadata from the event data and the process data; and stores the event data, the process data, and the process metadata in a data repository organized by the process metadata. Since the process data is determined early on in the data pipeline, the system can significantly reduce the amount of computation required for generating data analytics. The system is also capable of providing analytic results computed against a massive amount of archived data in real-time or near real-time as user requests are initiated. Efficiency of process mining and process optimization is also improved due to enhanced information stored for archived processes.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 23, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sanhita Sarkar, Kannan J. Somangili, Shanker Valipireddy, Harold Woods
  • Patent number: 10360370
    Abstract: Examples include an authenticated access to manageability hardware components in a computing device. Some examples enumerate manageability hardware components connected to an operative system kernel of the computing device, the manageability hardware components comprising a bus configuration space and the bus configuration space comprising memory map registers. Some examples include encoding an address stored in the memory map registers of each of the manageability hardware components to produce encoded address to control unauthorized accesses and locks the bus configuration space of each manageability hardware component by setting a read-only attribute to the bus configuration space. Some examples reprogram, in response to a request for access of an authenticated OS component to a manageability hardware component, the memory map register of the requested manageability hardware component with an accessible address to provide the authenticated OS component with access to the manageability hardware component.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: July 23, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Suhas Shivanna, Srinivasa Ragavan Rajagopalan, Nagaraj S Salotagi
  • Patent number: 10324664
    Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 18, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirokazu So, Toshiyuki Honda, Shigekazu Kogita
  • Patent number: 10303560
    Abstract: In accordance with embodiments of the present disclosure, a method may include, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and storing the data in response to a power event associated with the write-back cache: (a) calculating a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and (b) storing the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Dell Products L.P.
    Inventors: Chandrashekar Nelogal, Anand Nunna
  • Patent number: 10289507
    Abstract: A storage server comprises a plurality of storage devices arranged in a redundant storage array and a plurality of controllers. One of the controllers determines that a storage device in the redundant storage array has failed, determines a first portion of the storage device to be recovered by a first controller and determines a second portion of the storage device to be recovered by a second controller. The first controller recovers the first portion of the storage device and the second controller recovers the second portion of the storage device.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 14, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Kiron Balkrishna Malwankar, Karagada Ramarao Kishore, Sundar Kanthadai
  • Patent number: 10289593
    Abstract: A hot swap management device includes a bus buffer, a hot swap switch, and a controller. The bus buffer is selectively coupled to a host system management bus of a server. The hot swap switch is coupled to the bus buffer and a hardware expansion device. The controller is coupled to the bus buffer and the hot swap switch. When the hot swap management device is coupled to a board system management bus of the server, the controller assigns a hardware address to the bus buffer. A computational unit of the server controls the hardware expansion device through the host system management bus according to the hardware address.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: May 14, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventor: Po-Chung Chang
  • Patent number: 10282135
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device operates based on a store data request from a requesting entity to dispersed error encode a data segment associated with a data object to generate a set of encoded data slices (EDSs). The computing device selects a write threshold number of EDSs based on a desired consistency level indicator and issues a write request to storage unit(s) (SU(s)). The computing device receives write response(s) from the SU(s) and, based on write response(s) received from the at least some of the SU(s), provides a store data response to the requesting entity.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: S. Christopher Gladwin, Jason K. Resch
  • Patent number: 10228993
    Abstract: As the file system of an operating system program might be damaged by a crash, the file system is usually used neither for the selection of data to be dumped from a memory nor for the analysis of the dumped data, and all data contained in one or several areas of the memory are dumped. In order to preserve the integrity of the file system and enable its use after the crash, the memory is divided into a primary and a secondary memory section during a memory setup, file system data are transferred from the primary memory section to the secondary memory section widely out of the control of the operating system program, and a read access of a dump program is directed to the secondary memory section in order to select file system data to be dumped after the crash using error data.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Victor Rafael Escobar Olmos, Jakob Christopher Lang, Angel Nunez Mencias, Albert Schirmer, Jochen Schweflinghaus
  • Patent number: 10223033
    Abstract: Methods for use in a dispersed storage network (DSN) to coordinate data slice arrival times. In various examples, a DSN computing device receives a store data request, the store data request including a data object. A set of storage units associated with the store data request is identified, and the data object is dispersed storage error encoded to produce a plurality of sets of encoded data slices. One or more sets of write slice requests that include one or more sets of encoded data slices are also generated for reception by storage units of the set of storage units. For each set of write slice requests, a transmission schedule is determined for each write slice request such that the set of write slice requests arrives at corresponding storage units at substantially the same time frame. Each of the write slice requests is then transmitted in accordance with the transmission schedule.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventor: Jason K. Resch
  • Patent number: 10204003
    Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 12, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Ninose, Takuji Itou, Fumio Yoshioka, Takashi Tsunehiro, Go Uehara, Shigeo Homma
  • Patent number: 10200949
    Abstract: A technique is described herein for saving power (e.g., battery power) at a receiving device (e.g., wireless device) by having a transmitting device (e.g., wireless access node) add an indicator to repeated radio blocks, where the indicator can be used by the receiving device (e.g., wireless device) to stop monitoring one or more of the repeated radio blocks.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: February 5, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Paul Schliwa-Bertling, Mårten Sundberg, John Walter Diachina
  • Patent number: 10191809
    Abstract: One embodiment provides a method comprising arranging a first data chunk into a ring structure, tagging the first data chunk by appending extra data to the first data chunk, and performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventor: Zhenxing Han
  • Patent number: 10191799
    Abstract: A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 29, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yonatan Karlik, Judah Gamliel Hahn, Ariel Navon, Alex Bazarsky, Ofer Shapira
  • Patent number: 10191816
    Abstract: A storage system according to certain embodiments includes a client-side repository (CSR). The CSR may communicate with a client at a higher data transfer rate than the rate used for communication between the client and secondary storage. During copy operations, for instance, some or all of the data being backed up or otherwise copied to secondary storage is stored in the CSR. During restore operations, copies of the data stored in the CSR is accessed from the CSR instead of from secondary storage, improving performance. Remaining data blocks not stored in the CSR can be restored from secondary storage.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 29, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Vijayan, Deepak Raghunath Attarde, Hetalkumar N. Joshi
  • Patent number: 10192015
    Abstract: Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-Su Kim, Kyoung-Hwan Lim, Cheol-Jun Bae
  • Patent number: 10175892
    Abstract: An adaptive read algorithm for accessing information stored on a nonvolatile medium. The nonvolatile medium can be organized as a plurality of storage units. A method of servicing a read request to the nonvolatile medium can include recording a history of read-retries for read requests to individual storage units of the nonvolatile medium. The method can include adapting a read algorithm for a read request to a particular storage unit based on the history of the read-retries for the read requests to the individual storage units of the nonvolatile medium.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Kevin Kim, Jingyu Kang, Wenzhou Chen, Sujan Biswas, Truong Nguyen
  • Patent number: 10169163
    Abstract: Provided are techniques for managing backup operations from a client system to a primary server and secondary server. A determination is made at the client system of whether a state of the data on the secondary server permits a backup operation in response to determining that the primary server is unavailable when a force failover parameter is not set. The client system reattempts to connect to the primary server to perform the backup operation at the primary server in response to determining that the state of the data on the secondary server does not permit the backup operation. The client system performs the backup operation at the secondary server in response to determining that the state of the secondary server permits the backup operation.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Anglin, David M. Cannon, Ken Eugene Hannigan, Kevin Patrick Hoyt, Erick Christian Kissel, Howard N. Martin, Michael Harry Segapeli
  • Patent number: 10157005
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Tony S. Baker, Theodros Yigzaw, Chris Ackles, Celeste M. Brown
  • Patent number: 10140053
    Abstract: A computer program product, system, and method for generating coded fragments comprises receiving, at a primary data protection appliance (DPA), an I/O write for a user volume; determining a distributed consistency group (DCG) associated with the user volume, the DCG having a plurality of replica copies; determining one or more secondary DPAs assigned to one or more of the replica copies; sending the I/O write from the primary DPA to each of the secondary DPAs; and applying, at each of the secondary DPAs, the I/O write to at least one of the replica copies assigned to the secondary DPA.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 27, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Lev Ayzenberg, Leehod Baruch, Valerie Lotosh
  • Patent number: 10135385
    Abstract: Systems and methods for local and master management units in a photovoltaic energy system. In one embodiment, a method implemented in a computer system includes sending a first identification code from a local management unit to a master management unit. The first identification code is associated with the first local management unit, and the local management unit controls a solar module. An authentication of the first identification code is received from the master management unit. In response to receiving the authentication, active operation of the local management unit is continued (e.g., for a set time period).
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 20, 2018
    Assignee: TIGO ENERGY, INC.
    Inventors: Daniel Eizips, Shmuel Arditi, Ron Hadar, Maxym Makhota
  • Patent number: 10127152
    Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
  • Patent number: 10108370
    Abstract: A method of reading a nonvolatile memory device including a plurality of pages coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of pages including a data region storing a data and a flag region storing a flag, includes applying a first read voltage to a selected word line to generate first sensing data and a first sensing flag; applying a second read voltage to the selected word line to generate second sensing data and a second sensing flag, generating determination data by performing a logical operation on the first and second sensing data; determining a shift voltage based on the determination data and the read flag; and applying a third read voltage, based on the shift voltage, to the selected word line to generate a read data.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Makoto Hirano
  • Patent number: 10102060
    Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 16, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Koseki, Takashi Tsunehiro, Junji Ogawa, Nagamasa Mizushima, Atsushi Kawamura
  • Patent number: 10095582
    Abstract: Methods for use in a dispersed storage network (DSN) to rebuild data. In various examples, at least one data segment of a data object is dispersed storage error encoded to produce a set of encoded data slices that includes an information dispersal algorithm (IDA) width number of encoded data slices, wherein the IDA width number is at least twice the number of storage units of a set of storage units utilized to store the data object. At least two encoded data slices are stored in each of the storage units. In response to detecting a storage error indicating an error slice, a partial threshold number of partial encoded data slices (generated by performing a partial encoding function on stored encoded data slices) are generated. The partial threshold number of partial encoded data slice responses are combined to produce a rebuilt encoded data slice corresponding to the error slice.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Trevor J. Vossberg, Jason K. Resch