Of Memory Patents (Class 714/6.1)
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Patent number: 12260114Abstract: Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.Type: GrantFiled: August 16, 2022Date of Patent: March 25, 2025Assignee: Micron Technology, Inc.Inventors: Luca Porzio, Gianluca Coppola, Ryan Laity, Christopher Joseph Bueb
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Patent number: 12248406Abstract: The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.Type: GrantFiled: December 13, 2022Date of Patent: March 11, 2025Assignee: ALIBABA (CHINA) CO., LTD.Inventors: Lide Duan, Qichen Zhang, Shijian Zhang, Yen-Kuang Chen
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Patent number: 12242349Abstract: In various embodiments, a method for page cache management is described. The method can include: identifying a storage device fault associated with a fault-resilient storage device; determining that a first region associated with the fault-resilient storage device comprises an inaccessible space and that a second region associated with the fault-resilient storage device comprises an accessible space; identifying a read command at the second storage device for the data and determine, based on the read command, first data requested by a read operation from a local memory of the second storage device; determining, based on the read command, second data requested by the read operation from the second region; retrieving the second data from the second region; and scheduling a transmission of the second data from the fault-resilient storage device to the second storage device.Type: GrantFiled: April 13, 2023Date of Patent: March 4, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Yang Seok Ki, Sungwook Ryu
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Patent number: 12229025Abstract: A data storage method includes deploying a data storage service system including two nodes on a wheeled mobile device, where the wheeled mobile device is an intelligent vehicle, an autonomous vehicle, or a connected vehicle; running a first process on a first node; running a second process on a second node, where the first node is a primary node and the second node is a secondary node; invoking, by the first node, a first database engine using the first process to write data to a first storage module on the first node when the first node receives a data write request; and enabling by the first node, in a blocking mode, the second node to invoke a second database engine using the second process to perform a same data write operation on a second storage module on the second node.Type: GrantFiled: March 27, 2023Date of Patent: February 18, 2025Assignee: SHENZHEN YINWANG INTELLIGENT TECHNOLOGIES CO., LTD.Inventor: Xiaojie Li
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Patent number: 12229030Abstract: A storage device is disclosed. A first storage media may store data. The first storage media may be of a first storage type and may be organized into at least two blocks. A second storage media may also store data. The second storage media may be of a second storage type different from the first type, and may also be organized into at least two blocks. A controller may manage reading data from and writing data to the first storage media and the second storage media. Metadata storage may store device-based log data for errors in the storage device. The drive-based log data may include a first log data for the first storage media and a second log data for the second storage media. An identification circuit may identify a suspect block in the at least two blocks in the first storage media and the second storage media, responsive to the device-based log data.Type: GrantFiled: October 11, 2022Date of Patent: February 18, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nima Elyasi, Changho Choi
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Patent number: 12204469Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.Type: GrantFiled: February 26, 2024Date of Patent: January 21, 2025Assignee: Rambus Inc.Inventors: Hongzhong Zheng, Brent Haukness
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Patent number: 12197298Abstract: A data management system can include a set of storage media configured to implement a storage space and a set of controllers. The set of controllers can be configured to write to the storage space and to implement a set of nodes. The set of controllers can include a first controller that implements a first node and includes a first persistent memory, a second controller that implements a second node and includes a second persistent memory and a third controller that implements a third node and includes a third persistent memory. The third node can be configured to write third node journal data to the first persistent memory. The first node can be configured to generate first node journal data based on a first request received from a backend, write the first node journal data to the first persistent memory, and replicate the journal data to the second persistent memory.Type: GrantFiled: March 7, 2024Date of Patent: January 14, 2025Assignee: NetApp, Inc.Inventors: Kalaivani Arumugham, Parag Sarfare, Prachi Deskmukh
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Patent number: 12189464Abstract: In a method of managing a debugging log in a storage device, an event trigger signal is generated based on an external power supply voltage and a plurality of configuration control signals. The event trigger signal is activated in response to an event of interest being issued for generating and storing the debugging log. The debugging log represents information associated with errors occurring in the storage device. The debugging log is generated based on the event trigger signal. The debugging log is stored in a nonvolatile memory. The event of interest includes at least one of a power up event a reset event, a link up event, a link down event or a power down event.Type: GrantFiled: April 1, 2022Date of Patent: January 7, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Bomi Choi, Sunghoon Chun, Seongyeon Kim, Jaeyoung Eum
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Patent number: 12174718Abstract: A storage device is disclosed. A first storage media may store data. The first storage media may be of a first storage type and may be organized into at least two blocks. A second storage media may also store data. The second storage media may be of a second storage type different from the first type, and may also be organized into at least two blocks. A controller may manage reading data from and writing data to the first storage media and the second storage media. Metadata storage may store device-based log data for errors in the storage device. The drive-based log data may include a first log data for the first storage media and a second log data for the second storage media. An identification circuit may identify a suspect block in the at least two blocks in the first storage media and the second storage media, responsive to the device-based log data.Type: GrantFiled: October 11, 2022Date of Patent: December 24, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nima Elyasi, Changho Choi
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Patent number: 12164804Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.Type: GrantFiled: December 15, 2021Date of Patent: December 10, 2024Assignee: Micron Technology, Inc.Inventors: Karl D. Schuh, Jiangang Wu, Kishore K. Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu
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Patent number: 12111725Abstract: Devices and techniques to recover data from a memory device are disclosed, including recovering data corresponding to a detected error in data stored on a memory array corresponding to a memory operation using one of a set of read offset values and loading the one of the set of read offset values used to recover data corresponding to the detected error in a temporary storage of the memory array as a custom read offset value for a subsequent memory operation. The temporary storage of the memory array can include a scratch space of the memory array separate from read retry offset registers of the memory device.Type: GrantFiled: February 17, 2023Date of Patent: October 8, 2024Assignee: Micron Technology, Inc.Inventors: Rahul Mitchell Jairaj, Mark A. Hawes, Terry M. Grunzke
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Patent number: 12093132Abstract: Techniques for accessing data involve reading data from at least one disk among a plurality of disks. Such techniques further involve detecting whether a lookup table stored on a memory is empty, where the lookup table stores information indicating data loss. Such techniques further involve comparing, in response to the lookup table not being empty, data read information associated with the read data with table items in the lookup table to determine whether there is a table item in the lookup table that matches the data read information. Such techniques further involve sending, in response to determining that there is a table item that matches the data read information, the information indicating data loss. Such a technique improve the efficiency of data access, reduces the complexity of the system and the power consumption of the system, and improves the performance of the system.Type: GrantFiled: November 10, 2022Date of Patent: September 17, 2024Assignee: Dell Products L.P.Inventors: Geng Han, Jianbin Kang, Jian Gao
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Patent number: 12063713Abstract: A system of mobile device operation system and apps delivery is disclosed. All updates of the mobile device including system updates and feature apps updates are delivered over-the-air (“OTA”). When a system update is available, it is delivered to the mobile device for download and installation. If feature apps updates are available but a system update is not available, the system delivers the feature apps updates to the mobile device for download and installation. Feature apps updates coming from the two different routes are stored in different partitions of the OS image on the mobile device for version control. Feature apps updates included in subsequent system updates takes precedent over previously installed updates of the same or earlier versions.Type: GrantFiled: May 19, 2021Date of Patent: August 13, 2024Assignee: Snap Inc.Inventors: Mehmood Zafarullahkhan, Manish Bodhankar, Mingyang Chai
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Patent number: 12001411Abstract: Methods, computer program products, and computer systems for the management of data references in an efficient and effective manner are disclosed. Such methods, computer program products, and computer systems include receiving a change tracking stream at the computer system, identifying a data object group, and performing a deduplication management operation on the data object group. The change tracking stream is received from a client computing system. The change tracking stream identifies one or more changes made to a plurality of data objects of the client computing system. The identifying is based, at least in part, on at least a portion of the change tracking stream. The data object group represents the plurality of data objects.Type: GrantFiled: January 30, 2023Date of Patent: June 4, 2024Assignee: Veritas Technologies LLCInventors: Xianbo Zhang, Jialun Liu, Weibao Wu
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Patent number: 11900140Abstract: A data protection system includes a splitter configured to reduce latencies when splitting writes in a computing environment. The splitter captures a write and adds metadata to augment the write with virtual related information. The augmented data is provided to a smartNIC while the write is then processed in the IO stack. The smartNIC may have a volume only visible to the splitter. The smartNIC also includes processing power that allows data protection operations to be performed at the smartNIC rather than with the processing resources of the host.Type: GrantFiled: March 3, 2021Date of Patent: February 13, 2024Assignee: EMC IP HOLDING COMPANY LLCInventors: Jehuda Shemer, Srinivas Kangyampeta
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Patent number: 11892902Abstract: The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.Type: GrantFiled: September 9, 2021Date of Patent: February 6, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventor: YanLan Liu
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Patent number: 11861177Abstract: Methods, systems, and devices for configurable verify level are described. A host device may determine a target level of reliability for a set of data stored in a memory device. The host device may transmit, to the memory device, a command indicating the target level of reliability and a request to perform one or more error management operations for the set of data based on or in response to the target level of reliability. The memory device may determine the target level of reliability and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the set of data. The memory device may transmit, to the host device, an indication of a level of reliability of the set of data based on or in response to the command and performing the set of error management operations.Type: GrantFiled: August 6, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 11823759Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.Type: GrantFiled: August 16, 2021Date of Patent: November 21, 2023Assignee: Texas Instruments IncorporatedInventors: Charles Lance Fuoco, Brian Karguth, Jay Bryan Reimer, Samuel Paul Visalli
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Patent number: 11797872Abstract: A quantum prediction AI system includes a quantum prediction circuit adapted to receive an input vector representing a subset of a time-sequential sequence; encode the input vector as a corresponding qubit register; apply a trained quantum circuit to the qubit register; and measure one or more qubits output from the quantum prediction circuit to infer a next data point in the series following the subset represented by the input vector.Type: GrantFiled: September 20, 2019Date of Patent: October 24, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Alexei V. Bocharov, Eshan Kemp, Michael Hartley Freedman, Martin Roetteler, Krysta Marie Svore
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Patent number: 11789832Abstract: In various examples, a computing device of a dispersed storage network (DSN) receives a store data request including a data object. The computing device identifies a storage unit pool associated with the store data request. The storage unit pool includes a plurality of storage sets, each of the storage sets associated with a plurality of address ranges that are associated with a respective set of memories of the storage set. The computing device identifies a first set of memories of a first storage set of the storage unit pool, and issues a set of write slice requests to the first set of memories to initiate storage of encoded data slices produced from the data object. When an unfavorable storage condition is detected, the computing device identifies a second set of memories of the first storage set and facilitates storage of the data object in the second set of memories.Type: GrantFiled: March 31, 2020Date of Patent: October 17, 2023Assignee: PURE STORAGE, INC.Inventor: Jason K. Resch
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Patent number: 11775209Abstract: A controller for controlling a memory device may include: a sequence detector suitable for determining, each time a set number of data chunks are processed, whether the set number of recently processed data chunks are sequential data chunks, based on the lengths of the data chunks and logical-address-adjacency of the data chunks; and a processor suitable for performing a sequential operation according to the determination result, until next determination.Type: GrantFiled: April 15, 2020Date of Patent: October 3, 2023Assignee: SK hynix Inc.Inventor: Kwang-Su Kim
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Patent number: 11700299Abstract: Provided are a request processing unit to send a first process distribution request to other information processing apparatuses via a communication I/F unit, the first process distribution request being a request for ordering execution of a first process on a first; and an order destination selecting unit to receive, via the communication I/F unit, as a response to the first process distribution request, a first estimated reply time calculated as the time required to receive the transfer of the first data and to reply a first process result obtained by executing the first process on the first data, to use the first estimated reply time to select an order destination to which the execution of the first process is to be ordered by the plurality of information processing apparatuses, and to order the execution of the first process on the first data to the order destination via the communication interface unit.Type: GrantFiled: February 5, 2019Date of Patent: July 11, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Ayako Nagata, Junji Sukeno, Masahide Koike, Susumu Iino, Keiichi Tsuda, Kiyoyasu Maruyama
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Patent number: 11656783Abstract: One example method includes intercepting an IO issued by an application, writing the IO and IO metadata to a splitter journal in NVM, forwarding the IO to storage, and asynchronous with operations occurring along an IO path between the application and storage, evacuating the splitter journal by sending the IO and IO metadata from the splitter journal to a replication site. In this example, sending the IO and IO metadata from the journal to the replication site does not increase a latency associated with the operations on the IO path.Type: GrantFiled: February 27, 2020Date of Patent: May 23, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Itay Azaria, Kfir Wolfson, Jehuda Shemer, Saar Cohen
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Patent number: 11656963Abstract: A storage device includes an integrity checking module checking integrity of data stored in a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device, and an HMB mapping module mapping, if the integrity checking module determines the data as corrupted, the first HMB address to a second address.Type: GrantFiled: February 24, 2022Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeon Woo Kim, Jea Young Kwon, Walter Jun
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Patent number: 11593203Abstract: A method for proactively rebuilding user data in a plurality of storage nodes of a storage cluster is provided. The method includes distributing user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can read the user data, using erasure coding, despite loss of two of the storage nodes. The method includes determining that one of the storage nodes is unreachable and determining to rebuild the user data for the one of the storage nodes that is unreachable. The method includes reading the user data across a remainder of the plurality of storage nodes, using the erasure coding and writing the user data across the remainder of the plurality of storage nodes, using the erasure coding. A plurality of storage nodes within a single chassis that can proactively rebuild the user data stored within the storage nodes is also provided.Type: GrantFiled: May 21, 2021Date of Patent: February 28, 2023Assignee: Pure Storage, Inc.Inventors: John Martin Hayes, John Colgrove, Robert Lee, Igor Ostrovsky, Joshua P. Robinson
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Patent number: 11579990Abstract: Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.Type: GrantFiled: January 6, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventor: Alan J. Wilson
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Patent number: 11537292Abstract: A method and apparatus for enhancing reliability of a data storage device. The storage device controller is configured to convert a typical UBER-type event to an MTBF (FFR) event by converting a data error event into a drive functional failure. In this context, the converted error is not counted as an UBER type event for purposes of determining the reliability of the storage device.Type: GrantFiled: June 24, 2020Date of Patent: December 27, 2022Assignee: Western Digital Technologies, Inc.Inventors: Karin Inbar, Avichay Haim Hodes, Einat Lev
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Patent number: 11494103Abstract: A storage system comprises a plurality of storage nodes each comprising one or more storage devices and a processor coupled to a memory. The storage system is configured to store data blocks across the storage devices of the storage nodes utilizing a redundant array of independent disks (RAID) arrangement. At least a given one of the storage nodes is configured to store a plurality of RAID metadata bitmaps in persistent storage of the storage node so as to be available for a recovery operation in the event of a detected failure, to identify a particular subset of the RAID metadata bitmaps to be updated in conjunction with an additional operation other than the recovery operation, and to temporarily store the identified subset of the RAID metadata bitmaps in the memory of the storage node in a manner determined based at least in part on an operation type of the additional operation.Type: GrantFiled: August 2, 2019Date of Patent: November 8, 2022Assignee: EMC IP Holding Company LLCInventors: Anton Kucherov, David Meiri
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Patent number: 11455215Abstract: Systems and methods for unified application-level backup and restore using heterogeneous cloud-based backup service providers. An application programming interface is configured to process both data level replication operations as well as application-level operations that are executed to carry out high-level commands between a virtualized computing environment and any one or more of the heterogeneous cloud-based backup service providers. The API receives commands from applications in the virtualized computing environment. The API processes commands from the applications so as to facilitate replication of data to selected one or more cloud-based backup service providers. The commands perform data level replication operations as well as application-level operations for storing content to the cloud-based service provider. After a failure event and/or upon receipt of a restore command, the API initiates application-level operations that restore the application and its constituent entities.Type: GrantFiled: April 29, 2019Date of Patent: September 27, 2022Assignee: Nutanix Inc.Inventors: Parthasarathy Ramachandran, Binny Sher Gill, Naveen Kumar, Karthik Chandrasekaran
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Patent number: 11442495Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.Type: GrantFiled: September 25, 2020Date of Patent: September 13, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Ranjith Kumar Sajja, Sreekanth Godey, Anirudh R. Acharya
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Patent number: 11442829Abstract: Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.Type: GrantFiled: March 16, 2020Date of Patent: September 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ryan Patrick King, Kevin M. Mcilvain, Gary A. Van Huben
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Patent number: 11417994Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.Type: GrantFiled: November 24, 2020Date of Patent: August 16, 2022Assignee: Dell Products L.P.Inventors: Isaac Qin Wang, Jing Zhang
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Patent number: 11379356Abstract: A memory system includes a memory device and a controller. The memory device includes a memory block configured to store target data. The controller is configured to maintain the target data in a write buffer until a program operation to the memory block succeeds, update a write cache tag regarding the target data when the program operation fails and a read only mode is entered, and read the target data from the write buffer based on the write cache tag when a read command regarding the target data is received.Type: GrantFiled: August 18, 2020Date of Patent: July 5, 2022Assignee: SK hynix Inc.Inventor: Joo Young Lee
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Patent number: 11329036Abstract: According to one embodiment, a semiconductor memory device includes a mounting board and memory dies. The memory dies include first pad electrodes, first pull-up circuits connected to the first pad electrodes, a first output circuit that outputs a first parameter to the first pull-up circuits, first pull-down circuits connected to the first pad electrodes, a second output circuit that outputs a second parameter to the first pull-down circuits, a second pad electrode, a second pull-up circuit connected to the second pad electrode, a third output circuit that is connected to the second pad electrode, a third pad electrode, a second pull-down circuit connected to the third pad electrode, and a fourth output circuit that is connected to the third pad electrode. The second pad electrode of the second memory die is connected to the third pad electrode of the first memory die.Type: GrantFiled: February 28, 2020Date of Patent: May 10, 2022Assignee: Kioxia CorporationInventor: Hiromi Noro
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Patent number: 11314594Abstract: Techniques involve determining whether data read from a redundant array of independent disks (RAID) is corrupted, the RAID including two parity disks. The techniques further involve determining, based on the read data being corrupted, whether single-disk data recovery can recover the corrupted data. The techniques further involve recovering, based on the single-disk data recovery failing to recover the corrupted data, the corrupted data using dual-disk data recovery. Such techniques may present a recovery solution for silent data corruption of a RAID with two parity disks, such that corrupted data can be recovered in the case of either a single-disk failure or a dual-disk failure, thereby improving the storage system performance.Type: GrantFiled: September 17, 2020Date of Patent: April 26, 2022Assignee: EMC IP Holding Company LLCInventors: Haiying Tang, Zhilong Wu, Jianbin Kang, Rongrong Shang, Jian Gao
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Patent number: 11295830Abstract: There are provided a memory system and an operating method of the memory system. The memory system includes: a memory device including a plurality of memory blocks; and a memory controller for controlling the memory device to detect an initial bad block by performing an initial test operation on the plurality of memory blocks. The memory controller registers and manages, as a weak memory block, memory blocks physically adjacent to the detected initial bad block.Type: GrantFiled: May 1, 2020Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventor: Ju Hyeon Han
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Patent number: 11269720Abstract: A memory storage apparatus including a memory array and a controller circuit is provided. The memory array is configured to store a first error correcting code and a first data. The controller circuit is coupled to the memory array. The controller circuit is configured to read the first data from the memory array and determine whether an error bit of the first data is one of one or more data mask bits to decide whether to update the first error correcting code stored in the memory array. The controller circuit includes a switch element. The switch element is coupled to the memory array. The switch element receives the first data from the memory array. An error correcting procedure is not performed on the first data. In addition, a data access method is also provided.Type: GrantFiled: August 11, 2019Date of Patent: March 8, 2022Assignee: Winbond Electronics Corp.Inventor: Che-Min Lin
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Patent number: 11249892Abstract: A computer-implemented backup management method that includes performing a backup process or method for each one of N backup media storage devices, wherein N is an integer equal to or greater than 1. The method includes performing a filesystem integrity test on test data stored on a device connected to a primary network to obtain a baseline test result. The method includes activating a network switch to connect the primary network to an isolated network associated with one of the N backup media storage devices. The method includes storing a first backup copy of the user data stored on the device on the one of the N backup media storage devices. The first backup copy is stored over a first time period that begins when the storing of the first backup copy is initiated and ends when the storing of the first backup copy is completed.Type: GrantFiled: July 1, 2020Date of Patent: February 15, 2022Assignee: THE AIRGAP INC.Inventors: Samudra Vijay, Jamie Pleasants
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Patent number: 11243932Abstract: The present disclosure relates to a method, a device, and a computer program product for managing indexes in a storage system. The storage system includes storage data. In the method, a first set of data objects associated with the storage data is acquired. A first set of hashes of the first set of data objects is determined respectively. Hashes in the first set of hashes are hashes of data objects in the first set of data objects. A first file is generated in the storage system to store the first set of hashes. A first name of the first file is determined based on the hashes in the first set of hashes. An index of the storage data is created based on the first file.Type: GrantFiled: June 30, 2020Date of Patent: February 8, 2022Assignee: EMC IP Holding Company LLCInventors: Jie Liu, Haitao Li, Jian Wen, Chao Lin
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Patent number: 11237891Abstract: Embodiments of the present disclosure facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in an error memory location of a memory and a kernel function impacted by the CE. The kernel function includes a plurality of instructions including a first instruction of the kernel function at a first physical location in a first region of the memory. The first region includes the error memory location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the kernel function at a second physical location in the second region of the memory. The first physical location in the first region of the memory is updated to include an instruction to branch to the second physical location in the second region of the memory.Type: GrantFiled: February 12, 2020Date of Patent: February 1, 2022Assignee: International Business Machines CorporationInventors: Aravinda Prasad, Mahesh Jagannath Salgaonkar
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Patent number: 11182148Abstract: A method includes determining that initial boot block (IBB) firmware at an information handling system is invalid. The method further includes identifying that a redundant copy of the IBB firmware is stored at the information handling system, and executing the redundant copy of the IBB firmware.Type: GrantFiled: March 13, 2018Date of Patent: November 23, 2021Assignee: Dell Products L.P.Inventors: Wei Liu, Po-Yu (Smith) Cheng
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Patent number: 11169888Abstract: A storage system according to certain embodiments includes a client-side repository (CSR). The CSR may communicate with a client at a higher data transfer rate than the rate used for communication between the client and secondary storage. During copy operations, for instance, some or all of the data being backed up or otherwise copied to secondary storage is stored in the CSR. During restore operations, copies of the data stored in the CSR is accessed from the CSR instead of from secondary storage, improving performance. Remaining data blocks not stored in the CSR can be restored from secondary storage.Type: GrantFiled: December 18, 2018Date of Patent: November 9, 2021Assignee: Commvault Systems, Inc.Inventors: Manoj Kumar Vijayan, Deepak Raghunath Attarde, Hetalkumar N. Joshi
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Patent number: 11151001Abstract: Embodiments are directed to managing data in a file system over a network. A source file system that includes a plurality of objects may be provided. A replication job that copies each object associated with a source replication snapshot to a target file system may be executed. The replication job may be associated with a job identifier. Recovery point information that includes the job identifier, a source snapshot number that corresponds to the source replication snapshot, a target snapshot number that corresponds to a target replication snapshot may be generated. The recovery point information may be stored on the source file system and a copy of the recovery point information may be stored on the target file system. The recovery point information or the copy of the recovery point information may be employed to recover from errors detected during execution of a next replication job.Type: GrantFiled: January 28, 2020Date of Patent: October 19, 2021Assignee: Qumulo, Inc.Inventors: Sihang Su, Kevin David Jamieson, Michael Anthony Chmiel
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Patent number: 11086727Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).Type: GrantFiled: April 30, 2019Date of Patent: August 10, 2021Assignee: RUBRIK, INC.Inventors: Benjamin Travis Meadowcroft, Li Ding, Shaomin Chen, Hardik Vohra, Arijit Banerjee, Abhay Mitra, Kushaagra Goyal, Arnav Gautum Mishra, Samir Rishi Chaudhry, Suman Swaroop, Kunal Sean Munshani, Mudit Malpani
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Patent number: 11068341Abstract: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.Type: GrantFiled: September 30, 2019Date of Patent: July 20, 2021Assignee: Microchip Technology Inc.Inventor: John L. McCollum
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Patent number: 10996867Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.Type: GrantFiled: July 9, 2019Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventors: Jianmin Huang, Kulachet Tanpairoj, Harish Reddy Singidi, Ting Luo
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Patent number: 10983862Abstract: A method of responding to failures in a tiered storage system is provided. The method includes (a) rebuilding a set of failed storage extents belonging to a first storage tier; (b) receiving a notification that a particular storage extent has failed while rebuilding the set of failed storage extents belonging to the first tier; and (c) upon determining that the particular storage extent belongs to a second storage tier that has a higher priority than does the first storage tier: (1) pausing rebuilding the set of failed storage extents belonging to the first storage tier, (2) rebuilding the particular storage extent, and (3) resuming rebuilding the set of failed storage extents belonging to the first storage tier after rebuilding the particular storage extent. An apparatus, system, and computer program product for performing a similar method are also provided.Type: GrantFiled: April 30, 2019Date of Patent: April 20, 2021Assignee: EMC IP Holding Company LLCInventors: Philippe Armangau, Vamsi K. Vankamamidi, Pavan Vutukuri
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Global coordination of in-progress operation risks for multiple distributed storage network memories
Patent number: 10915380Abstract: A method for coordinating management of operation risks in a distributed storage network (DSN) that includes multiple distributed computing systems including DSN memories begins with a global coordinating unit receiving messages including metadata from managing units associated with the multiple distributed computing systems. The method continues with the global coordinating unit determining, based on the metadata, that storage units in one or more of the distributed computing systems are executing or planning to execute an operation that could result in data loss or data outage. The method continues with the global coordinating unit transmitting an alert, including a command to halt the operation at the affected distributed computing systems.Type: GrantFiled: July 16, 2018Date of Patent: February 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick A. Tamborski, Bart R. Cilfone, Alan M. Frazier, Sanjaya Kumar -
Patent number: 10879660Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.Type: GrantFiled: July 26, 2019Date of Patent: December 29, 2020Assignee: Dell Products, L.P.Inventors: Isaac Qin Wang, Jing Zhang
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Patent number: 10866854Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.Type: GrantFiled: September 22, 2017Date of Patent: December 15, 2020Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad