Plurality Of Memory Devices (e.g., Array, Etc.) Patents (Class 714/6.2)
  • Patent number: 10554752
    Abstract: A method begins by a dispersed storage (DS) processing module identifying, by a first storage unit of a dispersed storage network (DSN), an encoded data slice for transfer to a second storage unit of the DSN. The method continues by the first storage unit determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group by the first storage unit sending an encoded data slice transfer message to the second storage unit. The encoded data slice transfer message includes the encoded data slice and information regarding the fan-out encoded data slice group. The second storage unit stores the encoded data slice and generates copies of the encoded data slice based on the fan-out encoded data slice group and stores the copies of the encoded data slice.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Asimuddin Kazi
  • Patent number: 10511334
    Abstract: An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 10498820
    Abstract: The present invention relates to a data storage and retrieval system. The system includes a at least one client device; and at least one-server. The server includes at least one memory, a processor and a log store. The client data is divided into different blocks and stored in the server. Different logs are generated for each block and stored in the log store. The storage in the server are audited for ensuring their integrity. The present invention also relates to a method used to store and retrieve data form the above system. The present invention also relates to a method used to initialize empty buffers in a storage of a system.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 3, 2019
    Assignee: KOC UNIVERSITY
    Inventors: Alptekin Kupcu, Mohammad Etemad
  • Patent number: 10496482
    Abstract: A technique for managing RAID storage in a data storage system provides a mapping subsystem and a RAID subsystem and employs the mapping subsystem to direct repair operations on damaged RAID stripes. The mapping subsystem stores metadata that provides information about data stored in the RAID subsystem and locations of that data on RAID stripes. In response to detection of a damaged RAID stripe, the mapping subsystem selectively determines, based on the metadata, whether to perform repair operations or to avoid repair operations. As many repair operations can safely be avoided, the disclosed technique has the effect of reducing unnecessary processing in the data storage system. When the RAID subsystem includes flash drives, the technique also reduces write amplification, thus preserving flash drives which might otherwise be subject to premature wear.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov
  • Patent number: 10490243
    Abstract: A memory device includes a memory, and a processor coupled to the memory and configured to hold memory information corresponding to the memory, access information corresponding to access to the memory, and storage information indicating a storage area of the access information, extract, based on the storage information, an access information code including the access information, output the memory information in response to a read request from an external, and output the extracted access information code in response to an acknowledgment received from the external corresponding to the memory information.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 26, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Yoshitsugu Goto
  • Patent number: 10491405
    Abstract: Systems and methods for cryptographic security verification include receiving, using a dedicated short range communications system, a message from a remote vehicle or an infrastructure system. A processor determines whether a current number of attempted message verifications per second is less than a predetermined threshold. The processor performs verification of the message in response to determining that the current number of attempted message verifications per second is less than the threshold. The processor determines whether the message falls within at least one predetermined category of message type and performs verification of the message in response to the current number of attempted message verifications per second not being less than the threshold and the message falling within the at least one predetermined category of message type. The processor processes the message in response to the message being verified.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: November 26, 2019
    Assignees: DENSO International America, Inc., DENSO CORPORATION
    Inventor: Aaron D. Weinfield
  • Patent number: 10374637
    Abstract: A method for creating distributed erasure coding chunks in a distributed storage system with unbalanced load is disclosed. The operations comprise configuring the distributed storage system into at least k+m zones, wherein each zone accumulates at least l primary backup chunks of original data chunks replicated from different remote zones, and wherein l<k, and preparing the distributed storage system for recovery from a failure of 1 to m zones of the at least k+m zones including, in each zone, encoding the at least l primary backup chunks to create m coding chunks using an erasure coding having parameters k+m, wherein in each zone in which fewer than k primary backup chunks have been accumulated, at most k?l predetermined virtual chunks are used to create partial coding chunks.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 6, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Konstantin Buinov, Alexander Rakulenko, Andrey Kurilov, Kirill Gusakov
  • Patent number: 10360180
    Abstract: To identify slice errors, a processing module of a computing device in a dispersed storage network (DSN) sends first list digest requests to at least first and second dispersed storage (DS) units. The requests indicates a first range of slice names to include in a first list digest. The processing module receives digest responses from the DS units, and compares the digest responses to determine whether they identify the same slices. If they do not identify the same slices, the processing module sends second list digest requests indicating a sub-range of the first range of slice names to include in second list digests. The sub-range continues to be narrowed until the processing module identifies at least one sub-range of slice names where a slice error exists.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastien Vas, Zachary J. Mark, Jason K. Resch
  • Patent number: 10331614
    Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Dimitrios Ziakas, Bassam N. Coury, Mohan J. Kumar, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich
  • Patent number: 10318649
    Abstract: A computer-implemented method according to one embodiment includes identifying an accessing of a file within an operating system, checking an in-memory cache for path information associated with the file, checking an external cache for the path information associated with the file, conditionally retrieving the path information associated with the file by performing a file system lookup and adding the path information associated with the file to the in-memory cache and the external cache, and returning the path information.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Umesh Deshpande, Wayne A. Sawdon, Vasily Tarasov
  • Patent number: 10318175
    Abstract: A storage device. The device includes both low-latency persistent memory and higher-latency nonvolatile memory. The persistent memory may be used for write caching or for journaling. A B-tree may be used to maintain an index of write requests temporarily stored in the persistent memory. Garbage collection may be performed in the nonvolatile memory while write requests are being stored in the persistent memory.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jianjian Huo, Vikas K. Sinha, Gunneswara R. Marripudi, Indira Joshi, Harry R. Rogers
  • Patent number: 10310752
    Abstract: Techniques for allocating mapped RAID extents of a RAID group may include: determining a pool of N physical storage devices; selecting M physical storage portions, wherein each of the M physical storage portions is selected from a different one of the N physical storage devices of the pool; and allocating a first mapped RAID extent as the selected M physical storage portions. The first mapped RAID extent may denotes a stripe of the RAID group. Physical storage portions for each mapped RAID extent may be selected from the N physical storage devices with a goal of maintaining even distribution of the selected portions among the N physical storage devices. Such selection may use a neighborhood matrix and a subset of all possible combinations of M physical storage devices that may be selected from the N physical storage devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 4, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne Li, Geng Han, Jian Gao, Jibing Dong, Jianbin Kang, Lili Chen
  • Patent number: 10296426
    Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yong Hong Shi, Qian Su, Yu Sun, Wei You
  • Patent number: 10255304
    Abstract: Elements of a database object are removed. The database object is stored as a plurality of different object portions, where each object portion is associated with one or more versions of transaction identifiers stored separately from the database object. An oldest transaction identifier is determined for a transaction for which data portions of the database object remains visible. Each object portion is examined and object portions with a threshold amount of data to remove are determined based on a comparison of the transaction identifiers for those object portions and the oldest transaction identifier. Data from the database object are removed in response to a sufficient quantity of data is to be removed from object portions containing the threshold amount of data.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Dietterich, Jeffrey M. Keller
  • Patent number: 10228867
    Abstract: A distributed object storage system comprises an encoding module configured to calculate for a plurality of predetermined values of the spreading requirement the cumulative size of the sub fragment files when stored on the file system with the predetermined block size; and select as a spreading requirement from said plurality of predetermined values a calculated value that is equal to one of said predetermined values for which the cumulative size is minimal.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 12, 2019
    Assignee: AMPLIDATA NV
    Inventors: Stefaan Vervaet, Frederik De Schrijver, Wim De Wispelaere, Wouter Van Eetvelde
  • Patent number: 10229018
    Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 12, 2019
    Assignee: Dell Products, LP
    Inventors: Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10182115
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory that is configured to perform various operations based on operational instructions. The computing device receives name range information and priority level information to handle data objects associated with the name range information and identifies object names associated with a name range. The computing device identifies EDS name ranges that respectively correspond to the object names. The computing device updates an EDS priority table to associate EDS name range(s) with the priority level information. The computing device receives a request associated with an EDS name range and accesses the EDS priority table to identify a priority level associated therewith. The computing device then processes the request based on the priority level associated with the EDS name range.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dennis A. Kalaf, S. Christopher Gladwin, Jason K. Resch
  • Patent number: 10146644
    Abstract: A method may include copying transaction rollback data to a buffer in a first memory. The method may further include calculating a checksum for the transaction rollback data, and storing the calculated checksum and a checksum pointer in the first memory. The checksum pointer may refer to a last valid location in a transactional memory region of the second memory for which the checksum is calculated. The method may further include writing, to the transactional memory region, the transaction rollback data from the buffer and the checksum and the checksum pointer from the first memory, and performing at least part of the transaction by writing new transaction data to the heap. The transaction rollback data may be useable to restore the heap to a state prior to initiating the transaction if the transaction was incomplete, upon reconnecting the card computing device after determining that a card tear event has occurred.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 4, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mikhail Aleksandrovich Smirnov, Kari Okamoto, Johnny Le
  • Patent number: 10140186
    Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Brad W. Michael, Tony E. Sawan
  • Patent number: 10126955
    Abstract: A method for big size file blocking for distributed processing by a plurality of work nodes that belong to a distributed processing system, the method comprising, dividing the file into a first area and a second area processed later than data of the first area, partitioning the first area into blocks having various sizes and partitioning the second area into blocks having a fixed size.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventor: Seong-Moon Kang
  • Patent number: 10102068
    Abstract: A method includes dispersed storage error encoding a data object in accordance with temporary parameters. The method further includes generating a first source name. The method further includes sending, in accordance with the first source name, the first sets of encoded data slices to a first set of storage units for temporary storage therein. When a determination is made to permanently store the data object, the method further includes recovering the data object from the first sets of encoded data slices. The method further includes dispersed storage error encoding the recovered data object in accordance with permanent parameters to produce second sets of encoded data slices. The method further includes generating a second source name. The method further includes sending, in accordance with the second source name, the second sets of encoded data slices to a second set of storage units for permanent storage therein.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: S. Christopher Gladwin, Timothy W. Markison, Greg Dhuse, Thomas Franklin Shirley, Jr., Wesley Leggette, Jason K. Resch, Gary W. Grube
  • Patent number: 10068662
    Abstract: A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Masashi Oya
  • Patent number: 10031934
    Abstract: Data from a database object are processed. Transaction information for a set of data of the database object is stored separate from the set of data in an allocated storage space, where the transaction information indicates visibility of the set of data to other transactions. A map structure is generated indicating storage of the set of data and the allocated storage space of the transaction information. The transaction information is altered in response to a transaction to the set of data to alter visibility of the set of data. Altering the transaction information is accomplished by providing updated transaction information within a new storage space in accordance with the transaction to the set of data and generating a descriptor for the transaction indicating an existing location of the set of data and the new storage space.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel J. Dietterich
  • Patent number: 10019355
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: July 10, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 9996411
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Patent number: 9940211
    Abstract: A resource system comprises a plurality of resource elements and a resource controller connected to the resource elements and operating the resource elements according to a predefined set of operational goals. A method of operating the resource system comprises the steps of identifying error recovery procedures that could be executed by the resource elements, categorizing each identified error recovery procedure in relation to the predefined set of operational goals, detecting that an error recovery procedure is to be performed on a specific resource element, deploying one or more actions in relation to the resource elements according to the categorization of the detected error recovery procedure, and performing the detected error recovery procedure on the specific resource element.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Bartlett, Matthew J. Fairhurst, Nicholas M. O'Rourke
  • Patent number: 9921910
    Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 20, 2018
    Assignee: NetApp, Inc.
    Inventors: Dheeraj Raghavender Sangamkar, Ajay Bakre, Vladimir Radu Avram, Emalayan Vairavanathan, Viswanath Chandrasekara Bharathi
  • Patent number: 9858142
    Abstract: Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Min Su Park
  • Patent number: 9852811
    Abstract: In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 26, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen Long Chang, Ken Hui Chen, Su Chueh Lo, Chia-Feng Cheng
  • Patent number: 9830221
    Abstract: Embodiments use data shuttle devices to restore erasure-coded data in a distributed storage environment. In some embodiments, a first data shuttle is communicatively coupled to a first node of the storage environment. On the data shuttle, first restoration data is generated from a first erasure-coded data portion stored on the first node. The first data shuttle or a second data shuttle is communicatively coupled to a second node of the storage environment. On the data shuttle at the second node, second restoration data is generated from a second erasure-coded data portion stored on the second node. Subsequent to transporting the first or second data shuttle from at least one of the other nodes to a third node, a third erasure-coded data portion is restored at the third node. The third erasure-coded data portion is generated via an erasure-coding process from one or more of the first or second restoration data.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 28, 2017
    Assignee: NETAPP, INC.
    Inventors: David Slik, Ronnie Lon Hei Chan, Vishnu Vardhan Chandra Kumaran
  • Patent number: 9823965
    Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 21, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Antonin Fried
  • Patent number: 9817727
    Abstract: Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary and a secondary replica for an instance, with each capable of residing in a separate data zone or geographic location to provide a level of reliability and availability. A database running on the primary instance can have information synchronously replicated to the secondary replica at a block level, such that the primary and secondary replicas are in sync. In the event that the monitoring component is not able to communicate with one of the replicas, the monitoring component can attempt to determine whether those replicas can communicate with each other, as well as whether the replicas have the same data generation version. Depending on the state information, the monitoring component can automatically perform a recovery operation, such as to failover to the secondary replica or perform secondary replica recovery.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: November 14, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Grant Alexander MacDonald McAlister, Swaminathan Sivasubramanian
  • Patent number: 9785524
    Abstract: A fault tolerant server according to the present invention configured to duplicate information processing by an online subsystem and an offline subsystem, the fault tolerant server operates to: execute entire copy processing for copying all data being stored in the memory of the online subsystem into the memory of the offline subsystem without stopping execution of information processing by the processor of the online subsystem, before start of duplication; detect data, the data satisfying a criterion indicating that content of data is changed during the entire copy processing, among data being stored in the memory of the online subsystem; and copy the detected data from the memory of the online subsystem into the memory of the offline subsystem.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: October 10, 2017
    Assignee: NEC Corporation
    Inventor: Chikashi Ueda
  • Patent number: 9734920
    Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin W. Gorman, Michael R. Ouellette, Patrick E. Perry
  • Patent number: 9696740
    Abstract: A system for providing backup power to a facility includes a generator, and a controller configured to determine whether electrical power to the facility has been interrupted, determine a mode of operation based on a type of occupancy currently within the facility, and if electrical power has been interrupted, then operate the generator based on the determined mode.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 4, 2017
    Assignee: Eaton Corporation
    Inventors: David G. Loucks, Todd M. Lathrop
  • Patent number: 9690665
    Abstract: A relay device includes a first storage unit, a second storage unit and a processor. The processor extracts a duplication pattern, which is an identical portion between data stored in the first storage unit in the past and data received currently. Also, the processor executes a process of storing the currently received data in the first storage unit and a process of associating an identifier with the extracted duplication pattern and storing the duplication pattern and the identifier in the second storage unit. Further, the processor edits data into edited data in which a duplication pattern included in the data has been replaced with the identifier associated with the duplication pattern when the data including a duplication pattern stored in the second storage unit has been received from a first device. Then, the processor transfers the edited data to a second device.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hiroshi Otsuka
  • Patent number: 9602405
    Abstract: A method, service appliance, and non-transitory media for establishing connections to virtual device contexts (VDCs) whereby a communication channel for each of the VDCs is identified based on connection data corresponding to each of the VDCs. A service appliance receives, from each of one or more VDCs located on a switch, a message containing connection data that identifies at least one communication channel between the service appliance and a corresponding one of the one or more VDCs from which the message was received. The connection data is stored in a memory accessible to the service appliance. The service appliance identifies a communication channel for each of a plurality of VDCs based on the connection data and an identifier corresponding to each of the plurality of VDCs. The service appliance establishes a connection to each of the plurality of VDCs using the communication channel for each of the plurality of VDCs.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 21, 2017
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Samar Sharma, Mitali Parthasarathy, Avni Baveja, Ashish Purushottam Attarde, Biju Mathews Mammen
  • Patent number: 9588857
    Abstract: When a media error occurs on a storage device of a number of storage devices of a redundant array, the logical stripe of data affected by the media error is determined. A portion of non-volatile memory is reserved and the logical stripe is backed up to this portion of non-volatile memory. A read request is subsequently serviced from the non-volatile memory and not from the storage devices. When a write request is received, it is first serviced to the storage devices. If successful, then the previously reserved portion of non-volatile memory is freed up, and subsequent requests are serviced using the storage devices. If unsuccessful, then the write request is serviced using the non-volatile memory.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 7, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventors: Timothy J. Louie, Ernest N. Mandese, Joaquin F. Pacheco
  • Patent number: 9535791
    Abstract: There is provided a storage control device that is communicably connected to a plurality of storage devices and a plurality of spare storage devices through a plurality of paths. The storage control device includes: a memory configured to store path information associating the plurality of spare storage devices and the plurality of paths with each other; and a selection unit configured to select a spare storage device that is a replacing apparatus from among the plurality of spare storage devices based on a path connection condition determined in accordance with a path in which the storage device that is a replacement target among the plurality of storage devices is connected and the path information.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 3, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yoshihito Konta, Norihide Kubota, Kenji Kobayashi
  • Patent number: 9521197
    Abstract: A method begins by a dispersed storage (DS) processing module dividing a very large data object into a plurality of data regions and generating a data object storage tracking table that includes sections for identifying one or more data regions that are available or unavailable for retrieval. The method continues with the DS processing module dividing a first data region into data segments and disperse storage error encoding the data segments to produce sets of encoded data slices. The method continues with the DS processing module sending DSN write requests regarding storing the sets of encoded data slices to storage units and when at least a write threshold number of write responses is received for each of the sets of encoded data slices, updating the data object storage tracking table to indicate that the first data region is available for retrieval.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: December 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wesley Leggette, Jason K. Resch, Yogesh Ramesh Vedpathak, Sebastien Vas, Eric Gunnar Smith, Adam Michael Gray
  • Patent number: 9514844
    Abstract: Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aravindan J. Busi, Kevin W. Gorman, Kiran K. Narayan, Michael R. Ouellette
  • Patent number: 9513807
    Abstract: Systems and methods for increasing scalability and reducing latency in relation to managing large numbers of storage arrays of a storage network. Separate, dedicated, communication channels may be established between an array manager running on a server and each of a number of storage arrays for respectively performing reading and writing operations to limit the delays imposed by repeated array connection setup and teardown and improve array communication stability (e.g., as compared to performing read/write operations over the same array connection). The read connection can be used to maintain current state information (e.g., volumes, capacities, and the like) for a plurality of storage arrays in a local cache of the array manager that can be quickly accessed by the array manager, such as for presenting substantially current, summary-type state information of the various storage arrays to a user (e.g., upon the user requesting to configure a particular storage array).
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: December 6, 2016
    Assignee: Oracle International Corporation
    Inventors: Juan Carlos Zuluaga, Alka Deshpande, Mark Vetter
  • Patent number: 9465694
    Abstract: A method and apparatus for recovering a partition based on file system metadata, which calculate core information necessary for the recovery of a partition using only the MFT entry information of $MFT and recover a deleted partition when an MBR and a GPT that correspond to the partition configuration information of a disk and a BR and a BBR that store the configuration information of a volume are deleted or destroyed. The method includes determining an unallocated area in a disk or an evidence image, collecting MFT entries from the unallocated area, generating MFT partition candidate information by analyzing the MFT entries, and creating information enabling a layout of a partition to be reconfigured based on the MFT partition candidate information, and creating a tree structure using the created information and the MFT entries.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: October 11, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyunuk Hwang, Kibom Kim, Seungyong Lee
  • Patent number: 9401955
    Abstract: A method of integrating a plurality of network storage spaces includes: receiving data in a single user interface; dividing the data into a plurality of sub-data, wherein the plurality of sub-data correspond to the plurality of network storage spaces, respectively; and uploading each of the plurality of sub-data to a corresponding network storage space among the plurality of network storage spaces.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 26, 2016
    Assignee: Wistron Corporation
    Inventors: Hung-Ming Kang, Chi-Hsiang Yeh, Jia-Cyuan Fan
  • Patent number: 9324022
    Abstract: Embodiments are directed towards classifying data using machine learning that may be incrementally refined based on expert input. Data provided to a deep learning model that may be trained based on a plurality of classifiers and sets of training data and/or testing data. If the number of classification errors exceeds a defined threshold classifiers may be modified based on data corresponding to observed classification errors. A fast learning model may be trained based on the modified classifiers, the data, and the data corresponding to the observed classification errors. And, another confidence value may be generated and associated with the classification of the data by the fast learning model. Report information may be generated based on a comparison result of the confidence value associated with the fast learning model and the confidence value associated with the deep learning model.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 26, 2016
    Assignee: Signal/Sense, Inc.
    Inventors: David Russell Williams, Jr., Luke Robert Gutzwiller, Megan Ursula Hazen, Brigham Sterling Anderson, Alan McIntyre, Tom Abeles
  • Patent number: 9304852
    Abstract: Example apparatus and methods produce a set of rateless erasure codes (e.g., fountain codes) for a file stored in a primary data store (e.g., hard drive) or in an archive system. The archive system may store the file in a redundant array of independent disks (RAID). A first subset of the rateless erasure codes are stored in an object storage using a synchronous protocol. A second subset of rateless erasure codes are stored in the object storage using an asynchronous protocol. The object storage system may inform the archive system when desired redundancy has been achieved or when desired redundancy has been lost. The archive system may buffer rateless erasure codes before providing the codes to the object storage to improve performance. A failure in the archive system or object storage system may be mitigated by retaining the file in the primary data store until the desired redundancy is achieved.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: April 5, 2016
    Assignee: Quantum Corporation
    Inventor: John Reinart
  • Patent number: 9286219
    Abstract: A method, computer program product, and computing system for defining a portion of a frontend cache system for use as a data array cache portion. One or more cache slots included within a backend cache system are identified that are going to be overwritten with hot cache data and are currently filled with cold cache data. The cold cache data included within the one or more cache slots included within the backend cache system is written to one or more cache slots included within the data array cache portion.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 15, 2016
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Arieh Don, Anat Eyal, Alex Veprinsky, Zvi Gabriel Benhanokh
  • Patent number: 9235468
    Abstract: A method for controlling flash memory includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: January 12, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Yinian Mao
  • Patent number: 9213489
    Abstract: Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes. A plurality of nonvolatile memory units may be included with computing nodes, coupled with computing nodes or coupled with input/output nodes. The input/output nodes may be included with the compute cluster or super computer, or coupled thereto. The nonvolatile memory units store data items provided by the computing nodes, and the input/output nodes maintain where the data items are stored in the nonvolatile memory units via a hash table distributed among the input/output nodes. The use of a distributed hash table allows for quick access to data items stored in the nonvolatile memory units even as the computing nodes are writing large amounts of data to the storage system quickly in bursts.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 15, 2015
    Assignee: DataDirect Networks, Inc.
    Inventors: Paul Nowoczynski, Jason Micah Cope, Gordon Manning, Don Molaro, Michael Piszczek, Pavan Uppu
  • Patent number: 9164827
    Abstract: Method and apparatus for protecting data comprising dividing data into a plurality of data subsets. Generating parity data for each data subset and another data subset of the plurality of data subsets. Generating parity data for each data subset and a second other data subset of the plurality of data subsets. Method and apparatus for recovering data comprising retrieving one or more data subsets. Retrieving two or more different parity data sets generated for one data subset. Regenerating any missing data subsets using the retrieved one or more data subset and two or more retrieved parity data sets. Combining the one or more retrieved data subset and regenerated missing data subsets to form the recovered data.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 20, 2015
    Assignee: Qando Services Inc.
    Inventors: Iskender Syrgabekov, Yerkin Zadauly