Plurality Of Memory Devices (e.g., Array, Etc.) Patents (Class 714/6.2)
  • Patent number: 10942807
    Abstract: A plurality of failure domains are communicatively coupled to each other via a network, and each of the plurality of failure domains is coupled to one or more storage devices. A failure resilient stripe is distributed across the plurality of storage devices, such that two or more blocks of the failure resilient stripe are located in each failure domain.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 9, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti
  • Patent number: 10909121
    Abstract: The subject technology receives first metadata corresponding to a set of micro-partitions. The subject technology generates second metadata for a grouping of the first metadata. The subject technology generates a first data structure including the first metadata and a second data structure including the second metadata, the second data structure including information associating the second metadata to the first metadata. The subject technology stores the first data structure and the second data structure in persistent storage as a first file and a second file. The subject technology receives a query on a table. Further, the subject technology analyzes the query against cumulative table metadata to determine whether data stored in the table matches the query.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 2, 2021
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Yi Fang, Martin Hentschel, Ashish Motivala, Spyridon Triantafyllis, Yizhi Zhu
  • Patent number: 10866955
    Abstract: The subject technology receives first metadata corresponding to a set of micro-partitions. The subject technology generates second metadata for a grouping of the first metadata. The subject technology generates a first data structure including the first metadata and a second data structure including the second metadata, the second data structure including information associating the second metadata to the first metadata. Further, the subject technology stores the first data structure and the second data structure in persistent storage as a first file and a second file.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 15, 2020
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Yi Fang, Martin Hentschel, Ashish Motivala, Spyridon Triantafyllis, Yizhi Zhu
  • Patent number: 10860210
    Abstract: Division RAID (Redundant Array of Independent Disks) for disk array expansion is provided herein. A data storage system as described herein can include a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can include a disk initialization component that divides a first storage disk into partitions comprising a uniform number of partitions; an array expansion component that adds the first storage disk to a logical storage array, wherein the logical storage array comprises second storage disks, the second storage disks respectively being divided into partitions comprising the uniform number of partitions; and a data allocation component that allocates a data group to respective partitions of the first storage disk and a subset of the second storage disks in a deterministic order, resulting in a set of allocated partitions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Kuolin Hua
  • Patent number: 10831723
    Abstract: A computer-implemented method according to one embodiment includes identifying an accessing of a file within an operating system, checking an in-memory cache for path information associated with the file, checking an external cache for the path information associated with the file, conditionally retrieving the path information associated with the file by performing a file system lookup and adding the path information associated with the file to the in-memory cache and the external cache, and returning the path information.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Umesh Deshpande, Wayne A. Sawdon, Vasily Tarasov
  • Patent number: 10831651
    Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a controller to cause the controller to perform a method which includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, and writing the data streams simultaneously, in parallel, to page-stripes having a same index across a series of planes of memory. The writing of the first data stream begins at an opposite end of the series of planes as the writing of the second data stream, the writing of the streams being toward one another. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Patent number: 10768822
    Abstract: A method for increasing effective storage capacity in a heterogeneous storage array is disclosed. In one embodiment, such a method determines a number of smaller-capacity storage drives and a number of larger-capacity storage drives in a storage array. The method further determines which RAID arrays in the storage array may be composed exclusively of the larger-capacity storage drives. Using this information, the method establishes a first set of RAID arrays in the storage array that will be composed exclusively of the larger-capacity storage drives and a second set of RAID arrays that may contain the smaller-capacity storage drives. The method then initiates a process to swap the smaller-capacity storage drives in the first set with the larger-capacity storage drives in the second set until the first set of RAID arrays is composed exclusively of the larger-capacity storage drives. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Karl A. Nielsen, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 10733062
    Abstract: The present invention provides a software storage unit, a backup method, and a backup control program capable of completing data transfer to a data backup destination in a shorter time. The software storage unit includes a software storage section constructed across a plurality of physical machines and a switch section coupled to an external network, wherein the software storage section grasps data to back up, among stored data, which is to be transferred to a data backup destination, splits the grasped data into a plurality of data parts, and issues a command to transfer the split data parts from respective ones of the plurality of physical machines to the data backup destination via the switch section.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 4, 2020
    Assignee: NEC CORPORATION
    Inventor: Kouichi Matsumoto
  • Patent number: 10698763
    Abstract: A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Uhn Cha
  • Patent number: 10698844
    Abstract: A storage system interface (SSI) located externally to a data storage system serves as an interface between a host system and the data storage system. The SSI may be part of the host system, and in some embodiments may be a separate and discrete component from the remainder of the host system, physically connected to the remainder of the host system by one or more buses that connect periphery devices to the remainder of the host system. The SSI may be physically connected directly to the internal fabric of the data storage system, and may be implemented on a card or chipset physically connected to the remainder of a host system by a PCIe bus. The SSI may provide functionality traditionally provided on data storage systems, enabling at least some I/O processing to be offloaded from data storage systems to hosts that include SSIs.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: June 30, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Ian Wigmore, Alesia A. Tringale, Jason J. Duquette
  • Patent number: 10691532
    Abstract: Systems, devices, and methods for providing ECC-assisted scrubbing of memory devices and error correction of memory devices. In one embodiment, a method is disclosed comprising obtaining, at a storage device, data and a first parity portion to write to a memory device, the first parity portion generated via a first encoding; encoding, at the storage device, the data with a second encoding to generate a second parity portion; aligning, by the storage device, the data, the first parity portion, and the second parity portion according to a predefined alignment scheme, the aligning generating aligned data; and writing, by the storage device, the aligned data to the memory device.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 23, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Patent number: 10684801
    Abstract: Methods, systems, and computer-readable media for a bulk ingestion interface for a distributed data storage system are described. A bulk ingestion interface may allow bulk data to be ingested into a distributed data storage system using compute resources separate from respective compute resources of the distributed data storage system used to perform access requests to datasets stored on one or more resource hosts of the distributed data storage system.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 16, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Mukesh Kumar Bhangria, Vipin A, Aditya Abhas, Venkata Satya Srujan Kanumuri, Shiva Kumar Korikana, Umang Popli, Amit Kumar Rai, Pallav Milankumar Shah
  • Patent number: 10684927
    Abstract: The failure of a storage unit in a storage array of a storage system may render the storage unit unresponsive to any requests. Any writes to the storage system that occur during the failure of the storage unit will not be reflected on the failed unit, rendering some of the failed unit's data stale. Assuming the failed unit's data is not corrupted but is just stale, a partial rebuild may be performed on the failed unit, selectively reconstructing only data that is needed to replace the stale data. Described herein are techniques for storing information that identifies the data that needs to be rebuilt. When the storage unit fails, the segment identifier associated with the last data segment written to the storage system may be stored. Upon the storage unit recovering, the storage system can rebuild only those data segments whose identifier is greater than the stored segment identifier.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: June 16, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Anil Nanduri, Chunqi Han, Murali Krishna Vishnumolakala
  • Patent number: 10665318
    Abstract: A semiconductor system may include a first and second rank, and a semiconductor device. The semiconductor device may be configured to receive information on the first and second ranks to prioritize which rank out of the first and second ranks to perform an operation with instead of the other rank. The information may include PVT conditions. The information may include error occurrences of the first or second ranks.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10666470
    Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
  • Patent number: 10621089
    Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Mohamed Arafa, Raj K. Ramanujan
  • Patent number: 10613782
    Abstract: A data storage system includes: a storage device having a first storage and a physically separate second storage. A first core includes first data information related to first data to be written to the first storage, and a second core includes second data information related to second data to be written to the second storage. A shared memory is accessible by the first and second cores, and an emergency power system supplies backup power to the first and second cores when external power supplied to the data storage system is less than a minimum threshold operating power. When a write operation error of the second core is detected in a first mode, the first core writes the second data information to the first storage as third data information and writes the second data to the first storage as third data by referring to the second data information.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Uk Kim, In Su Choi
  • Patent number: 10588053
    Abstract: The present application discloses a method for receiving, by a terminal, data in a wireless communication system. Specifically, the method for receiving data comprises the steps of: receiving a first division code from a first helper node in a first time unit; overhearing a second division code transmitted from a second helper node to another terminal in a second time unit; and acquiring the data by using the first division code and the second division code.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 10, 2020
    Assignees: LG ELECTRONICS INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Tae Yeoung Kim, Dongin Kim, Wan Choi, Hanbyul Seo
  • Patent number: 10554752
    Abstract: A method begins by a dispersed storage (DS) processing module identifying, by a first storage unit of a dispersed storage network (DSN), an encoded data slice for transfer to a second storage unit of the DSN. The method continues by the first storage unit determining whether the encoded data slice is part of a fan-out encoded data slice group and, when it is part of a fan-out encoded data slice group by the first storage unit sending an encoded data slice transfer message to the second storage unit. The encoded data slice transfer message includes the encoded data slice and information regarding the fan-out encoded data slice group. The second storage unit stores the encoded data slice and generates copies of the encoded data slice based on the fan-out encoded data slice group and stores the copies of the encoded data slice.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Asimuddin Kazi
  • Patent number: 10511334
    Abstract: An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Jang Seob Kim
  • Patent number: 10496482
    Abstract: A technique for managing RAID storage in a data storage system provides a mapping subsystem and a RAID subsystem and employs the mapping subsystem to direct repair operations on damaged RAID stripes. The mapping subsystem stores metadata that provides information about data stored in the RAID subsystem and locations of that data on RAID stripes. In response to detection of a damaged RAID stripe, the mapping subsystem selectively determines, based on the metadata, whether to perform repair operations or to avoid repair operations. As many repair operations can safely be avoided, the disclosed technique has the effect of reducing unnecessary processing in the data storage system. When the RAID subsystem includes flash drives, the technique also reduces write amplification, thus preserving flash drives which might otherwise be subject to premature wear.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Robert P. Foley, Peter Puhov
  • Patent number: 10498820
    Abstract: The present invention relates to a data storage and retrieval system. The system includes a at least one client device; and at least one-server. The server includes at least one memory, a processor and a log store. The client data is divided into different blocks and stored in the server. Different logs are generated for each block and stored in the log store. The storage in the server are audited for ensuring their integrity. The present invention also relates to a method used to store and retrieve data form the above system. The present invention also relates to a method used to initialize empty buffers in a storage of a system.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 3, 2019
    Assignee: KOC UNIVERSITY
    Inventors: Alptekin Kupcu, Mohammad Etemad
  • Patent number: 10490243
    Abstract: A memory device includes a memory, and a processor coupled to the memory and configured to hold memory information corresponding to the memory, access information corresponding to access to the memory, and storage information indicating a storage area of the access information, extract, based on the storage information, an access information code including the access information, output the memory information in response to a read request from an external, and output the extracted access information code in response to an acknowledgment received from the external corresponding to the memory information.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 26, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Yoshitsugu Goto
  • Patent number: 10491405
    Abstract: Systems and methods for cryptographic security verification include receiving, using a dedicated short range communications system, a message from a remote vehicle or an infrastructure system. A processor determines whether a current number of attempted message verifications per second is less than a predetermined threshold. The processor performs verification of the message in response to determining that the current number of attempted message verifications per second is less than the threshold. The processor determines whether the message falls within at least one predetermined category of message type and performs verification of the message in response to the current number of attempted message verifications per second not being less than the threshold and the message falling within the at least one predetermined category of message type. The processor processes the message in response to the message being verified.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: November 26, 2019
    Assignees: DENSO International America, Inc., DENSO CORPORATION
    Inventor: Aaron D. Weinfield
  • Patent number: 10374637
    Abstract: A method for creating distributed erasure coding chunks in a distributed storage system with unbalanced load is disclosed. The operations comprise configuring the distributed storage system into at least k+m zones, wherein each zone accumulates at least l primary backup chunks of original data chunks replicated from different remote zones, and wherein l<k, and preparing the distributed storage system for recovery from a failure of 1 to m zones of the at least k+m zones including, in each zone, encoding the at least l primary backup chunks to create m coding chunks using an erasure coding having parameters k+m, wherein in each zone in which fewer than k primary backup chunks have been accumulated, at most k?l predetermined virtual chunks are used to create partial coding chunks.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 6, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Konstantin Buinov, Alexander Rakulenko, Andrey Kurilov, Kirill Gusakov
  • Patent number: 10360180
    Abstract: To identify slice errors, a processing module of a computing device in a dispersed storage network (DSN) sends first list digest requests to at least first and second dispersed storage (DS) units. The requests indicates a first range of slice names to include in a first list digest. The processing module receives digest responses from the DS units, and compares the digest responses to determine whether they identify the same slices. If they do not identify the same slices, the processing module sends second list digest requests indicating a sub-range of the first range of slice names to include in second list digests. The sub-range continues to be narrowed until the processing module identifies at least one sub-range of slice names where a slice error exists.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastien Vas, Zachary J. Mark, Jason K. Resch
  • Patent number: 10331614
    Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Dimitrios Ziakas, Bassam N. Coury, Mohan J. Kumar, Murugasamy K. Nachimuthu, Thi Dang, Russell J. Wunderlich
  • Patent number: 10318649
    Abstract: A computer-implemented method according to one embodiment includes identifying an accessing of a file within an operating system, checking an in-memory cache for path information associated with the file, checking an external cache for the path information associated with the file, conditionally retrieving the path information associated with the file by performing a file system lookup and adding the path information associated with the file to the in-memory cache and the external cache, and returning the path information.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Umesh Deshpande, Wayne A. Sawdon, Vasily Tarasov
  • Patent number: 10318175
    Abstract: A storage device. The device includes both low-latency persistent memory and higher-latency nonvolatile memory. The persistent memory may be used for write caching or for journaling. A B-tree may be used to maintain an index of write requests temporarily stored in the persistent memory. Garbage collection may be performed in the nonvolatile memory while write requests are being stored in the persistent memory.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jianjian Huo, Vikas K. Sinha, Gunneswara R. Marripudi, Indira Joshi, Harry R. Rogers
  • Patent number: 10310752
    Abstract: Techniques for allocating mapped RAID extents of a RAID group may include: determining a pool of N physical storage devices; selecting M physical storage portions, wherein each of the M physical storage portions is selected from a different one of the N physical storage devices of the pool; and allocating a first mapped RAID extent as the selected M physical storage portions. The first mapped RAID extent may denotes a stripe of the RAID group. Physical storage portions for each mapped RAID extent may be selected from the N physical storage devices with a goal of maintaining even distribution of the selected portions among the N physical storage devices. Such selection may use a neighborhood matrix and a subset of all possible combinations of M physical storage devices that may be selected from the N physical storage devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 4, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne Li, Geng Han, Jian Gao, Jibing Dong, Jianbin Kang, Lili Chen
  • Patent number: 10296426
    Abstract: According to one aspect of the present invention, there is provided a method for performing storage control. Member storage media and a hot spare storage medium are identified in a storage system. The member storage media are members of a storage medium array, and the hot spare storage medium is for joining in the storage medium array when a member storage medium fails. Data on a member storage medium having a write amplification effect is migrated to the hot spare storage medium. In the member storage medium having a write amplification effect, an erase operation is performed on a storage medium where the migrated data is located. Embodiments of the present invention can alleviate adverse impact caused by a write amplification effect.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yong Hong Shi, Qian Su, Yu Sun, Wei You
  • Patent number: 10255304
    Abstract: Elements of a database object are removed. The database object is stored as a plurality of different object portions, where each object portion is associated with one or more versions of transaction identifiers stored separately from the database object. An oldest transaction identifier is determined for a transaction for which data portions of the database object remains visible. Each object portion is examined and object portions with a threshold amount of data to remove are determined based on a comparison of the transaction identifiers for those object portions and the oldest transaction identifier. Data from the database object are removed in response to a sufficient quantity of data is to be removed from object portions containing the threshold amount of data.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Dietterich, Jeffrey M. Keller
  • Patent number: 10228867
    Abstract: A distributed object storage system comprises an encoding module configured to calculate for a plurality of predetermined values of the spreading requirement the cumulative size of the sub fragment files when stored on the file system with the predetermined block size; and select as a spreading requirement from said plurality of predetermined values a calculated value that is equal to one of said predetermined values for which the cumulative size is minimal.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 12, 2019
    Assignee: AMPLIDATA NV
    Inventors: Stefaan Vervaet, Frederik De Schrijver, Wim De Wispelaere, Wouter Van Eetvelde
  • Patent number: 10229018
    Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 12, 2019
    Assignee: Dell Products, LP
    Inventors: Vadhiraj Sankaranarayanan, Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10182115
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory that is configured to perform various operations based on operational instructions. The computing device receives name range information and priority level information to handle data objects associated with the name range information and identifies object names associated with a name range. The computing device identifies EDS name ranges that respectively correspond to the object names. The computing device updates an EDS priority table to associate EDS name range(s) with the priority level information. The computing device receives a request associated with an EDS name range and accesses the EDS priority table to identify a priority level associated therewith. The computing device then processes the request based on the priority level associated with the EDS name range.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dennis A. Kalaf, S. Christopher Gladwin, Jason K. Resch
  • Patent number: 10146644
    Abstract: A method may include copying transaction rollback data to a buffer in a first memory. The method may further include calculating a checksum for the transaction rollback data, and storing the calculated checksum and a checksum pointer in the first memory. The checksum pointer may refer to a last valid location in a transactional memory region of the second memory for which the checksum is calculated. The method may further include writing, to the transactional memory region, the transaction rollback data from the buffer and the checksum and the checksum pointer from the first memory, and performing at least part of the transaction by writing new transaction data to the heap. The transaction rollback data may be useable to restore the heap to a state prior to initiating the transaction if the transaction was incomplete, upon reconnecting the card computing device after determining that a card tear event has occurred.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 4, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mikhail Aleksandrovich Smirnov, Kari Okamoto, Johnny Le
  • Patent number: 10140186
    Abstract: An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Brad W. Michael, Tony E. Sawan
  • Patent number: 10126955
    Abstract: A method for big size file blocking for distributed processing by a plurality of work nodes that belong to a distributed processing system, the method comprising, dividing the file into a first area and a second area processed later than data of the first area, partitioning the first area into blocks having various sizes and partitioning the second area into blocks having a fixed size.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventor: Seong-Moon Kang
  • Patent number: 10102068
    Abstract: A method includes dispersed storage error encoding a data object in accordance with temporary parameters. The method further includes generating a first source name. The method further includes sending, in accordance with the first source name, the first sets of encoded data slices to a first set of storage units for temporary storage therein. When a determination is made to permanently store the data object, the method further includes recovering the data object from the first sets of encoded data slices. The method further includes dispersed storage error encoding the recovered data object in accordance with permanent parameters to produce second sets of encoded data slices. The method further includes generating a second source name. The method further includes sending, in accordance with the second source name, the second sets of encoded data slices to a second set of storage units for permanent storage therein.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: S. Christopher Gladwin, Timothy W. Markison, Greg Dhuse, Thomas Franklin Shirley, Jr., Wesley Leggette, Jason K. Resch, Gary W. Grube
  • Patent number: 10068662
    Abstract: A semiconductor device that includes a plurality of memory cells assigned with addresses that are different from each other, a redundant memory cell replacing a defective memory cell among the memory cells, a fuse circuit storing an address of the defective memory cell, an access control circuit accessing the redundant memory cell when the address of the defective memory cell stored in the fuse circuit is supplied, and a roll call circuit outputting the address of the defective memory cell to outside the semiconductor device in a serial manner.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Masashi Oya
  • Patent number: 10031934
    Abstract: Data from a database object are processed. Transaction information for a set of data of the database object is stored separate from the set of data in an allocated storage space, where the transaction information indicates visibility of the set of data to other transactions. A map structure is generated indicating storage of the set of data and the allocated storage space of the transaction information. The transaction information is altered in response to a transaction to the set of data to alter visibility of the set of data. Altering the transaction information is accomplished by providing updated transaction information within a new storage space in accordance with the transaction to the set of data and generating a descriptor for the transaction indicating an existing location of the set of data and the new storage space.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel J. Dietterich
  • Patent number: 10019355
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: July 10, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 9996411
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Patent number: 9940211
    Abstract: A resource system comprises a plurality of resource elements and a resource controller connected to the resource elements and operating the resource elements according to a predefined set of operational goals. A method of operating the resource system comprises the steps of identifying error recovery procedures that could be executed by the resource elements, categorizing each identified error recovery procedure in relation to the predefined set of operational goals, detecting that an error recovery procedure is to be performed on a specific resource element, deploying one or more actions in relation to the resource elements according to the categorization of the detected error recovery procedure, and performing the detected error recovery procedure on the specific resource element.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Bartlett, Matthew J. Fairhurst, Nicholas M. O'Rourke
  • Patent number: 9921910
    Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 20, 2018
    Assignee: NetApp, Inc.
    Inventors: Dheeraj Raghavender Sangamkar, Ajay Bakre, Vladimir Radu Avram, Emalayan Vairavanathan, Viswanath Chandrasekara Bharathi
  • Patent number: 9858142
    Abstract: Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Min Su Park
  • Patent number: 9852811
    Abstract: In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 26, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuen Long Chang, Ken Hui Chen, Su Chueh Lo, Chia-Feng Cheng
  • Patent number: 9830221
    Abstract: Embodiments use data shuttle devices to restore erasure-coded data in a distributed storage environment. In some embodiments, a first data shuttle is communicatively coupled to a first node of the storage environment. On the data shuttle, first restoration data is generated from a first erasure-coded data portion stored on the first node. The first data shuttle or a second data shuttle is communicatively coupled to a second node of the storage environment. On the data shuttle at the second node, second restoration data is generated from a second erasure-coded data portion stored on the second node. Subsequent to transporting the first or second data shuttle from at least one of the other nodes to a third node, a third erasure-coded data portion is restored at the third node. The third erasure-coded data portion is generated via an erasure-coding process from one or more of the first or second restoration data.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: November 28, 2017
    Assignee: NETAPP, INC.
    Inventors: David Slik, Ronnie Lon Hei Chan, Vishnu Vardhan Chandra Kumaran
  • Patent number: 9823965
    Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 21, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Antonin Fried
  • Patent number: 9817727
    Abstract: Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary and a secondary replica for an instance, with each capable of residing in a separate data zone or geographic location to provide a level of reliability and availability. A database running on the primary instance can have information synchronously replicated to the secondary replica at a block level, such that the primary and secondary replicas are in sync. In the event that the monitoring component is not able to communicate with one of the replicas, the monitoring component can attempt to determine whether those replicas can communicate with each other, as well as whether the replicas have the same data generation version. Depending on the state information, the monitoring component can automatically perform a recovery operation, such as to failover to the secondary replica or perform secondary replica recovery.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: November 14, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Grant Alexander MacDonald McAlister, Swaminathan Sivasubramanian