Synchronization Control Patents (Class 714/707)
  • Patent number: 10547339
    Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas and first and second radio-frequency modules. The device may include a conductive housing having dielectric antenna windows. The first module may generate first millimeter wave signals in a first communications band. The antenna may transmit the first signals to external equipment through the dielectric window at a transmit power level. The antenna may receive control signals in the second communications band from the external equipment through the dielectric window. The first and second communications bands may include frequencies greater than 10 GHz. The second module may pass the received control signals to the first module to adjust the transmit power level of the first signals transmitted by the antenna. A duplexer may be interposed between the modules and the antenna for isolating the first and second communications bands.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 28, 2020
    Assignee: Apple Inc.
    Inventors: Boon W. Shiu, Jobin Jacob, Jorge L. Rivera Espinoza, Kiavash Baratzadeh, Louie J. Sanguinetti, Ruben Caballero
  • Patent number: 10534034
    Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Daniel S. Froelich, Debendra Das Sharma
  • Patent number: 10025585
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for applying a plurality of program patch sets on a plurality of computer programs. Virtual machines are prepared to be patchable, in response to a suspended computer program. Synchronized snapshots of the virtual machines are created. A plurality of binary code sections of each of the synchronized snapshots are determined. Symbol data information of each of the synchronized snapshots are analyzed, based on the program patch sets. The determined binary code sections are replaced with a set of patch data, based on the plurality of program patch sets, resulting in patched snapshots for each of the synchronized snapshots. Dependencies of the patch data are adjusted, based on the replaced plurality of binary code sections and the execution of the computer program on each of the virtual machines are resumed using the plurality of patched snapshots.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jakob C. Lang, Angel Nunez Mencias, Thomas Pohl, Martin Troester
  • Patent number: 10025582
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for applying a plurality of program patch sets on a plurality of computer programs. Virtual machines are prepared to be patchable, in response to a suspended computer program. Synchronized snapshots of the virtual machines are created. A plurality of binary code sections of each of the synchronized snapshots are determined. Symbol data information of each of the synchronized snapshots are analyzed, based on the program patch sets. The determined binary code sections are replaced with a set of patch data, based on the plurality of program patch sets, resulting in patched snapshots for each of the synchronized snapshots. Dependencies of the patch data are adjusted, based on the replaced plurality of binary code sections and the execution of the computer program on each of the virtual machines are resumed using the plurality of patched snapshots.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jakob C. Lang, Angel Nunez Mencias, Thomas Pohl, Martin Troester
  • Patent number: 9904587
    Abstract: Anomalous behavior in a multi-tenant computing environment may be identified by analyzing hardware sensor value data associated with hardware events on a host machine. A privileged virtual machine instance executing on a host machine acquires hardware sensor values and causes the values to be compared to other hardware sensor value data that may be indicative of anomalous behavior; for example, various threshold values, patterns, and/or signatures of hardware counter values generated by analyzing and correlating hardware event counter data. In this manner, potential anomalous behavior on an instance may be determined without having to access customer data or workloads associated with the instance.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nachiketh Rao Potlapally, Donald Lee Bailey, Jr., Richard Weatherly
  • Patent number: 9804918
    Abstract: A physical layer (PHY) preamble is generated, the PHY preamble defined by a first wireless communication protocol and including a first portion that corresponds to a legacy PHY preamble defined by a second, legacy wireless communication protocol. The PHY preamble also includes a second portion that is defined by the first wireless communication protocol. Error detection information is generated using a first field in the first portion of the PHY preamble. The second portion of the PHY preamble is generated to include the error detection information in a second field. The PHY data unit is generated so that the PHY data unit includes the PHY preamble.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: October 31, 2017
    Assignee: Marvell International Ltd.
    Inventors: Hongyuan Zhang, Mingguang Xu, Yakun Sun
  • Patent number: 9591672
    Abstract: There is provided a wireless communication device including a receiving unit for receiving a wireless signal from a base station; a transmitting unit for transmitting an initial signal for connecting to the base station; a random number generator for generating a random number; and a controller for, after a synchronization process based on the wireless signal received from the base station, controlling a timing when the transmitting unit transmits the initial signal in accordance with a delay time corresponding to the random number generated by the random number generator.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: March 7, 2017
    Assignee: Sony Corporation
    Inventors: Atsushi Yoshizawa, Hiroaki Takano
  • Patent number: 9565014
    Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Paul A. Ganfield
  • Patent number: 9483340
    Abstract: A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies one or more bit errors. The system may determine whether an estimated bit error rate (BER) for the bit stream is likely to satisfy a threshold. The system may select an approach for determining the estimated BER for the bit stream. The estimated BER may be determined based on combining the current bit error count with a quantity of bits received in the time interval when the estimated BER is likely to exceed the threshold, and the estimated BER may be determined based on the current bit error count and one or more past bit error counts when the estimated BER is unlikely to exceed the threshold. The system may determine the estimated BER.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 1, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: John D. Johnson, Tapan Kumar Chauhan
  • Patent number: 9363045
    Abstract: Methods and systems are described for analyzing signal impairments using a test and measurement instrument. A method may include decomposing aggregate signal impairments into signal impairments that are correlated and uncorrelated to an acquired data pattern. The uncorrelated signal impairments may be further decomposed into periodic signal impairments (e.g., PJ) and non-periodic uncorrelated signal impairments. A PDF of the non-periodic uncorrelated signal impairments may be mathematically integrated, thereby producing an estimated cumulative distribution function (CDF) curve. Random signal impairments may be estimated as an unbound Gaussian distribution. The CDF curve of the non-periodic uncorrelated signal impairments and the unbound Gaussian distribution may be plotted in Q-space on a display device. Non-periodic bounded uncorrelated signal impairments (e.g., NP-BUJ) PDF may then be isolated. Bounded uncorrelated signal impairments PDF may then be synthesized.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 7, 2016
    Assignee: TEKTRONIX, INC.
    Inventors: Maria Agoston, Pavel R. Zivny
  • Patent number: 9312955
    Abstract: Raman interference (also known as Raman scattering) during an idle frame transmission state in a passive optical network (PON) having radio frequency video overlay is reduced by generating and transmitting data packets having both random data and random length. Randomly varying both the packet data content and the packet length can achieve significant improvement in Raman interference reduction. The random packet data and length in effect spreads the interference across a spectrum wide enough that there is no interference effect perceptible to a television viewer.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 12, 2016
    Assignee: Alcatel Lucent
    Inventors: Duane R. Remein, John Lane Moss, Hugh Andrew Lagle, III
  • Patent number: 9209813
    Abstract: An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: December 8, 2015
    Assignee: Oracle International Corporation
    Inventor: Robert P. Masleid
  • Patent number: 9106498
    Abstract: A method for symbol synchronization of received digital signal and a digital signal reception apparatus are provided. The method comprises steps of correlating the received digital signal with the received signal delayed by one symbol so as to obtain a first correlation value result as a combined effort of a strongest path and other paths; removing substantially effect of the strongest path from the first correlation result so as to obtain a second correlation result which exhibits contribution of a fastest path; searching a maximum correlation value and its position of the fastest path so as to determine symbol synchronization timing for initiating FFT processing. The digital signal reception apparatus is characterized by a symbol timing detecting unit for determining symbol synchronization timing of the fastest path through substantially removing the effect of a strongest path.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: August 11, 2015
    Assignee: Thomson Licensing
    Inventors: Gang Liu, Li Zou
  • Patent number: 8982974
    Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: March 17, 2015
    Inventor: John W Bogdan
  • Patent number: 8976776
    Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Motorola Solutions, Inc.
    Inventors: David G. Wiatrowski, Dipendra M. Chowdhary, Thomas B. Bohn
  • Patent number: 8843793
    Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: September 23, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Hyoung-Gon Lee
  • Patent number: 8837301
    Abstract: A wireless communication terminal is disclose. The terminal includes a transceiver coupled to a processor configured to determine that a subset of a plurality of REs must be excluded from demodulation, the plurality of resource elements (REs) received in a signal from a first base station, to estimate a hypothetical block error rate (BLER) based on the signal received from the first base station by excluding the subset of the plurality of Res, and to estimate channel state information based on the hypothetical block error rate (BLER).
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 16, 2014
    Assignee: Motorola Mobility LLC
    Inventor: Sandeep H. Krishnamurthy
  • Patent number: 8826106
    Abstract: A method includes generating first and second data units corresponding to first and second PHY modes, respectively. Generating the first data unit includes FEC encoding first information bits, mapping the FEC-encoded bits to first constellation symbols, and generating first OFDM symbols to include the first constellation symbols. The first OFDM symbols utilize a first tone spacing, and include a first number of non-zero tones collectively spanning a first bandwidth. Generating the second data unit includes FEC encoding second information bits, block encoding the FEC-encoded bits, mapping the block-encoded bits to second constellation symbols, and generating second OFDM symbols to include the second constellation symbols. The second OFDM symbols utilize the first tone spacing, and include a second number of non-zero tones collectively spanning a second bandwidth less than the first bandwidth. The second number of non-zero tones is less than the first number of non-zero tones.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 2, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Hongyuan Zhang, Raja Banerjea, Sudhir Srinivasa
  • Patent number: 8824612
    Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Yantao Ma
  • Patent number: 8819531
    Abstract: The present inventions are related to systems and methods for information divergence based data processing. As an example, a system is disclosed that includes a scheduling circuit operable to calculate a first quality metric using a first information divergence value calculated based at least in part on the first detected output, and to calculate a second quality metric using a second information divergence value calculated based at least in part on the second detected output. A decoder input is selected based at least in part on the first quality metric and the second quality metric.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Shaohua Yang
  • Patent number: 8804892
    Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 12, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Ian Kyles
  • Patent number: 8761325
    Abstract: A clock generator generates a clock signal used for sampling a received signal by a comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal and a controller adjusts the phase of the clock signal to maximize the vertical eye opening of the signal at the sampling time. In an example embodiment, the phase of the clock signal is adjusted in a first direction and a measure of vertical eye opening of the signal is compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment is made in the same direction and if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction is made. By increasing the vertical eye opening of the signal the signal-to-noise ratio of the received signal is improved.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 24, 2014
    Inventors: Ben Willcocks, Chris Born, Miguel Marquina, Andrew Sharratt, Allard Van Der Horst
  • Patent number: 8745432
    Abstract: A delay controller includes an acquiring section that acquires synchronization timings indicating timings when a plurality of controllers, which control via a line a plurality of transmitters that transmit data, synchronously control the transmitters, a determining section that determines a reference synchronization timing serving as a reference for synchronization between the controllers, on the basis of the synchronization timings acquired by the acquiring section, and a synchronization information transmitting section that transmits synchronization information to the controllers, the synchronization information being used when the controllers receive data from each of the transmitters at the reference synchronization timing determined by the determining section.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Hideki Iwami, Eisaburo Itakura, Satoshi Tsubaki, Hiroaki Takahashi, Kei Kakitani, Tamotsu Munakata, Hideaki Murayama
  • Patent number: 8724660
    Abstract: Provided is a transmission apparatus for a dynamic lane operation in a multi-lane based Ethernet system, including: a monitor to monitor whether at least one lane being used by the transmission apparatus is modified; an upper layer manager to transmit, to a Reconciliation Sublayer (RS) of the transmission apparatus, lane change information associated with the modified at least one lane; and an RS manager to transmit the lane change information to an RS of a reception apparatus corresponding to the RS of the transmission apparatus.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 13, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Kyeongeun Han
  • Patent number: 8705633
    Abstract: A video transport system is provided for transporting as 8B/10B coded video stream across a 64B/66B coded link, wherein forward error correction is provided without the overhead of the prior art. The system also provides a system with the ability to recover 64B/66B Encoded blocks that have corrupt Sync bits.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 22, 2014
    Assignee: Omron Management Center of America, Inc.
    Inventor: Kenneth R. Herrity
  • Patent number: 8675753
    Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 18, 2014
    Assignee: Metanoia Technologies, Inc.
    Inventor: Jeffrey C. Strait
  • Patent number: 8659959
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
  • Patent number: 8649400
    Abstract: A method and apparatus for timing an output signal based on timing of an input signal is provided. A method includes determining a first clock rate derived from the input signal during a first time interval measured by a reference clock. The method also includes signal processing logic to determine a second clock rate during a second time interval based on an error signal that is calculated as a difference between the first clock rate multiplied by the second time interval and a previous value of the second clock rate multiplied by the first time interval.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 11, 2014
    Assignee: Ciena Corporation
    Inventors: Roger R. Darr, Jeff Nichols
  • Patent number: 8634510
    Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: January 21, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaohua Kong, Vannam Dang, Tirdad Sowlati
  • Patent number: 8627156
    Abstract: A device under test (DUT) is tested by: receiving a signal transmitted by the DUT, wherein the signal includes first portions that include scrambled bits produced from a selected bit pattern and a selected scrambling algorithm, and further includes second portions that include unscrambled bits, the first portions and second portions being interspersed within the signal; detecting received scrambled bits within the received signal; generating a test bit sequence using the selected scrambling algorithm and the selected bit pattern, including generating a bit of the test bit sequence for each of the received scrambled bits within the received signal, and not generating a bit of the test bit sequence for each of the received unscrambled bits within the received signal; and comparing the received scrambled bits to the test bit sequence to determine a bit error rate of the received signal.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 7, 2014
    Assignee: Agilent Technologies, Inc.
    Inventor: Bruce Erickson
  • Patent number: 8576964
    Abstract: There is provided a radio receiver including: a first matched filter, a second matched filter, a first frame synchronization determining unit and a first phase determining unit. The first matched filter performs matching processing on the basis of N first tap coefficients and sign information of a received digital signal to obtain first output data. The second matched filter performs matching processing on the basis of M (M is a natural number smaller than the N) second tap coefficients, the sign information and amplitude information of the received digital to obtain second output data. The first frame synchronization determining unit determines a first frame synchronization timing of the received digital signal on the basis of the first output data. The first phase determining unit determines a first phase amount of the received digital signal on the basis of the second output data and the first frame synchronization timing.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Taniguchi, Hirotsugu Kajihara
  • Patent number: 8576961
    Abstract: A method for determining an overlap and add length estimate comprises determining a plurality of correlation values of a plurality of ordered frequency domain samples obtained from a data frame; comparing the correlation values of a first subset of the samples to a first predetermined threshold to determine a first edge sample; comparing the correlation values of a second subset of the samples to a second predetermined threshold to determine a second edge sample; using the first and second edge samples to determine an overlap and add length estimate; and providing the overlap and add length estimate to an overlap and add circuit.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: November 5, 2013
    Assignee: Olympus Corporation
    Inventors: Haidong Zhu, Dumitru Mihai Ionescu, Abu Amanullah
  • Patent number: 8578221
    Abstract: A method is provided for determining a measure of error of a device under test (DUT). The method includes storing baseband data received from the DUT in a storage device, segmenting the baseband data into multiple data segments, determining processing parameters for one data segment of the plurality of data segments, and storing the determined processing parameters for the one data segment. The method further includes retrieving additional data segments of the multiple data segments from the storage device, and processing the additional data segments using the stored processing parameters for the one data segment. The measure of error of the DUT is determined based at least in part on data from the processed additional data segments.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: November 5, 2013
    Assignee: Agilent Technologies, Inc.
    Inventors: Tetsuaki Ikoma, Shuji Kubo, Takuya Yoshimura, Ikura Yoshida
  • Patent number: 8526554
    Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: September 3, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Michael Hennedy
  • Patent number: 8520787
    Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 27, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Michael Hennedy
  • Patent number: 8514920
    Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 20, 2013
    Assignee: LSI Corporation
    Inventors: Christopher J. Abel, Parag Parikh, Vladimir Sindalovsky
  • Patent number: 8489974
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 16, 2013
    Assignee: salesforce.com, inc.
    Inventors: Mark Movida, Didier Prophete, Ronald F. Fischer, Marni Gasn, Anshu Agarwal
  • Patent number: 8442021
    Abstract: A method for predicting performance of a radio link in a wireless communication terminal including hypothesizing a second codeword including information associated with a hypothesized first codeword, obtaining channel state information from a received signal, and estimating a decoder error rate of the first codeword under a condition that the second codeword may not be decoded correctly, wherein the decoder error rate is estimated using the channel state information.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: May 14, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Sandeep Krishnamurthy, Ravi Kuchibhotla
  • Patent number: 8433962
    Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 30, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8433964
    Abstract: Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: April 30, 2013
    Assignee: Advantest Corporation
    Inventor: Tokunori Akita
  • Patent number: 8428206
    Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: April 23, 2013
    Assignee: NXP B.V.
    Inventor: Yan Li
  • Patent number: 8416902
    Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 9, 2013
    Inventors: Ian Kyles, Eugene Pahomsky
  • Patent number: 8412996
    Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics SA
    Inventors: Frederic Bancel, Nicolas Berard, Philippe Roquelaure
  • Patent number: 8374256
    Abstract: A communication system includes a synchronizing signal generator that generates a synchronizing signal based on a timing of an alternating waveform in a power line, a data communicating circuit that performs the data communication, and a communication controller that controls to acquire a transmitting right utilizing a timing of the synchronizing signal and to control the communication circuit in accordance with whether or not the communication apparatus acquires the transmitting right.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: February 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Nobutaka Kodama, Hisao Koga, Yuji Igata, Shinichiro Ohmi, Go Kuroda
  • Patent number: 8375259
    Abstract: Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 8369307
    Abstract: Scheduler 304 performs scheduling such that the communication terminal apparatuses to transmit packets to are determined according to the order in CIR information output from demodulator 303, and determines the modulation schemes and coding rates of the packets. Command detector 305 detects an ARQ command transmitted from the communication terminal apparatus determined in scheduler 304, outputs an ACK/NACK signals to buffer 306, and outputs a SUSUPEND signal or a GIVEUP signal to scheduler 304. Scheduler 304 stops retransmission upon receiving a SUSPEND signal or a GIVEUP signal from command detector 305, and redoes the scheduling. Thus, it is possible to improve overall system throughput in a wireless communication system that performs packet transmission.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Kenichi Miyoshi, Hidetoshi Suzuki
  • Patent number: 8347160
    Abstract: An information communication terminal performs communications with another information communication terminal over a radio communication network system. In the information communication terminal, a receiving unit receives an externally transmitted frame. In a state where error correction is to be performed, a correction processing unit outputs data after performing error correction according to correction information in the frame on data in the frame received by the receiving unit. In a state where the error correction is not to be performed, the correction processing unit outputs the data without performing the error correction on the data in the frame received by the receiving unit. A determining unit determines whether the error correction is to be performed by the correction processing unit or not.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: January 1, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Koki Okada
  • Patent number: 8341458
    Abstract: An apparatus, method and computer program operable in a network controls consistency guarantees of a plurality of data copies in a storage apparatus, and includes: a lease control component for extending a lease to the storage apparatus; and a consistency freeze/thaw component responsive to a failure indication for initiating a consistency freeze action at the storage apparatus prior to expiration of the current group lease period. It may further include a timer component for waiting the apparatus for a predetermined period after the consistency freeze action, where the consistency freeze/thaw component is operable to initiate a thaw action at the storage apparatus.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Henry E. Butterworth, Carlos F. Fuente
  • Patent number: 8335950
    Abstract: A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: December 18, 2012
    Assignee: Tektronix, Inc.
    Inventor: Que Thuy Tran
  • Patent number: 8320437
    Abstract: In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: November 27, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Florian Hartwich, Andreas-Juergen Rohatschek, Eberhard Boehl