Abstract: A decoding engine within an integrated-circuit (IC) component iteratively executes error detection/correction operations with respect to a sequence of input data volumes to generate a corresponding sequence of error syndrome values, the input data volumes each including a first block of data and corresponding error correction code retrieved from one or more external memory components together with a respective one of a plurality of q-bit data patterns. Selector circuitry within the decoding engine selects one of the plurality of q-bit data patterns to be an output q-bit value according to error-count differentiation indicated by the error syndrome values.

Abstract: A system includes a server to generate a real-time stream of audio packets and a client device to decode and playback the audio content of the stream. The client device includes a network interface configured to receive a stream of audio packets via a network and a buffer configured to temporarily buffer a subset of audio packets of the stream. The client device further includes an audio decoder having an input to receive audio packets from the buffer and an output to provide corresponding segments of a decoded audio data stream. The client device also includes a stream monitoring module configured to provide an audio packet of the subset in the buffer which was previously decoded by the decoder to the input of the decoder again for a repeated decoding in place of a decoding of an audio packet that is lost or late.

Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.

Abstract: A method and system for storing data in portable storage devices. Specifically, the disclosed method and system provide a solution for the write-hole problem inflicting persistent storage, especially redundant array of independent disks (RAID) configured storage. The write-hole problem may arise from the occurrence of power failure during a write operation of data to RAID configured storage, subsequently resulting in disparities between the data and parity information thereof—the consistency there-between of which is critical to data reconstruction upon disk failure. To rectify these inconsistencies, a full-stripe (or full-block set) write is recommended, which the disclosed method and system implements through the use of, and re-mapping of relationships between, virtual, physical, and in-memory block sets.

Abstract: A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.

Abstract: An indication to remove one or more data in a time series database is received. A metadata index associated with the time series database is updated to indicate a soft removal of each data of the one or more data. A data hole index associated with the time series database is updated to indicate a data hole at a location of each data of the one or more data in the time series database. Responsive to an input/output rate for the time series database being below a threshold, the data hole of each data of the one or more data is optimized.

Abstract: An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

Abstract: The present application discloses methods for debugging and using an overdrive brightness value look-up table, and a display panel. The debugging method includes the following steps: measuring actual brightness by exhaustively enumerating all gray scales in an available gray scale range at a preset gray scale interval as a gray scale M of a previous frame, and exhaustively enumerating all the gray scales in the available gray scale range at the preset gray scale interval as a target gray scale N of a current frame, and correspondingly recording all actual brightness values in the overdrive brightness value look-up table.

Abstract: A block generation method and apparatus, and a block receiving method and apparatus are disclosed. The block generation method includes: generating a first block and a second block, where the first block includes a first block unit, the second block includes a second block unit, a first indicator is configured in the first block unit, and the first indicator is used to indicate whether the second block unit is a control code; and sending the first block and the second block. According to this method, an indicator is configured in a block unit in the first block to indicate whether an adjacent block is a control code, so that a boundary between a control code and a data code is determined, thereby avoiding extra indication information for an indication and reducing overheads of the indication information.

Abstract: A duty correction device includes a global duty correction circuit and a local duty correction circuit. The global duty correction circuit performs a global duty correction operation on a first clock signal and a second clock signal based on a local correction signal. The local duty correction circuit performs a local duty correction by detecting phases of the first and second clock signals, and enables the local correction signal when a number of the local duty correction operation reaches a threshold value.

Abstract: A time synchronization system includes a first wireless device and a second wireless device. A wireless unit of the first wireless device wirelessly transmits timing information and time information separately, the time information being acquired from a first clock and relating to a transmission time when the timing information was transmitted. A wireless unit of the second wireless device receives the wirelessly transmitted timing information and time information separately. A correction unit of the second wireless device corrects s a second clock on the basis of a reference time indicated by the second clock at a time when the wireless unit received the timing information, and a transmission time obtained from the time information.

Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas and first and second radio-frequency modules. The device may include a conductive housing having dielectric antenna windows. The first module may generate first millimeter wave signals in a first communications band. The antenna may transmit the first signals to external equipment through the dielectric window at a transmit power level. The antenna may receive control signals in the second communications band from the external equipment through the dielectric window. The first and second communications bands may include frequencies greater than 10 GHz. The second module may pass the received control signals to the first module to adjust the transmit power level of the first signals transmitted by the antenna. A duplexer may be interposed between the modules and the antenna for isolating the first and second communications bands.

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for applying a plurality of program patch sets on a plurality of computer programs. Virtual machines are prepared to be patchable, in response to a suspended computer program. Synchronized snapshots of the virtual machines are created. A plurality of binary code sections of each of the synchronized snapshots are determined. Symbol data information of each of the synchronized snapshots are analyzed, based on the program patch sets. The determined binary code sections are replaced with a set of patch data, based on the plurality of program patch sets, resulting in patched snapshots for each of the synchronized snapshots. Dependencies of the patch data are adjusted, based on the replaced plurality of binary code sections and the execution of the computer program on each of the virtual machines are resumed using the plurality of patched snapshots.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for applying a plurality of program patch sets on a plurality of computer programs. Virtual machines are prepared to be patchable, in response to a suspended computer program. Synchronized snapshots of the virtual machines are created. A plurality of binary code sections of each of the synchronized snapshots are determined. Symbol data information of each of the synchronized snapshots are analyzed, based on the program patch sets. The determined binary code sections are replaced with a set of patch data, based on the plurality of program patch sets, resulting in patched snapshots for each of the synchronized snapshots. Dependencies of the patch data are adjusted, based on the replaced plurality of binary code sections and the execution of the computer program on each of the virtual machines are resumed using the plurality of patched snapshots.

Abstract: Anomalous behavior in a multi-tenant computing environment may be identified by analyzing hardware sensor value data associated with hardware events on a host machine. A privileged virtual machine instance executing on a host machine acquires hardware sensor values and causes the values to be compared to other hardware sensor value data that may be indicative of anomalous behavior; for example, various threshold values, patterns, and/or signatures of hardware counter values generated by analyzing and correlating hardware event counter data. In this manner, potential anomalous behavior on an instance may be determined without having to access customer data or workloads associated with the instance.

Abstract: A physical layer (PHY) preamble is generated, the PHY preamble defined by a first wireless communication protocol and including a first portion that corresponds to a legacy PHY preamble defined by a second, legacy wireless communication protocol. The PHY preamble also includes a second portion that is defined by the first wireless communication protocol. Error detection information is generated using a first field in the first portion of the PHY preamble. The second portion of the PHY preamble is generated to include the error detection information in a second field. The PHY data unit is generated so that the PHY data unit includes the PHY preamble.

Abstract: There is provided a wireless communication device including a receiving unit for receiving a wireless signal from a base station; a transmitting unit for transmitting an initial signal for connecting to the base station; a random number generator for generating a random number; and a controller for, after a synchronization process based on the wireless signal received from the base station, controlling a timing when the transmitting unit transmits the initial signal in accordance with a delay time corresponding to the random number generated by the random number generator.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies one or more bit errors. The system may determine whether an estimated bit error rate (BER) for the bit stream is likely to satisfy a threshold. The system may select an approach for determining the estimated BER for the bit stream. The estimated BER may be determined based on combining the current bit error count with a quantity of bits received in the time interval when the estimated BER is likely to exceed the threshold, and the estimated BER may be determined based on the current bit error count and one or more past bit error counts when the estimated BER is unlikely to exceed the threshold. The system may determine the estimated BER.

Abstract: Methods and systems are described for analyzing signal impairments using a test and measurement instrument. A method may include decomposing aggregate signal impairments into signal impairments that are correlated and uncorrelated to an acquired data pattern. The uncorrelated signal impairments may be further decomposed into periodic signal impairments (e.g., PJ) and non-periodic uncorrelated signal impairments. A PDF of the non-periodic uncorrelated signal impairments may be mathematically integrated, thereby producing an estimated cumulative distribution function (CDF) curve. Random signal impairments may be estimated as an unbound Gaussian distribution. The CDF curve of the non-periodic uncorrelated signal impairments and the unbound Gaussian distribution may be plotted in Q-space on a display device. Non-periodic bounded uncorrelated signal impairments (e.g., NP-BUJ) PDF may then be isolated. Bounded uncorrelated signal impairments PDF may then be synthesized.

Abstract: Raman interference (also known as Raman scattering) during an idle frame transmission state in a passive optical network (PON) having radio frequency video overlay is reduced by generating and transmitting data packets having both random data and random length. Randomly varying both the packet data content and the packet length can achieve significant improvement in Raman interference reduction. The random packet data and length in effect spreads the interference across a spectrum wide enough that there is no interference effect perceptible to a television viewer.

Abstract: An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.

Abstract: A method for symbol synchronization of received digital signal and a digital signal reception apparatus are provided. The method comprises steps of correlating the received digital signal with the received signal delayed by one symbol so as to obtain a first correlation value result as a combined effort of a strongest path and other paths; removing substantially effect of the strongest path from the first correlation result so as to obtain a second correlation result which exhibits contribution of a fastest path; searching a maximum correlation value and its position of the fastest path so as to determine symbol synchronization timing for initiating FFT processing. The digital signal reception apparatus is characterized by a symbol timing detecting unit for determining symbol synchronization timing of the fastest path through substantially removing the effect of a strongest path.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error in data received from a telecommunication device, an error frequency calculation unit configured to calculate an error frequency based at least in part on the error detected by the error detection unit, and a mode decision unit configured to decide a scheduling mode for the telecommunication device based at least in part on the error frequency calculated by the error frequency calculation unit.

Abstract: A wireless communication terminal is disclose. The terminal includes a transceiver coupled to a processor configured to determine that a subset of a plurality of REs must be excluded from demodulation, the plurality of resource elements (REs) received in a signal from a first base station, to estimate a hypothetical block error rate (BLER) based on the signal received from the first base station by excluding the subset of the plurality of Res, and to estimate channel state information based on the hypothetical block error rate (BLER).

Abstract: A method includes generating first and second data units corresponding to first and second PHY modes, respectively. Generating the first data unit includes FEC encoding first information bits, mapping the FEC-encoded bits to first constellation symbols, and generating first OFDM symbols to include the first constellation symbols. The first OFDM symbols utilize a first tone spacing, and include a first number of non-zero tones collectively spanning a first bandwidth. Generating the second data unit includes FEC encoding second information bits, block encoding the FEC-encoded bits, mapping the block-encoded bits to second constellation symbols, and generating second OFDM symbols to include the second constellation symbols. The second OFDM symbols utilize the first tone spacing, and include a second number of non-zero tones collectively spanning a second bandwidth less than the first bandwidth. The second number of non-zero tones is less than the first number of non-zero tones.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: The present inventions are related to systems and methods for information divergence based data processing. As an example, a system is disclosed that includes a scheduling circuit operable to calculate a first quality metric using a first information divergence value calculated based at least in part on the first detected output, and to calculate a second quality metric using a second information divergence value calculated based at least in part on the second detected output. A decoder input is selected based at least in part on the first quality metric and the second quality metric.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A clock generator generates a clock signal used for sampling a received signal by a comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal and a controller adjusts the phase of the clock signal to maximize the vertical eye opening of the signal at the sampling time. In an example embodiment, the phase of the clock signal is adjusted in a first direction and a measure of vertical eye opening of the signal is compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment is made in the same direction and if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction is made. By increasing the vertical eye opening of the signal the signal-to-noise ratio of the received signal is improved.

Abstract: A delay controller includes an acquiring section that acquires synchronization timings indicating timings when a plurality of controllers, which control via a line a plurality of transmitters that transmit data, synchronously control the transmitters, a determining section that determines a reference synchronization timing serving as a reference for synchronization between the controllers, on the basis of the synchronization timings acquired by the acquiring section, and a synchronization information transmitting section that transmits synchronization information to the controllers, the synchronization information being used when the controllers receive data from each of the transmitters at the reference synchronization timing determined by the determining section.

Abstract: Provided is a transmission apparatus for a dynamic lane operation in a multi-lane based Ethernet system, including: a monitor to monitor whether at least one lane being used by the transmission apparatus is modified; an upper layer manager to transmit, to a Reconciliation Sublayer (RS) of the transmission apparatus, lane change information associated with the modified at least one lane; and an RS manager to transmit the lane change information to an RS of a reception apparatus corresponding to the RS of the transmission apparatus.

Abstract: A video transport system is provided for transporting as 8B/10B coded video stream across a 64B/66B coded link, wherein forward error correction is provided without the overhead of the prior art. The system also provides a system with the ability to recover 64B/66B Encoded blocks that have corrupt Sync bits.

Abstract: A communication system and method is disclosed that performs symbol boundary synchronization by generating a symbol alignment estimate from a partial signal correlation; and then refining the symbol alignment estimate via a carrier phase calculation. To generate the symbol alignment estimate, two methods are disclosed. After an estimate is determined, an embodiment provides for refining the symbol alignment estimate via a carrier phase calculation by determining a carrier phase of two adjacent carriers, determining a phase error as directly proportional to an offset from the start of a symbol, determining a phase difference contribution due to a communication channel and device hardware, and counter-rotating the determined carrier phase by an angle of a constellation point at a transmitter.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A method and apparatus for timing an output signal based on timing of an input signal is provided. A method includes determining a first clock rate derived from the input signal during a first time interval measured by a reference clock. The method also includes signal processing logic to determine a second clock rate during a second time interval based on an error signal that is calculated as a difference between the first clock rate multiplied by the second time interval and a previous value of the second clock rate multiplied by the first time interval.

Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

Abstract: A device under test (DUT) is tested by: receiving a signal transmitted by the DUT, wherein the signal includes first portions that include scrambled bits produced from a selected bit pattern and a selected scrambling algorithm, and further includes second portions that include unscrambled bits, the first portions and second portions being interspersed within the signal; detecting received scrambled bits within the received signal; generating a test bit sequence using the selected scrambling algorithm and the selected bit pattern, including generating a bit of the test bit sequence for each of the received scrambled bits within the received signal, and not generating a bit of the test bit sequence for each of the received unscrambled bits within the received signal; and comparing the received scrambled bits to the test bit sequence to determine a bit error rate of the received signal.

Abstract: A method is provided for determining a measure of error of a device under test (DUT). The method includes storing baseband data received from the DUT in a storage device, segmenting the baseband data into multiple data segments, determining processing parameters for one data segment of the plurality of data segments, and storing the determined processing parameters for the one data segment. The method further includes retrieving additional data segments of the multiple data segments from the storage device, and processing the additional data segments using the stored processing parameters for the one data segment. The measure of error of the DUT is determined based at least in part on data from the processed additional data segments.

Abstract: A method for determining an overlap and add length estimate comprises determining a plurality of correlation values of a plurality of ordered frequency domain samples obtained from a data frame; comparing the correlation values of a first subset of the samples to a first predetermined threshold to determine a first edge sample; comparing the correlation values of a second subset of the samples to a second predetermined threshold to determine a second edge sample; using the first and second edge samples to determine an overlap and add length estimate; and providing the overlap and add length estimate to an overlap and add circuit.

Abstract: There is provided a radio receiver including: a first matched filter, a second matched filter, a first frame synchronization determining unit and a first phase determining unit. The first matched filter performs matching processing on the basis of N first tap coefficients and sign information of a received digital signal to obtain first output data. The second matched filter performs matching processing on the basis of M (M is a natural number smaller than the N) second tap coefficients, the sign information and amplitude information of the received digital to obtain second output data. The first frame synchronization determining unit determines a first frame synchronization timing of the received digital signal on the basis of the first output data. The first phase determining unit determines a first phase amount of the received digital signal on the basis of the second output data and the first frame synchronization timing.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc.

Abstract: A method for predicting performance of a radio link in a wireless communication terminal including hypothesizing a second codeword including information associated with a hypothesized first codeword, obtaining channel state information from a received signal, and estimating a decoder error rate of the first codeword under a condition that the second codeword may not be decoded correctly, wherein the decoder error rate is estimated using the channel state information.

Abstract: Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal.