Abstract: A method for operating a memory includes: performing an error check operation; detecting N bad sections during the error check operation, where N is an integer equal to or greater than 1; stopping the error check operation in response to the detecting of the N bad sections; transferring information on the N bad sections to a memory controller; and resuming the error check operation in response to the transferring of the information on the N bad sections to a memory controller.

Abstract: Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.

Abstract: An electronic price label system and a method for an electronic price label system include a product database in which products are listed. A new price of a product is sent to an electronic price label linked to the product. The received new price of a product is stored by the electronic price label. The electronic price label changes the displayed price to the received new price in response to receiving a price activation signal from the electronic price label system, e.g. from base station of the electronic price label system.

Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.

Abstract: Methods for a CoAP server to inform CoAP clients regarding a set of one or more communication protocols supported by the CoAP server. In one aspect, a CoAP client obtains information indicating a set of one or more communication protocols supported by the CoAP server and determines which of the set of one or more communication protocols to use to communicate with the CoAP server.

Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

Abstract: Vulnerabilities to physical memory, such as server dynamic random access memory (DRAM) with error correction code (ECC) capability, can be mitigated though the use of guard pages allocated in that physical memory. Physical memory pages can be mapped to virtual memory pages of a contiguous virtual address space. When an error such as a bit flip is detected in a physical memory page, the data from that physical memory page can be copied to a protected page, such as a guard page or page isolated from other sensitive data. Information such as an error correction code (ECC) can be used to determine and correct the erroneous bit. The mappings in a related page table can be updated such that the same virtual pages or addresses are then mapped to the guard page that now includes the relevant data.

Abstract: A memory controller may include: a weight management unit configured to store a weight based on a read disturb strength of each of the plurality of word lines of the plurality of memory blocks; a counter configured to increase a read count of a management group that includes a target word line, based on the weight of the target word line obtained from the weight management unit, the counter configured to increase the read count in response to the controller receiving a read request for the target word line from an external host device; and a verification operation determination unit configured to determine whether to perform or to not perform a word line verification operation based on a comparison of a reference interval count with the read count of the management group that includes the target word line.

Abstract: According to an embodiment, an operation method of a terminal in a wireless communication system comprises the steps of: generating a first waveform from a signal related to a physical sidelink control channel (PSCCH) and generating a second waveform from a signal related to a physical sidelink shared channel (PSSCH); generating a third waveform on the basis of a peak to average power ratio (PAPR) and a constellation shift and transmitting the second waveform and the third waveform, wherein the constellation shift is applied only to the first waveform.

Abstract: Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

Abstract: A method includes moving one or more transmit facility or transmit facilities attached to a first component with regard to at least two receive facilities attached at a fixed position to the second component; and at least one of registering a respective error if an error condition exists for the respective receive facility or modifying an operation of an apparatus comprising the first and a second component if the error condition exists for the respective receive facility, the error condition for the respective receive facility depends on location information relating to at least one of the position of the first component with regard to the second component or orientation of the first component with regard to the second component, and/or at least one of a measure for a receive quality of the signals or data packets received from the transmit facility or from at least one of the transmit facilities.

Abstract: Techniques for injecting memory read errors may include obtaining an error injection profile from a test library. A defense level in the defense hierarchy can be selected for execution according to the probabilities in the error injection profile. One or more errors can be injected into read operations of the storage device according to the defense-level read retry vector of the selected defense level, and a defense algorithm of the selected defense level is executed to recover read data of the read operations.

Abstract: Systems and methods are described that estimates a remaining useful life (RUL) of an electronic device. Time-series signals gathered from sensors in the electronic device are received. Statistical changes are detected in the set of time-series signals that are deemed as anomalous signal patterns. Anomaly alarms are generated, wherein an anomaly alarm is generated for each of the anomalous signal patterns. An irrelevance filter is applied to the set of anomaly alarms to produce filtered anomaly alarms, wherein the irrelevance filter removes anomaly alarms associated with anomalous signal patterns that are not correlated with previous failures of similar electronic devices. A logistic-regression model is used to compute an RUL-based risk index for the electronic device based on the filtered anomaly alarms. When the risk index exceeds a risk-index threshold, a notification is generated indicating that the electronic device has a limited remaining useful life.

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

Abstract: In one embodiment, a system for allocating clients between radios of an access point is disclosed. The system includes a first antenna coupled to a first radio, a second antenna coupled to a second radio, and a monitoring radio coupled to the first antenna and second antenna. The system includes computer-readable instructions that cause the system to receive at the monitoring radio, a first client attribute from each of a plurality of first client devices, and a second client attribute from each of a plurality of second client devices, and provide each aforementioned attribute to an optimization function. The system determines, with the optimization function, that one of the first radio and second radio will optimize performance for at least one device of the plurality of first client devices and second client devices and steer the at least one device accordingly.

Abstract: Provided are method and apparatus for processing data packets, a device, and a storage medium that relate to the field of communications. The method includes: receiving multiple data packets of an identical service transmitted in multiple frequency bands, where each of the data packets carries arrangement indication information; and sorting the data packets based on the arrangement indication information carried in each of the data packets.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive a scaling factor and a retention time power law coefficient associated with a solid state drive (SSD); determine a first raw bit error rate (RBER) value for the SSD at a first time; extrapolate a second time at which a second RBER value for the SSD would reach a maximum RBER value if left unpowered, based at least on the first raw bit error rate value, the scaling factor, and the retention time power law coefficient; and provide the second time at which the second RBER value for the SSD would reach the maximum raw bit error rate value if left unpowered to at least one of an information handling system (IHS), IHS firmware, a baseboard management controller of the IHS, and an application executing on the IHS.

Abstract: Methods, systems, and devices for wireless communications are described. Some wireless communications systems may support communications. For example, a wireless communications system may support New Radio (NR) cellular-vehicle to everything (C-V2X) communication. In some examples, a user equipment (UE) may receive a sidelink control channel for a sidelink transmission on a first set of symbols of a time slot (e.g., the first two or three symbols of a time slot). The UE may decode the sidelink control channel and disable one or more radio frequency (RF) components associated with processing the sidelink transmission on a second set of symbols of the time slot based on decoding the sidelink control channel. For example, the UE may disable one or more RF components if the UE determines the sidelink control channel is decoded unsuccessfully.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: A method for optimizing a Polar-RNNA quantizer of MLC NAND flash based on deep learning comprises the following steps: Step S1: transforming an MLC flash detection task into a deep learning task, and obtaining three hard-decision read thresholds based on a neural network; Step S2: expanding six soft-decision read thresholds based on the three hard-decision read thresholds; Step S3: constructing an LLR mapping table, and obtaining new LLR information of MLC flash based on the LLR mapping table; Step S4: symmetrizing an MLC flash channel, and performing density evolution; and Step S5: optimizing the soft-decision read thresholds based on a genetic algorithm to obtain an optimal quantization interval. According to the invention, polar codes can be directly used for MLC flash channels without the arduous work of MLC flash channel modeling, so that the reliability of MLC flash is effectively improved.

Abstract: The meta data containing count and key fields of CKD records are reversibly decoupled from the user data of the data field so that the data can be deduplicated. Multiple CKD records may be coalesced into a larger size CKD track. The coalesced meta data is compressed and stored in a CKD hash table. The user data is hashed, and the hash is used as a hash key that is associated with the compressed meta data in the CKD hash table. When the hash of user data associated with a CKD write IO matches the hash key of an existing entry in the table, data duplication is indicated. The compressed meta data is added to the entry and the user data is deduplicated by creating storage system meta data that points to the pre-existing copy of the user data. The storage system metadata includes unique information that enables the corresponding compressed metadata to be subsequently located in the hash table to reassemble the CKD records.

Abstract: Visual safety is ensured when image switching takes place. When an image is switched by nonlinear reproduction, a display property is kept switched, during a transition display period, to a transition display property with a brightness level kept lower than a normal level, on the basis of pixel statistical information regarding the image. For example, an electro-optic conversion property is controlled to a transition property or the brightness level of a backlight is suppressed.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for failure handling. This failure handling method includes determining a sector set failure type associated with at least one failed sector set of a disk; if the sector set failure type indicates that the number of failed sector sets in the at least one failed sector set is greater than a first threshold number, generating an instruction for replacing the disk; and otherwise performing at least one of the following: migrating data from a failed sector set in which the number of failed sectors is greater than a second threshold number to a spare sector set, and performing a failure recovery for a failed sector set in which the number of failed sectors is less than or equal to the second threshold number.

Abstract: A method for implementing an out-of-band communication channel in a coherent optical access network includes steps (a)-(e). Step (a) includes separating a MAC-layer signal received from a media access control (MAC) layer into an initial communication-channel signal and an initial data-channel signal. Step (b) includes encoding, using a first signal-coding scheme within a transceiver of a coherent passive optical network (PON), the initial communication-channel signal into a communication-channel signal occupying a first frequency band. Step (c) includes encoding, using a second signal-coding scheme within the transceiver, the initial data-channel signal into a data-channel signal occupying a second frequency band not overlapping the first frequency band. Step (d) includes combining the communication-channel signal and the data-channel signal to yield an analog signal.

Abstract: This application describes a link bit error-based processing method and apparatus. A network device may report, to a controller, a bit error rate at which an egress port on the network device is configured to send data traffic. In this way, the controller may collect and accumulate bit error rates at which data traffic is sent through all egress ports on a transmission path, to obtain an accumulated bit error rate of the transmission path. In this way, the controller may determine, based on the accumulated bit error rate of the transmission path, whether to switch a service flow on the transmission path to another transmission path. Therefore, the controller may switch a service flow transmitted on a transmission path with an excessively high accumulated bit error rate to another transmission path with a relatively low accumulated bit error rate for transmission.

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: A Hyper-Converged Infrastructure (HCl) system that includes a plurality of HCl log generating components and an HCl storage system that provides at least a portion of a log database. The HCl system receives a request from a management system to store a first log bundle of the plurality of HCl log generating components and determines the at least one second log bundle that is stored in the log database is at least a size threshold. The HCl system performs a log database clean operation on the at least one second log bundle and determines that the log database clean operation on the at least one second log bundle has provided an available storage capacity in the log database that is sufficient to store the first log bundle. The HCl system then stores the first log bundle in the log database.

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

Abstract: Some embodiments of this disclosure include apparatuses and methods for a media access control (MAC) level operation that enables a transmitter and a receiver to select low-density parity check (LDPC) codewords that are HARQ retransmitted. The operations described herein provide for reducing the number of codewords that need to be retransmitted, minimizing the overhead needed to signal the feedback from a receiver to a transmitter, and allowing a transmitter to control which codewords are retransmitted.

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

Abstract: Systems and methods are provided for error correction in network data transfers. In some cases, such systems and methods include selection of a ratio of error correction to user data based upon determined communication channel health.

Abstract: The present invention relates to a data transmission control method, an information sending end and receiving end, and an aerial vehicle image transmission system. The data transmission control method includes: receiving data frames sent by a sending end, the data frames being sequentially sent by the sending end in an order of a data frame sequence; and returning an acknowledgement signal corresponding to a currently-received data frame N to the sending end, to enable the information sending end to determine a current network status according to the acknowledgement signal, and adjusting data encoding quality of the sent data frame based on the current network status. In the method, delays for image quality and transmission speed to recover when a network status recovers can be effectively reduced by rapidly determining a current network status based on the feedback of an acknowledgement signal.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: A method for application operational monitoring may include an operational monitoring computer program: (1) ingesting a plurality of service level indicator (SLI) metrics for an application, each SLI metric identifying a number of successful observations and a number of total observations; (2) calculating a SLI score for each SLI metric based on the number of successful observations and the number of total observations for the SLI metric; (3) weighting the SLI score for each SLI metric; (4) combining the weighted SLI scores into an application SLI score; (5) calculating a calculated error budget based on the application SLI score; (6) determining that the calculated error budget exceeds an error budget for the application; (7) generating a notification in response to the calculated error budget breaching the error budget; and (8) causing implementation of a restriction on the application, wherein the restriction prevents enhancements to the application.

Abstract: A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.

Abstract: An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.