Abstract: A method for optimizing a Polar-RNNA quantizer of MLC NAND flash based on deep learning comprises the following steps: Step S1: transforming an MLC flash detection task into a deep learning task, and obtaining three hard-decision read thresholds based on a neural network; Step S2: expanding six soft-decision read thresholds based on the three hard-decision read thresholds; Step S3: constructing an LLR mapping table, and obtaining new LLR information of MLC flash based on the LLR mapping table; Step S4: symmetrizing an MLC flash channel, and performing density evolution; and Step S5: optimizing the soft-decision read thresholds based on a genetic algorithm to obtain an optimal quantization interval. According to the invention, polar codes can be directly used for MLC flash channels without the arduous work of MLC flash channel modeling, so that the reliability of MLC flash is effectively improved.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: The meta data containing count and key fields of CKD records are reversibly decoupled from the user data of the data field so that the data can be deduplicated. Multiple CKD records may be coalesced into a larger size CKD track. The coalesced meta data is compressed and stored in a CKD hash table. The user data is hashed, and the hash is used as a hash key that is associated with the compressed meta data in the CKD hash table. When the hash of user data associated with a CKD write IO matches the hash key of an existing entry in the table, data duplication is indicated. The compressed meta data is added to the entry and the user data is deduplicated by creating storage system meta data that points to the pre-existing copy of the user data. The storage system metadata includes unique information that enables the corresponding compressed metadata to be subsequently located in the hash table to reassemble the CKD records.

Abstract: Visual safety is ensured when image switching takes place. When an image is switched by nonlinear reproduction, a display property is kept switched, during a transition display period, to a transition display property with a brightness level kept lower than a normal level, on the basis of pixel statistical information regarding the image. For example, an electro-optic conversion property is controlled to a transition property or the brightness level of a backlight is suppressed.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable storage media for monitoring application health via correctable errors. The method includes identifying, by a network device, a network packet associated with an application and detecting an error associated with the network packet. In response to detecting the error, the network device increments a counter associated with the application, determines an application score based at least in part on the counter, and telemeters the application score to a controller. The controller can generate a graphical interface based at least in part on the application score and a timestamp associated with the application score, wherein the graphical interface depicts a trend in correctable errors experienced by the application over a network.

Abstract: A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for failure handling. This failure handling method includes determining a sector set failure type associated with at least one failed sector set of a disk; if the sector set failure type indicates that the number of failed sector sets in the at least one failed sector set is greater than a first threshold number, generating an instruction for replacing the disk; and otherwise performing at least one of the following: migrating data from a failed sector set in which the number of failed sectors is greater than a second threshold number to a spare sector set, and performing a failure recovery for a failed sector set in which the number of failed sectors is less than or equal to the second threshold number.

Abstract: A method for implementing an out-of-band communication channel in a coherent optical access network includes steps (a)-(e). Step (a) includes separating a MAC-layer signal received from a media access control (MAC) layer into an initial communication-channel signal and an initial data-channel signal. Step (b) includes encoding, using a first signal-coding scheme within a transceiver of a coherent passive optical network (PON), the initial communication-channel signal into a communication-channel signal occupying a first frequency band. Step (c) includes encoding, using a second signal-coding scheme within the transceiver, the initial data-channel signal into a data-channel signal occupying a second frequency band not overlapping the first frequency band. Step (d) includes combining the communication-channel signal and the data-channel signal to yield an analog signal.

Abstract: This application describes a link bit error-based processing method and apparatus. A network device may report, to a controller, a bit error rate at which an egress port on the network device is configured to send data traffic. In this way, the controller may collect and accumulate bit error rates at which data traffic is sent through all egress ports on a transmission path, to obtain an accumulated bit error rate of the transmission path. In this way, the controller may determine, based on the accumulated bit error rate of the transmission path, whether to switch a service flow on the transmission path to another transmission path. Therefore, the controller may switch a service flow transmitted on a transmission path with an excessively high accumulated bit error rate to another transmission path with a relatively low accumulated bit error rate for transmission.

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including a plurality of memory blocks, the memory device being configured to output voltage information indicating whether an unstable state of an input voltage has occurred, the input voltage being provided to the memory device from an external power source, and a memory controller configured to store a read count indicating a number of times that one or more read operations are performed on each of the plurality of memory blocks and to control the memory device to move data stored in a first memory block for which the read count exceeds a threshold count to a second memory block, and configured to adjust the threshold count based on the voltage information.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: A Hyper-Converged Infrastructure (HCl) system that includes a plurality of HCl log generating components and an HCl storage system that provides at least a portion of a log database. The HCl system receives a request from a management system to store a first log bundle of the plurality of HCl log generating components and determines the at least one second log bundle that is stored in the log database is at least a size threshold. The HCl system performs a log database clean operation on the at least one second log bundle and determines that the log database clean operation on the at least one second log bundle has provided an available storage capacity in the log database that is sufficient to store the first log bundle. The HCl system then stores the first log bundle in the log database.

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

Abstract: Some embodiments of this disclosure include apparatuses and methods for a media access control (MAC) level operation that enables a transmitter and a receiver to select low-density parity check (LDPC) codewords that are HARQ retransmitted. The operations described herein provide for reducing the number of codewords that need to be retransmitted, minimizing the overhead needed to signal the feedback from a receiver to a transmitter, and allowing a transmitter to control which codewords are retransmitted.

Abstract: Methods, systems, and devices for managing information protection schemes in memory systems are described. A memory device may dynamically select an information protection scheme from a set of information protection schemes. In some examples, the memory device may identify a quantity of defective blocks in each plane associated with a control. The memory device may then identify a quantity of planes that satisfy a block threshold. In some cases, the memory device may select an information protection scheme using the quantity of planes. The information protection scheme may be an example of a redundant array of independent nodes scheme, and may indicate a quantity of planes used in performing a protected write operation.

Abstract: Systems and methods are provided for error correction in network data transfers. In some cases, such systems and methods include selection of a ratio of error correction to user data based upon determined communication channel health.

Abstract: The present invention relates to a data transmission control method, an information sending end and receiving end, and an aerial vehicle image transmission system. The data transmission control method includes: receiving data frames sent by a sending end, the data frames being sequentially sent by the sending end in an order of a data frame sequence; and returning an acknowledgement signal corresponding to a currently-received data frame N to the sending end, to enable the information sending end to determine a current network status according to the acknowledgement signal, and adjusting data encoding quality of the sent data frame based on the current network status. In the method, delays for image quality and transmission speed to recover when a network status recovers can be effectively reduced by rapidly determining a current network status based on the feedback of an acknowledgement signal.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: A digitally-controlled oscillator (DCO) circuit includes a digital-to-analog converter (DAC) to generate a first current based on most significant bits of a multi-bit code received from a time-to-digital converter (TDC) of a digital phase-locked loop (PLL). The DCO circuit further includes a sigma-delta modulator (SDM) to modulate least significant bits of the multi-bit code into a set of digital bits based on a first frequency of a feedback clock of the DPLL. The set of digital bits is to cause the DAC to generate a second current. The DCO circuit further includes a ring oscillator coupled to the DAC, the ring oscillator to generate an alternating-current (AC) output signal having a second frequency corresponding to a combination of the first current and the second current.

Abstract: A method for application operational monitoring may include an operational monitoring computer program: (1) ingesting a plurality of service level indicator (SLI) metrics for an application, each SLI metric identifying a number of successful observations and a number of total observations; (2) calculating a SLI score for each SLI metric based on the number of successful observations and the number of total observations for the SLI metric; (3) weighting the SLI score for each SLI metric; (4) combining the weighted SLI scores into an application SLI score; (5) calculating a calculated error budget based on the application SLI score; (6) determining that the calculated error budget exceeds an error budget for the application; (7) generating a notification in response to the calculated error budget breaching the error budget; and (8) causing implementation of a restriction on the application, wherein the restriction prevents enhancements to the application.

Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.

Abstract: An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.

Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a codeword of the memory: obtaining at least three read values of the codeword; calculating a signal counts metric value from the at least three reads; computing an optimal reference voltage offset from the signal counts metric and a correlation between optimal reference voltage offsets and a signal counts metric associated with the memory; determining a new center read reference voltage based on a current center reference voltage and the optimal reference voltage offset and performing at least one subsequent read of the codeword following the decoding failure utilizing the new center read reference voltage.

Abstract: Techniques for estimating raw bit error rate of data stored in a group of memory cells are described. Encoded data is read from a group of memory cells. A first population value is obtained based on a first number of memory cells in the group of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. An estimated raw bit error rate of the data is determined to satisfy a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. A first media management operation is initiated in response to the determination that the estimated raw bit error rate satisfies the first threshold.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.

Abstract: An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting unit for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search unit for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control unit for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.

Abstract: A memory device to perform a read disturb scan of unprogrammed memory cells. In one approach, a test read is performed on unprogrammed memory cells in a first memory block of a storage media (e.g., NAND flash) to provide a test result. Based on the test result, a portion of the unprogrammed cells for which a threshold voltage is above a predetermined voltage is determined. A determination is made whether the portion of the unprogrammed memory cells exceeds a predetermined limit. In response to determining that the portion exceeds the predetermined limit, data is moved from the first memory block to a second memory block of the storage media.

Abstract: One embodiment described herein provides a system for distributed fiber sensing. The system can include a plurality of network elements (NEs) in an optical transport network (OTN) and a control-and-management module coupled to the NEs. A respective network element (NE) can include a first wavelength coupler configured to separate an optical supervisory channel (OSC) signal from a data-carrying signal received from a fiber span, a polarization-measurement unit configured to perform a polarization measurement on the OSC signal, and a transmitter configured to transmit an outcome of the polarization measurement to the control-and-management module, thereby facilitating distributed fiber sensing based on the outcome of the polarization measurement.

Abstract: The disclosed systems and methods for improving a launch power in an optical link. The improvement of launch power in the optical link is based on: i) selecting an optical span from one or more optical spans within the optical link; ii) applying a power dither to a plurality of the optical signals propagating in the selected optical span; iii) selecting an optical signal from the plurality of the optical signals to which the power dither is applied; iv) correlating the power dither with a performance parameter of the selected optical signal; and v) based on the correlation, adjusting the launch power of a first optical amplifier in the selected optical span to minimize the correlation to approximately equal to zero.

Abstract: A lossy counter counts distinct network data items. The lossy counter includes a count sketch bounded by a predetermined value to limit the number of distinct network data items included in the count sketch. The count sketch may include counts for a set of distinct network data items. The lossy counter has an associated time interval, and the first set of distinct network data items and the second set of distinct data items include timestamps that coincide with the time interval associated with the lossy counter.

Abstract: In one embodiment, a method includes applying Forward Error Correction (FEC) to data at power sourcing equipment, transmitting the data and pulse power over a wire pair to a powered device, identifying data transmitted during power transitions between a pulse power on time and a pulse power off time in the pulse power at the powered device, and applying FEC decoding to at least a portion of the data based on said identified power transitions.

Abstract: An integrity check device includes a register array processing circuitry which generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on a plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.

Abstract: An electronic circuit comprising an SRAM memory, a control unit, an error detection and correction module and a scrubbing module. The electronic circuit further comprises an integrated SEU monitor of the SRAM memory. The SEU monitor does not use standalone or specialized SRAM memories or particle detectors. Rather, the same SRAM memory that is used for the main operation as a storage element of the electronic circuit serves simultaneously as detector for the SEU monitor. The proposed SEU monitor enables real-time monitoring of the SEU rate in order to detect early the high radiation levels and apply appropriate hardening measures. Furthermore, a method for monitoring an SEU rate and determining permanent faults in an electronic circuit is suggested.

Abstract: A time code display system comprising: a video receiver configured for receiving a plurality of non-homologous video signals; a time code parser connected with the video receiver and configured for extracting time code data of each video frame from each video signal; a write controller and a buffer, the write controller being connected with the video receiver and the time code parser; a synchronous clock component configured for generating a local clock signal according to a channel associated clock signal of any video signal; and a read controller and a display, the read controller being connected with the synchronous clock component and the buffer and configured for reading out the video frame of each video signal and the time code data corresponding to the video frame from the buffer at the same time, according to the local clock signal.

Abstract: A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.

Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

Abstract: To locate an intermittent fault in a communication structure of an aircraft comprising pieces of equipment that are interconnected by cabling forming a plurality of communication media that are shared, an analyzer retrieves an error report relating to transmission errors observed on each of said communication media, performs a count of the transmission errors, per type of error and per communication chain, computes a median of the counts for communication chains comprising the same pair of wired pieces of equipment, and when, for a communication chain, the count exceeds a threshold equal to the median plus a predefined margin, generates an alarm indicating detection of an intermittent fault in association with the communication chain that led the threshold to be exceeded. Thus, intermittent faults are easily located and repaired.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store XOR parity data in a host memory buffer (HMB) of a host device, monitor a health of the memory device, determine that a threshold corresponding to the health of one or more blocks of the memory device has been reached or exceeded, and copy the XOR parity data from the HMB to the memory device. The controller is further configured to receive a low power mode indication from the host device and enter the low power mode after copying the XOR parity data from the HMB to the memory device. The controller is further configured to correct read failures using the XOR parity data retrieved from the HMB.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: According to one implementation, an automated audio mapping system includes a computing platform having a hardware processor and a system memory storing an audio mapping software code including an artificial neural network (ANN) trained to identify multiple different audio content types. The hardware processor is configured to execute the audio mapping software code to receive content including multiple audio tracks, and to identify, without using the ANN, a first music track and a second music track of the multiple audio tracks. The hardware processor is further configured to execute the audio mapping software code to identify, using the ANN, the audio content type of each of the multiple audio tracks except the first music track and the second music track, and to output a mapped content file including the multiple audio tracks each assigned to a respective one predetermined audio channel based on its identified audio content type.

Abstract: To speed up a firmware update process, a gateway performs an expedited topological discovery of networked nodes. The gateway maintains a list of unlinked network nodes that are not known to share good edges with other nodes. The gateway transmits a topology query to a selected unlinked node, which the node retransmits to its neighboring nodes. Each neighboring node responds to the gateway with a link status of the edge between the queried node and the neighbor. The queried node and each neighboring node with an edge of sufficient link quality are removed from the list of unlinked nodes. The process is repeated until no networked nodes remain in the list of unlinked nodes. The gateway then sends a firmware update to nodes that will in turn retransmit the update over identified good edges.

Abstract: An electronic apparatus is provided.

Abstract: A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process.