Error Count Or Rate Patents (Class 714/704)
  • Patent number: 10375190
    Abstract: A non-transitory computer readable medium storing a program causing a computer to execute a process, the process including: selecting in a case where an error occurs in communication between a communication device and a communication target device, a setting item to be changed in order to handle the occurred error by referring to information in which a type of an error is previously correlated with a setting item to be changed; acquiring a setting value of another communication device regarding the selected setting item; and determining a setting value of the communication device based on the acquired setting value of the other communication device.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 6, 2019
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Tatsuyuki Tanaka
  • Patent number: 10360100
    Abstract: A cache memory system has a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC for correcting an error of the data in the first region, an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC, error rate determination circuitry which determines an error rate of the data in the first region, and region size adjustment circuitry which adjusts a size of the second region inside the nonvolatile memory based on the error rate.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 23, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10346232
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of: garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 9, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Arthur Shulkin, David Rozman, Tomer Eliash
  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Patent number: 10313207
    Abstract: A method for testing a cloud streaming server, and an apparatus and a system therefor are disclosed. Test result videos are created by receiving, from cloud streaming servers, test results corresponding to the key input of a preset test script; masked videos are created by masking the test result videos; and it is determined whether at least any one of the cloud streaming servers has a failure by mutually comparing test result images created by capturing the masked videos.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 4, 2019
    Assignee: SK TECHX CO., LTD.
    Inventors: Tae-Meon Bae, Hyun-Sik Na, Hong-Seo Yun, Jung-Keun Yang, Jong-Hyun Kim
  • Patent number: 10296406
    Abstract: A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies one or more bit errors. The system may determine whether an estimated bit error rate (BER) for the bit stream is likely to satisfy a threshold. The system may select an approach for determining the estimated BER for the bit stream. The estimated BER may be determined based on combining the current bit error count with a quantity of bits received in the time interval when the estimated BER is likely to exceed the threshold, and the estimated BER may be determined based on the current bit error count and one or more past bit error counts when the estimated BER is unlikely to exceed the threshold. The system may determine the estimated BER.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 21, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: John D. Johnson, Tapan Kumar Chauhan
  • Patent number: 10284424
    Abstract: A non-transitory computer readable medium stores a program causing a computer to execute a process for communicating. The process includes: when a connection error with a communication target device occurs, querying by transmitting equipment information acquired from the communication target device to a communication management server that manages information related to connection availability with the communication target device and procedures for connection errors; and displaying a connection availability with the communication target device or a procedure for the connection error, according to a result of the querying.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 7, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Kazutaka Saitoh
  • Patent number: 10284328
    Abstract: According to an example, motion-aware MCS adaptation may include determining whether a device is static relative to a wireless AP, moving towards the wireless AP, or moving away from the wireless AP. A device static rate probing interval, a device moving rate probing interval, first and second frame retransmission limits, a device static PER smoothing factor, and a device moving PER smoothing factor may be determined. In response to a determination that the device is static relative to the wireless AP, moving towards the wireless AP, or moving away from the wireless AP, an appropriate rate probing interval, an appropriate frame retransmission limit, and an appropriate PER smoothing factor may be used to determine a MCS value from a plurality of available MCS values to be used for transmitting data between the device and the wireless AP.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 7, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Souvik Sen, Li Sun
  • Patent number: 10268541
    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-hyung Song, Jangseok Choi
  • Patent number: 10263645
    Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 16, 2019
    Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei Uni
    Inventors: Seong-Ook Jung, Sara Choi, Byung Kyu Song, Taehui Na, Jisu Kim, Jung Pill Kim, Sungryul Kim, Taehyun Kim, Seung Hyuk Kang
  • Patent number: 10255121
    Abstract: An event clearinghouse engine is used with a data storage system to modify event disposition associated with components. A separate component disposition table is provided for each component. The component disposition table specifies different sets of disposition modifications for different types of events as indicated by event ID. A global disposition rule mapping table includes disposition modifications which are applied to all events. Per-vendor and per-tenant tables may be used to specify disposition modifications for particular vendors and tenants. Mode-specific tables such as a rescue/recovery mode table may be used to specify disposition modifications when the storage system is in a particular mode. The tables may be implemented in stages, including parallel and serial application.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 9, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ping He, Joseph Gugliemino, Hwai-Yeng Chan, Wai C. Yim
  • Patent number: 10223414
    Abstract: An electronic device is provided. The electronic device includes a memory in which contact information is stored, a communication circuit configured to receive at least one piece of contact information from the outside, and a processor configured to unify language scripts between a name of the stored contact information and a name of the received contact information and determine whether to integrate the stored contact information and the received contact information by comparing the name of the stored contact information with the name of the received contact information in a unified language script.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gene Wook Song, Byung Joon Jeon
  • Patent number: 10216595
    Abstract: Even when a main board is replaced, if no change is made to a connected storage unit, existent mirroring information is obtained to resume mirroring function processing. An information processing apparatus that performs mirroring to store same data in a plurality of storage units includes a first storage unit configured to store mirroring information indicating a state of the mirroring in a memory of a main board, a second storage unit configured to store the mirroring information in a memory of a sub board, a detection unit configured to detect replacement of the main board, and a restoration unit configured to restore the mirroring information stored in the memory of the sub board by the second storage unit in a memory of a replaced main board in accordance with detection of the replacement of the main board by the detection unit.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: February 26, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Akihiro Matsumoto
  • Patent number: 10198217
    Abstract: A last written page in an open block in NAND flash is identified where the NAND flash includes a plurality of pages and the last written page has first content. Second content is written to an adjacent page in the open block, wherein the adjacent page is physically adjacent to the last written page in the open block and the second content enhances robustness of the first content.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: February 5, 2019
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10181928
    Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: January 15, 2019
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Ju Cho, Ji Hun Cha
  • Patent number: 10177791
    Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 8, 2019
    Assignee: Seagate Technology LLC
    Inventors: Deepak Sridhara, Ara Patapoutian
  • Patent number: 10140180
    Abstract: Systems and methods are disclosed for performing segment-based outer code recovery at a data storage device. An apparatus may comprise a circuit configured to disable outer code error recovery, and perform a read operation spanning a plurality of segments of a data storage medium, a segment including a plurality of sectors. The circuit may identify one or more segments from the plurality of segments that have one or more sectors with an error. For an identified segment of the one or more segments, the circuit may perform a re-read operation with outer code error recovery enabled, and perform outer code recovery on sectors with an error within the identified segment.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Seagate Technology LLC
    Inventors: Deepak Sridhara, Ara Patapoutian, Prafulla B Reddy
  • Patent number: 10084487
    Abstract: One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ming Jin, Dennis P. O'Connor
  • Patent number: 10085261
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi Gigabit (EDMG) support indication. For example, a wireless station may be configured to generate a frame having a structure compatible with a Directional Multi Gigabit (DMG) frame structure, the frame including an EDMG supported field to indicate that the wireless station supports one or more EDMG features; and to transmit the frame over a DMG channel.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 25, 2018
    Assignee: INTEL IP CORPORATION
    Inventors: Carlos Cordeiro, Solomon B. Trainin, Chittabrata Ghosh
  • Patent number: 10075283
    Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Soo Lee, Sung Jun Kim, Chae Ryung Kim, Dong Uk Park, Youn Woong Chung, Jung Myung Choi, Han Kyul Lim, Gyeong Han Cha
  • Patent number: 10067826
    Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Rabenalt, Ulrich Backhausen, Thomas Kern, Michael Goessel
  • Patent number: 10014059
    Abstract: According to one embodiment, a distribution of threshold voltages of a plurality of memory cells is acquired from a nonvolatile memory which includes the plurality of memory cells, a malfunction state occurring in the nonvolatile memory is identified based on a shape of the distribution, and a read voltage when data is read out of the nonvolatile memory is set to a voltage value corresponding to a type of the malfunction state.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: July 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuyoshi Atsumi
  • Patent number: 10015500
    Abstract: A method and an apparatus for performing a Superposition Coded Modulation (SCM) scheme in a broadcasting or communication system including a controller are provided. The method includes controlling an SCM coefficient by the controller. The SCM coefficient is controlled according to a channel capacity of each layer of one or more layers in which information included in a signal is encoded.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: July 3, 2018
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation
    Inventors: Seho Myung, Kyung-Joong Kim, Kyeong-Cheol Yang
  • Patent number: 10013207
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) begins by identifying an unrecoverable encoded data slice of a data segment stored in a set of DSN storage units, where a region of a data object includes a plurality of data segments, and where the plurality of data segments includes the data segment. The method continues by determining whether the data segment is recoverable. The method continues, when recoverable, by salvaging the region by indicating that the region has corruption, updating a directory and replacing the data segment with filler data, and when not recoverable, by not salvaging the region by indicating that the region has been eliminated.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Wesley B. Leggette
  • Patent number: 10009041
    Abstract: Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 26, 2018
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Hoyoung Tang
  • Patent number: 9967567
    Abstract: A method for enhancing image quality of compressed video stream, mirrored thorough wireless network using a compression scheme, between a source device and a sink device. The method includes identifying idle time in the compression scheme of video, where the image change is below a predefined threshold for pre-defined period of time, calculating color code corrections between an original source last image and a decoded last image, sending corrections from the source device to the sink device in real-time during identified idle time and performing an image correction at the sink device based on the received correction.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: May 8, 2018
    Assignee: SCREENOVATE TECHNOLOGIES LTD.
    Inventors: Joshua Glazer, Sagiv Philipp
  • Patent number: 9965202
    Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 8, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigekazu Kogita, Hirokazu So, Toshiyuki Honda
  • Patent number: 9961174
    Abstract: System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link. A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Xiang Li, Nakul Midha, Varun Radhakrishnan, Chulkyu Lee
  • Patent number: 9954555
    Abstract: A system including a wireless device configured to apply selective error correction coding to data content to produce first data and second data, wherein the first and the second data being error correction coded differently; maintain the first data and the second data in a non-volatile memory of the wireless device; receive an electromagnetic signal for powering the wireless device; and transmit the first data and the second data over a short-range wireless link. The system further includes an apparatus configured to transmit an electromagnetic signal for powering the wireless device; receive first and second data over a short-range wireless link, wherein the first data and the second data being error correction coded differently; and apply selective error correction decoding to the first data and the second data to produce data content.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 24, 2018
    Assignee: Provenance Asset Group LLC
    Inventor: Martti Voutilainen
  • Patent number: 9940457
    Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael B. Healy, Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Patent number: 9941907
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: configuring a default encoding rule for a first physical erasing unit which includes encoding data to be stored to the first physical erasing unit based on a default code rate; configuring a first encoding rule, for the first physical erasing unit according to error estimating information of the first physical erasing unit, which includes encoding data to be stored to a first-type physical programming unit and a second-type physical programming unit belonging to the first physical erasing unit based on a first code rate and a second code rate respectively, where a value of the first code rate is greater than a value of the default code rate, and a value of the second code rate is less than the value of the default code rate.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 10, 2018
    Assignee: EpoStar Electronics Corp.
    Inventor: Yu-Hua Hsiao
  • Patent number: 9904479
    Abstract: A method for extending period of data retention of a flash memory device and a device for the same are disclosed. In the present invention, the temperature of the flash memory device is detected by a temperature sensor. According to the temperature and P/E cycles of the flash memory device, a safe period is obtained for the data retention of the flash memory device. By refreshing each block of the flash memory device during the safe period, the data retention period is refreshed, and the data stored in the flash memory device can be prevented from bit error caused by exceeding data retention period or read disturb.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 27, 2018
    Assignee: INNODISK CORPORATION
    Inventors: Ming-Sheng Chen, Ting-Chiang Liu, Liang-Tsung Wang
  • Patent number: 9899092
    Abstract: A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 20, 2018
    Assignee: IP GEM GROUP, LLC
    Inventor: Rino Micheloni
  • Patent number: 9886342
    Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: February 6, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Yuri Ryabinin, Eran Banani, Yan Dumchin, Mark Naumenko, Alexander Mostovoy, Mark Fiterman
  • Patent number: 9852799
    Abstract: Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage differences in one or more storage characteristics for blocks of a non-volatile memory medium within one or more established limits. A block classification module is configured to group blocks of a non-volatile memory medium based on one or more other storage characteristics. A configuration parameter module is configured to use a configuration parameter for at least one group of blocks based on a grouping. A configuration parameter update module is configured to update a configuration parameter for at least one group in response to a change in one or more managed storage characteristics.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: December 26, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Peterson, Gary Janik, Jea Hyun
  • Patent number: 9844038
    Abstract: A method for link adaptation at a mobile station can include the steps of computing mutual information per coded bit (MIB) metrics on at least one sub-channel for one or more candidate modulation types. The method may average the MIB metrics over at least two sub-channels, generate feedback information including MIB metrics for the plurality of candidate modulation types, and transmit the feedback information to a base station.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: December 12, 2017
    Assignee: Google Technology Holdings LLC
    Inventors: Krishna Kamal Sayana, Xiangyang Zhuang
  • Patent number: 9830079
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 9817738
    Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Camille C. Raad, Richard P. Mangold, Theodros Yigzaw
  • Patent number: 9812166
    Abstract: A recording/reproducing device and a recording/reproducing method, which are capable of improving reliability of data while securing compatibility with a file format employed in a recording medium are provided. Provided is a reconstruction method of reproduction data acquired from a reproducing device that reproduces data from a recording medium in which the data is recorded, performs error correction using a second error correction code specified in a file format employed in the recording medium, and outputs reproduction data, and the reconstruction method of the reproduction data includes obtaining reproduction data from the reproducing device, reading a first error correction code different from the second error correction code from the reproduction data, and performing error correction on the reproduction data using the first error correction code and reconstructing user data.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 7, 2017
    Assignee: Hitachi-LG Data Storage, Inc.
    Inventors: Hisahiro Hayashi, Norimoto Ichikawa
  • Patent number: 9772790
    Abstract: In a method for controlling data stored in an Solid State Disk (SSD) of a data de-duplication system, a storage controller obtains stability information of a data block. The stability information comprises a reference count of the data block and a length of a period of time when the data block is stored in the SSD. The storage controller identifies a stability level of the data block according to the stability information, and sends the stability level of the data block to the SSD. The SSD moves the data block to a target block which corresponds to the stability level. Thereby, the SSD can store data blocks having a same stability level together.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 26, 2017
    Assignee: HUAWEI TECHNOLOGY CO., LTD.
    Inventors: Liming Wu, Bin Huang, Wan Zhao
  • Patent number: 9692402
    Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Gerald S. Pasdast, Todd A. Hinck, David M. Lee, Narasimha R. Lanka
  • Patent number: 9690640
    Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Ron Gabor, Deep K. Buch, Theodros Yigzaw, Stanislav Shwartsman
  • Patent number: 9684034
    Abstract: Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Teck Seng Eng, Michael Russell Uy Gonzales, Louie Que Hermosura
  • Patent number: 9661646
    Abstract: Techniques to train a personal area network component may include obtaining a packet error rate from a personal area network component. It may be determined that the packet error rate is greater than a packet error rate threshold after a time period. A reservation may be requested from a wide area network component based a first transmit pattern from the personal area network component. A second or adjusted transmit pattern from the wide area network component may be received. Personal area network signals may be transmitted based on the second transmit pattern. The time period may be adjusted based on a personal area network packet error rate of the second transmit pattern. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 23, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sherry S. Chen, Marta Martinez Tarradell
  • Patent number: 9652321
    Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Patent number: 9654141
    Abstract: Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 9647953
    Abstract: In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the processor or media access control (MAC) functionality of a network port. The logic is configured to negotiate a credit aging duration during initialization of a link between a receiving endpoint and a sending endpoint, the receiving and sending endpoints being connected in a network fabric. The link includes at least one virtual link. The logic is also configured to receive an amount of available flow credits from the receiving endpoint and transmit one or more packets to the receiving endpoint. The amount of available flow credits are used to determine a capacity to process packets at the receiving endpoint. The exchange of flow credits is performed on a per virtual link basis. Other systems, methods, and computer program products are presented according to more embodiments.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bhalachandra G. Banavalikar, Casimer M. DeCusatis, Mircea Gusat, Keshav G. Kamble, Renato J. Recio
  • Patent number: 9647690
    Abstract: Described are methods, systems, and apparatus, including computer program products for error correction coding and decoding procedures for data storage or transfer. A plurality of data blocks is received. A plurality of checksum blocks are generated by multiplying the plurality of data blocks by a coding matrix, where the coding matrix comprises values of at least one basic interpolation polynomial and the multiplying is according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks. The plurality of data blocks and the plurality of checksum blocks are stored in a data storage medium.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: May 9, 2017
    Assignee: Raidix Corporation
    Inventors: Aleksei Marov, Aleksei Uteshev
  • Patent number: 9626309
    Abstract: Controller and method for requesting arbitration of a queue. The controller comprises a coalescing engine for determining a number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied. The method comprises determining the number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 18, 2017
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventors: Bradley Burke, Keith Graham Shaw
  • Patent number: 9625524
    Abstract: Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Teck Seng Eng, Michael Russell Uy Gonzales, Louie Que Hermosura