Abstract: A method and apparatus for controlling the read clock signal rate of a First-In First-Out data memory is provided. A control signal for controlling the read clock signal rate is derived from an error signal, wherein the level of data contained in the FIFO is used to generate the error signal. The control signal includes an integral element, which comprises the error signal, scaled by a first paramater and integrated over time, and a proportional element, which comprises the error signal scaled by a second parameter. In accordance with the invention, at least one of the first and second scaling parameters is varied in accordance with the absolute error signal level. In a preferred embodiment, the or each parameter is varied as an exponential function of the absolute error signal level. This results in the bandwidth of the apparatus varying exponentially with the absolute error signal level.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: A beat-pattern based error concealment system and method which detects drum-like beat patterns of music signals on the encoder side of the system and embeds the beat information as data ancillary to a preceding audio data interval in the transmitted compressed bitstream. The embedded information is then used to perform an error concealment task on the decoder side of the system. The beat detector functions as part of an error concealment system in an audio decoding section used in audio information transfer and audio download-streaming system terminal devices such as mobile phones. The disclosed sender-based method improves error concealment performance while reducing decoder complexity.

Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.

Abstract: A system and method for the concealment of errors resulting from missing or corrupted data in the transmission of audio signals in compressed digital packet formats is disclosed. The system utilizes a circular FIFO buffer to store audio frames from the transmitted audio signal, and a beat detector, to identify the presence of beats in the audio signal. The error concealment method replaces erroneous audio frames with error-free audio frames by a process which takes into account the presence and location of the detected beats.

Abstract: A disk recording apparatus and method therefore including a boundary violation detector to determine whether a violation of a block boundary occurs on a disk by determining a phase difference between a block boundary signal and an encoding block synchronous signal.

Abstract: A bit error measuring device for modem device, comprises; a bit error measuring unit for measuring a bit error in an input signal from the modem device, a clock controlling unit for controlling an output of a clock signal on the basis of a control signal outputted from the modem device, and a test pattern transmitting unit for transmitting a test pattern signal by synchronizing with the clock signal when clock pulses of the clock signal are outputted from the clock controlling unit, and for stopping a transmission of the test pattern signal when the clock pulses of the clock signal are not outputted from the clock controlling unit.

Abstract: A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T0 through T(N−1), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T0 signal, and each vector referencing a test event also indicates a nominal time delay following the start of the test cycle at which the event is to occur by referencing one of the timing signals T0 through T(N−1). However whenever the tester receives an input trigger signal edge, it determines an offset between the most recent T0 signal edge and the occurrence of the trigger signal edge.

Abstract: A circuit comprising a receiver configured to receive a first signal having a first phase, a second signal having a second phase opposite the first phase and an output configured to present either the first or second signals. A state machine may be configured to receive the output of the receiver circuit and to provide a control signal configured to select the first or second signals.

Abstract: Data synchronization detection means 3 is provided between data identification means 1 and code demodulation means 6 of the data reproduction system, which performs data synchronization detection using the code-modulated data itself; a specified bit pattern generated in the data codeword is calculated in each phase (bit), using a specified bit sequence pattern that is not generated in a specified phase of the data codeword, by the conversion law during code modulation (or there is a specified bit sequence pattern that is generated only in a specified phase of the codeword); the positions of the data codeword partitions are thereby identified. Scrambling is then applied to the write data as required in order to ensure accurate synchronization detection. In addition, the data position is specified by detecting the pattern correlation between the PLO_SYNC section and GAP section.

Abstract: A computer system, program product and method utilize thread synchronization for debugging multi-threaded computer programs. Synchronization control points (“sync points”) are used to conditionally suspend or delay execution of a thread or threads depending on another thread or threads hitting the same or other sync points. A thread hitting a synchronization control point is suspended, reference is made to break point table to determine what synchronization condition must be triggered to release the thread, and if triggered, what delay, if any, will be imposed prior to release.

Abstract: A sampling system for estimating the bit error rate of a signal carried by a communication system is provided. The sampling system includes an optical transmission medium for carrying an optical signal. A clock regenerator circuit is connected to the optical transmission medium. The clock regenerator circuit receives the optical signal and generates a synchronous clock signal. A clock divider circuit receives the synchronous clock signal and produces a divided clock signal. A sampling circuit receives a divided clock signal and produces a digitized signal. A threshold determination circuit compares the digitized circuit to a predetermined threshold value. The threshold determination circuit also produces an indicator signal representing the logic value of the digitized signal. In order to estimate the bit error rate, a histogram processor receives the digitized signal and the indicator signal, and generates a histogram representing statistical information about the optical signal.

Abstract: The present invention allows the logic state of a clocked precharge (CP) logic gate to be tested when stopping or starting the logic gate's clock and comprises a plurality of clock signals with overlapping phases and a plurality of CP logic gates coupled in series. Each CP logic gate of the plurality of CP logic gates is coupled to an individual clock signal. The present invention further comprises one or more signal keeper devices coupled to certain individual CP logic gates in the critical path of the logic state. The signal keeper device allows the state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signal of an individual logic gate of said plurality of logic gates. The present invention is suitable for a variety of testing techniques that includes IDDQ, scan testing, and hardware emulation testing.

Abstract: A method and apparatus for resynchronizing a network manager to its agents. Each object instance of an agent in an object-oriented management scheme is assigned two special attributes, namely, DATASYNCH and UNIQUEID. UNIQUEID is a unique number assigned to each object instance. DATASYNCH essentially is a counter which is incremented each time a change occurs to an object instance. When resynchronization is necessary, the manager requests the UNIQUEID and DATASYNCH attributes from its agents and compares those values with the corresponding values stored in its database. With respect to any object instance which does not match in both its UNIQUEID and DATASYNCH attributes to the manager's database, the manager uploads those object instances from the agent's database and/or revises its database accordingly.

Abstract: A code synchronization decision circuit of Viterbi decoder including a trigger signal generator that produces a trigger signal every time a symbol counter counts a predetermined number of symbols defined externally. A second comparator compares, in response to the trigger signal, the number of errors of symbols counted by an error counter with a threshold value that is externally set, and supplies a masking signal generator with a synchronization signal or a slip signal in response of the compared result. The masking signal generator, in response to the signals, generates a masking signal for suspending the operation of the error counter and symbol counter for a time period, during which unsuitable codes will be supplied to the code synchronization decision circuit from a re-encoder of the Viterbi decoder as one of compared values for detecting symbol errors.

Abstract: A synchronizing circuit receives an external signal and yields an output that is synchronized with the system clock and operates at the frequency of the external signal. The signal output from the synchronizing circuit is fed into the clock-enable input of the storage element, and the system clock signal is fed into the clock input of the storage element. Because the clock-enable signal triggers the storage element, the storage element is driven at the external signal frequency. Clock skew is eliminated because the system clock used for the clock input to the storage element is skew-controlled.

Abstract: A method of transferring image data between an initiator device and a target device using a IEEE 1394 standard bus. The present invention combines management functions, command functions, and isochronous data transfer to achieve the transfer of image data. The present invention discovers a target configuration using IEEE 1394 reads of a target configuration read only memory space. As part of the management function, the present invention uses a modified asynchronous data transfer protocol to establish a connection between the initiator and the target. Next, the present invention uses command functions to begin a job to transfer image data over an isochronous channel. Also, the present invention uses asynchronous data transfer to exchange printer job language commands to end a job.

Abstract: A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract: A digital subscriber line communication system does not require the use of a plain old telephone service (POTS) splitter in the resident's home. Digital signal processing is utilized to adapt to varying subscriber line conditions coming from POTS telephone equipment. The digital subscriber line modem includes a control circuit that utilizes a Reed-Solomon decoder and a synchronization error generator. The Reed-Solomon decoder provides a frame error signal, and the synchronization error generator responds to the frame error signal to generate a synchronization error signal. The synchronization error generator is configured as a leaking integrator to provide the synchronization error signal in response to a relatively large number of frame error signals occurring in a period of time. A resynchronization operation is performed in the modem in response to the synchronization error signal.

Abstract: In FIG. 5, a plurality of signal sources 21.sub.1 to 21.sub.N each generate a carrier with different frequencies. A pulse signal generating portion 23 generates a pulse signal with the same period and time width as those of a horizontal synchronizing signal in NTSC system color television broadcasting. Delay devices 32.sub.1 to 32.sub.N delay timing of the pulse signal for a randomly predetermined delay amount. Level adjuster 52.sub.1 to 52.sub.N generate a modulating signal by adjusting each pulse base of the delayed pulse signal for a level within a range between 12.5% and 74.375% with respect to a pulse top. Modulators 42.sub.1 to 42.sub.N output a signal obtained by modulating the carrier with the modulating signal. A multiplex portion 24 multiplexes the modulated signals to output a resultant signal as a test signal. The error rate of a QAM signal is evaluated with the test signal.

Abstract: In a semiconductor integrated circuit device having a test circuit, the test time can be shortened and further the circuit activation ratio can be increased, while reducing the circuit scale. In the operation test mode, the counter circuit (10) is divided into the first counter circuit (10a) and the second counter circuit (10b) by use of the test circuit (20). Further, the same input count clock CK is inputted at the same time to both the first and second counter circuits (10a, 10b) in parallel. The normal operation of the counter circuit (10) can be discriminated by checking whether the output signal A of the first counter circuit (10a) matches the output signal B of the second counter circuit (10b) or not.