Abstract: A neural processor and method for assigning config ID for neural core included in the same are provided. The neural processor includes a core array comprising a first neural core, a second neural core, a first data line connecting the first neural core and the second neural core in series, and a config line connecting the first neural core and the second neural core in series, an ID config manager configured to assign a first config ID to the first neural core and a second config ID to the second neural core via the config line, and a memory configured to input and output data to and from the core array via the first data line.

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: A device and a method for executing a program, and a method for storing a program are described. The method of executing a program includes a sequence of instruction cycles, wherein each instruction cycle comprises: updating the program counter value; reading a data word from a memory location identified by the updated program counter value, wherein the data word comprises an instruction and a protection signature; determining a verification signature by applying a signature function associated with the program counter value to the instruction; executing the instruction if the verification signature and the protection signature are consistent with each other; and initiating an error action if they are inconsistent with each other. A method for storing a program on a data carrier is also described.

Abstract: A method of verifying a layout of a mask read only memory (ROM) includes: receiving source ROM code, bitmap data, and layout design data of the mask ROM; generating coordinate data of a bit determining unit based on the layout design data; and determining an error cell based on the coordinate data of the bit determining unit, the bitmap data, and the source ROM code.

Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

Abstract: A method automatically performs regression testing of output of an altered variable information print job (program). In one embodiment, the method begins by supplying test data to a variable information (VI) print job to produce first sample data. Next, the method applies a numeric generation application to the sample data to produce numerical representations. Then, the VI print job is altered and the same test data is supplied to the altered VI print job to produce second sample data. Again, the numeric generation application is applied to the second sample data to produce more of the numerical representations. The numerical representations are then compared to identify altered data records caused by the altering of the VI print job.

Abstract: Techniques for handling errors on memory modules are provided. An uncorrected error from a pair of memory modules may be received. Memory modules other than the pair of memory modules producing the error may be de-configured. Diagnostic tests may be run on the faded pair of memory modules. The memory module of the pair of memory modules that caused the uncorrected error may be determined.

Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.

Abstract: A memory system or flash card may include a controller. Improved testing and memory evaluation may be achieved by utilizing the memory's controller rather than an external tester. User defined test algorithms may be run from the controller to characterize, evaluate and test memory (e.g. NAND memory) or test other components, such as the controller itself.

Abstract: A test apparatus and method for testing a server are provided. The server includes a CPU group and a memory module. The test apparatus is electrically coupled to the CPU group and the memory module. The CPU group includes a number of CPUs, where each CPU is coupled to other CPUs through a plurality of QPI buses. The test apparatus includes a first copying control unit, a second copying control unit and a calculation unit. The first copying control unit controls each CPU to copy data stored in the memory module to a cache of the CPU and records the copying time duration. The second copying control unit controls each CPU to copy data stored in the memory module to caches of other CPUs and records the copying time duration. The calculation unit obtains copying speed according to the copying time duration.

Abstract: Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. Such systems and methods may include data pre-processing and detection to identify a media defect.

Abstract: A code checking method for a memory of a printed circuit board is disclosed, and is used to firstly add a check code to a data end of codes, after the codes is written in a memory, then use a timing controller to calculate a checksum of the data of the part of the primary codes and further compare the calculated checksum with the check code, and then output to a probe via a testing pin to display the result of comparison, so as to accomplish an object of checking if the written codes are correct. Thus, work efficiency of checking the codes written in the memory is enhanced.

Abstract: A method and system for managing storage of one or more data blocks in a programmable data storage device is provided. A data storage controller partitions each of multiple data blocks into multiple sub data blocks comprising a number of bits based on one or more index value descriptors. The data storage controller generates transition vectors from each of the sub data blocks by applying one or more transition functions. The data storage controller encodes one of the transition vectors for each sub data block for obtaining a residual sub data block comprising a reduced number of bits, thereby resulting in increased bit space. The data storage controller generates a composite data block by merging each residual sub data block. The composite data block is configurable for writing to one or more regions in the programmable data storage device free from a disturbance caused by write operations to other regions.

Abstract: A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result.

Abstract: An imaging apparatus includes: a plurality of photoelectric converters each adapted to perform photoelectric conversion in response to receiving light, and output an electrical signal; a holding unit adapted to hold, for each of the plurality of photoelectric converters, a correction value for correcting photoelectric conversion characteristics of the photoelectric converter; and a correction unit adapted to correct each of the electrical signals output by the plurality of photoelectric converters, using the corresponding correction values, wherein the correction unit corrects each of the electrical signals based on the correction values, which have been increased or decreased in accordance with a prescribed pixel arrangement pattern, and the imaging apparatus comprises a determination unit adapted to evaluate correction results that are based on the correction values increased or decreased in accordance with the prescribed pattern, and determine a presence of a correction error in the correction values held

Abstract: A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.

Abstract: A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Abstract: The present invention relates to a data scanning circuit and method. According to the present invention, a memory circuit stores a plurality of codes. Each of the code corresponds to a sub-rule. The memory circuit outputs at least first bit and at least second bit of each code, respectively, according to a first and a second data items. An operational circuit performs logic operations on the first and second bits, and produces an operated result. A decision circuit decides whether the input data satisfies the scanning rule according to the operated result.

Abstract: A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame,—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: A method and system for randomizing memory in a functional verification test of a user design is disclosed. A random number is generated during the functional verification test. The data stored in the memory of the user design is stored. Encryption keys unique for each memory address of the memory are generated. Each encryption key for each memory address is a function of the random number and the memory address. Data in each memory address of the memory is encrypted with the encryption keys unique for each memory address. After exiting a low-power or power-off state, data in each memory address is read and decrypted using the same encryption keys. Data before and after the low-power or power-off state are compared to test memory loss.

Abstract: A method of securely transferring data. The source data stored in a source memory (NV_MEM) is compared with the transferred data (COPY_ELT_X_V_MEM) that has been copied from the source memory (NV_MEM) into a “destination” memory (V_MEM). The method consists in reading from the source memory (NV_MEM) an integrity value (PI_ELT_X) associated with an element (ELEMENT_X_NV_MEM) such as file containing the source data, in calculating the integrity of a reconstituted element made up of the transferred data (COPY_ELT_X_V_MEM) associated, where appropriate, with the data of the source element (ELEMENT_X_NV_MEM) other than the data that was transferred, and in deciding that the transferred data (COPY_ELT_X_V_MEM) is identical to the source data when the integrity calculation gives a value identical to the integrity value of the source element (PI_ELT_X). The method applies to transferring data between components of a smart card.

Abstract: A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed on the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.

Abstract: Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios.

Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Abstract: A method for adjusting a memory signal phase is applied to data access between a memory controller and a dynamic random access memory (DRAM) of an electronic apparatus. The method includes writing a test data into the DRAM by the memory controller in response to a predetermined status of the electronic apparatus; generating a first data strobe signal; offsetting a phase of the first data strobe signal to access and verify the test data to generate a verification result; generating a target offset value in response to the verification result; and offsetting the phase of the first data strobe signal by the target offset value for subsequent operations.

Abstract: The present invention discloses a code checking method for a memory of a printed circuit board, which is to firstly add a check code to a data end of codes, after the codes is written in a memory, then use a timing controller to calculate a checksum of the data of the part of the primary codes and further compare the calculated checksum with the check code, and then output to a probe via a testing pin to display the result of comparison, so as to accomplish an object of checking if the written codes are correct. The present invention enhances work efficiency of checking the codes written in the memory.

Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.

Abstract: Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.

Abstract: A method for determining the frequency distribution of the signal level of a measured signal measured respectively in overlapping observation intervals via a time or frequency raster. The method includes determining the incrementation of a memory cell in a first memory to be implemented for each measured signal level of the measured signal at a value of the time or frequency raster, and un-delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle. The method also includes delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle, and subtracting the result of the delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle from the result of the un-delayed summation of the incrementation determined for every memory cell of the first memory in every measurement cycle.

Abstract: An electronic control apparatus comprises a nonvolatile memory, operating means, determining means and retrying means. The nonvolatile memory stores predetermined data and has a memory region which is divided into a plurality of sub-regions. The operating means executes a check operation for each of the sub-regions in order to check whether the data stored in the nonvolatile memory are normal or not. The determining means determines whether the check operation has detected any data errors. The retrying means allows the operating means to retry the check operation for a predetermined number of times for the sub-regions that have been determined to be in data error by the determining means.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1?i?M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1?j?M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.

Abstract: A method for reading data from a data storage system is provided. The method comprises requesting a virtual data volume to access data from one or more data blocks in the data storage system; requesting a virtual protection information volume to access protection information associated with the data blocks; validating the data using the protection information; and providing the data to the host interface, in response to successful validation of the data. A method for writing data to a data storage system is also provided. The method comprises receiving data to be written to one or more data blocks in the data storage system, wherein the data is stored in a cache; generating protection information to be stored on a virtual protection information volume; requesting a virtual data volume to update the data blocks with the data; and requesting the virtual protection information volume to store the protection information.

Abstract: An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Abstract: An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address.

Abstract: In a method for detecting errors in computer data in a memory, a check sum is calculated in runtime and compared to a stored check sum. In this method, the computer data is being subdivided into at least two logical blocks and a check sum is calculated for each logical block. Also provided is a computer unit having a processor and a memory which has a ROM in which firmware is stored, and/or which has a RAM, the memory having at least two logging functions for logging established memory errors, e.g., errors in the ROM and/or the RAM.

Abstract: A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.

Abstract: A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios.

Abstract: An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Abstract: A system for detecting memory corruption in an engine control module includes a variable selection module, an output module, an input module, and a response comparing module. The variable selection module selects a variable of a control system for testing. The output module outputs a predetermined value of said variable to a memory location where said variable is stored in said engine control module. The input module receives a response of said control system to said predetermined value when said predetermined value is written in said memory location. The response comparing module compares said response to a predetermined range and determines that said memory location is defective when said response is not within said predetermined range.

Abstract: A method for adjusting a memory signal phase is applied to data access between a memory controller and a dynamic random access memory (DRAM) of an electronic apparatus. The method includes writing a test data into the DRAM by the memory controller in response to a predetermined status of the electronic apparatus; generating a first data strobe signal; offsetting a phase of the first data strobe signal to access and verify the test data to generate a verification result; generating a target offset value in response to the verification result; and offsetting the phase of the first data strobe signal by the target offset value for subsequent operations.

Abstract: A system and method of securing data stored in a memory are disclosed. The method comprises storing a payload data in a memory in one of first and second states related by a transform, reading the payload data from the memory, attempting to use the payload data for an application, verifying the payload data as being in the first state, transforming the payload data as a function of the transform in response to verifying that the payload data is in the second state, and repeating performing the verifying and transforming steps until the payload data is verified as being in the first state.

Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.