Abstract: A power-supply control device and a power test system are disclosed. The power test system includes a memory and a processor. The processor is configured to: obtain at least one power-supply path manner of at least one power-down test device; determine at least one power-supply path interface according to the at least one power-supply path manner; determine at least one electronic switch according to the at least one power-supply path interface; determine at least one target device to be tested; obtain at least one power-down test instruction according to the at least one target device; establish a target power-supply path corresponding to the target device between the at least one power-supply path interface and the at least one electronic switch according to the power-supply path establishment parameter; and at the target power-supply path, perform a power-down operation according to the power-down execution parameter.

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

Abstract: A method for repairing a memory device with faulty memory cells. The method includes defining a RA environment comprising a location of each of the faulty memory cells and a plurality of SR and a plurality of SC. The method further includes repairing the faulty memory cells based on an RA training process using the defined RA environment and mapping of the location of each faulty memory cell with the plurality of SC or SR. The method further includes training, based on a determination that indicates the at least one faulty memory cell among the faulty memory cells is left unrepaired and the at least one SC or SR is remaining, a first NN to perform an action for repairing of the faulty memory cells such that a maximum number of faulty memory cells are reparable and a minimum number of SC and SR are utilized during the repairing.

Abstract: Aspects of the disclosure are directed to a storage device including a memory and a controller. In some examples, the controller is configured to measure an error rate of one or more blocks of the memory. In some examples, the controller is further configured to estimate, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off. In some examples, the controller is further configured to set a read level for multiple blocks of the memory, wherein the read level is determined based at least in part on the time shift.

Abstract: A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

Abstract: A memory system includes: an address scrambler suitable for scrambling an address based on a scrambling rule to generate a scrambled address; a memory core including a plurality of memory cells and suitable for storing data in memory cells designated by the scrambled address; and a scramble control circuit suitable for changing the scrambling rule in response to satisfaction of an attack condition.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

Abstract: A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

Abstract: Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Abstract: An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

Abstract: A method for operating a control unit when testing software of the control unit. The control unit includes a processor for executing the software and a memory for storing the software. The method includes: receiving test requests, generated by a test computer, in the control unit; executing a test program for testing the software based on the test requests, by executing a first binary file, which is stored in the memory, by the processor, the first binary file encoding a test version of the software which includes at least one test module necessary for executing the test program; sending test results from the control unit to the test computer; and receiving a second binary file, executable by the processor, in the control unit and storing the second binary file in the memory when the test computer has determined, based on the test results, that the software is fit for operation.

Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

Abstract: Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.

Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Abstract: A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.

Abstract: The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.

Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

Abstract: A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.

Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

Abstract: An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.

Abstract: A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.

Abstract: An approach to create a multiple use test case when one or more computer processors receive a first test case from a test generator. The approach includes the computer processors evaluating each instruction in the first test case to determine that an instruction meets a set of conditions for creating a multiple use test case. The method includes one or more computer processors generating a set of rules for each instruction meeting the one or more conditions to create the multiple use test case. Furthermore, the method includes one or more computer processors creating the multiple use test case by adding the set of rules to each instruction meeting the one or more conditions to create the multiple use test case.

Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

Abstract: A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.

Abstract: An apparatus, method and computer program are described, the apparatus comprising decode circuitry configured to decode instructions, and processing circuitry responsive to the instructions decoded by the decode circuitry to perform data processing. In response to the decode circuitry decoding a memory copy size determining instruction specifying as operands a source memory address, a destination memory address and a total number of bytes to be copied from a source block of memory locations indicated by the source memory address to a destination block of memory locations indicated by the destination memory address, the processing circuitry is configured to determine, based on at least one of the source memory address and the destination memory address, a memory copy size indicating value indicative of a subset of the total number of bytes to be copied. A data transfer instruction is also described.

Abstract: Provided is a control system which can support a user with respect to the designation of a data group to be collected. The control system (1) includes: first and second controllers (100, 200); a drive device (300) which has a plurality of safety functions for a motor (400); a data tracing module (154) which traces a state value for indicating an operation state of the motor (400); and a support device (500) which receives a setting of the data group to be collected including the state value. The support device (500) includes: a storage (510) which stores collection candidate information in which a data group of collection candidates is associated with a type of a safety function; and an output section (508) which outputs, as the data group to be collected, the data group of collection candidates associated with one selected safety function.

Abstract: A first operation is performed on a first portion of a plurality of data blocks. A request is received to perform a second operation associated with the plurality of data blocks. A rate of performance of the first operation on the first portion of the plurality of data blocks is determined. The second program operation is performed on a second portion of the plurality of data blocks based on the rate of performance of the first operation on the first portion of the plurality of data blocks.

Abstract: A memory module includes at least one semiconductor memory device, and a test pattern memory that stores first test pattern information for testing the at least one semiconductor memory device, and the first test pattern information stored in the test pattern memory is transferred to a host in a test operation. Through the memory module having the above-described function, a memory test is possible in consideration of a unique weak characteristic of the memory module.

Abstract: Various embodiments of the invention provide a system and a method for testing one or more devices under test (DUTs) and for checking one or more test setups. Each of the one or more test setups includes a test board having several sockets for receipt of a DUT. A custom hardware interface is used to electrically connect the test board, such as a burn-in board with a test system configuration having multiple modules that can be configured using a computer device and related software to provide customized testing of the DUTs. The system is scalable to accommodate any DUT having any number of channels and to provide customized testing. Results of the testing are sent to the computing device.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: configuring the memory device with a zoned namespace comprising a plurality of zones; notifying a host system of a failure associated with a zone of the plurality of zones, wherein the failure affects stored data; receiving from the host system an indication to continue at a capacity that is reduced; recovering the stored data of the zone affected by the failure; and updating the set of memory devices to change the capacity to a reduced capacity.

Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The computing device obtains a data identifier associated with a data object and determines DSN address(es) associated with storage of one or more encoded data slice(s) (EDS(s)). The computing device selects slice names based on the DSN address(es) and issues at least a read threshold number of read slice requests using slice names to at least some storage units (SUs). When an insufficient number of EDSs is received, the computing device issues an alternate read slice request to an alternate SU. When a sufficient number of EDSs is received from the alternate SU and the computing device has received at least the read threshold number of EDSs, the computing device reconstructs the data segment.

Abstract: A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.