Memory Testing Patents (Class 714/718)
  • Patent number: 11917053
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Patent number: 11913990
    Abstract: An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 27, 2024
    Assignee: Advantest Corporation
    Inventors: Olaf Pöppe, Klaus-Dieter Hilliges, Alan Krech
  • Patent number: 11899959
    Abstract: A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaewon Park, Sangkil Park, Jaehoon Lee
  • Patent number: 11899561
    Abstract: A method for operating a control unit when testing software of the control unit. The control unit includes a processor for executing the software and a memory for storing the software. The method includes: receiving test requests, generated by a test computer, in the control unit; executing a test program for testing the software based on the test requests, by executing a first binary file, which is stored in the memory, by the processor, the first binary file encoding a test version of the software which includes at least one test module necessary for executing the test program; sending test results from the control unit to the test computer; and receiving a second binary file, executable by the processor, in the control unit and storing the second binary file in the memory when the test computer has determined, based on the test results, that the software is fit for operation.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 13, 2024
    Assignee: ROBERT BOSCH GMBH
    Inventor: Antoni Lacasta I Sulla
  • Patent number: 11868286
    Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: January 9, 2024
    Assignee: Waymo LLC
    Inventors: Sabareeshkumar Ravikumar, Shishuang Sun, Feng Wang, Ji Zhang
  • Patent number: 11847339
    Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-hoon Woo, Hak-sun Kim, Kwang-jin Lee, Su-chang Jeon
  • Patent number: 11830565
    Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: November 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yoshihito Morishita, Hiroshi Ichikawa
  • Patent number: 11809719
    Abstract: Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 7, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Gautam Bhatia, Robert Bloemer
  • Patent number: 11775369
    Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 3, 2023
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
  • Patent number: 11776590
    Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Riccardo Muzzetto, Ferdinando Bedeschi, Umberto Di Vincenzo
  • Patent number: 11651835
    Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: May 16, 2023
    Assignee: DEEPX CO., LTD.
    Inventors: Lok Won Kim, Jeong Kyun Yim
  • Patent number: 11557366
    Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: January 17, 2023
    Assignee: SK hynix Inc.
    Inventors: Kyung Whan Kim, Sun Hwa Park, Kee Yun Kim, Sung Joo Ha, Ah Reum Han
  • Patent number: 11551772
    Abstract: A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yingquan Wu, Eyal En Gad
  • Patent number: 11495318
    Abstract: The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jung-Hsing Chien
  • Patent number: 11494317
    Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 8, 2022
    Assignee: Waymo LLC
    Inventors: Sabareeshkumar Ravikumar, Shishuang Sun, Feng Wang, Ji Zhang
  • Patent number: 11442854
    Abstract: Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Andrew Roberts
  • Patent number: 11437113
    Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventors: Min Hwan Moon, Chung Un Na
  • Patent number: 11404109
    Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Glen E. Hush
  • Patent number: 11398288
    Abstract: A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 26, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Phil Reusswig, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Patent number: 11392468
    Abstract: Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher John Kawamura, Scott James Derner, Charles L. Ingalls
  • Patent number: 11385285
    Abstract: An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 12, 2022
    Assignee: Advantest Corporation
    Inventors: Olaf Pöppe, Klaus-Dieter Hilliges
  • Patent number: 11379157
    Abstract: A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 5, 2022
    Inventor: Philip Enrique Madrid
  • Patent number: 11361136
    Abstract: An approach to create a multiple use test case when one or more computer processors receive a first test case from a test generator. The approach includes the computer processors evaluating each instruction in the first test case to determine that an instruction meets a set of conditions for creating a multiple use test case. The method includes one or more computer processors generating a set of rules for each instruction meeting the one or more conditions to create the multiple use test case. Furthermore, the method includes one or more computer processors creating the multiple use test case by adding the set of rules to each instruction meeting the one or more conditions to create the multiple use test case.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventor: Oz Dov Hershkovitz
  • Patent number: 11353509
    Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: June 7, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Yi Mao, Jin-Fu Huang, Dai-De Wei, Yong-Bin Cao
  • Patent number: 11348654
    Abstract: A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-Won Yoon, Sang-Hyun Joo
  • Patent number: 11347506
    Abstract: An apparatus, method and computer program are described, the apparatus comprising decode circuitry configured to decode instructions, and processing circuitry responsive to the instructions decoded by the decode circuitry to perform data processing. In response to the decode circuitry decoding a memory copy size determining instruction specifying as operands a source memory address, a destination memory address and a total number of bytes to be copied from a source block of memory locations indicated by the source memory address to a destination block of memory locations indicated by the destination memory address, the processing circuitry is configured to determine, based on at least one of the source memory address and the destination memory address, a memory copy size indicating value indicative of a subset of the total number of bytes to be copied. A data transfer instruction is also described.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: May 31, 2022
    Assignee: Arm Limited
    Inventors: James Tsung-Lun Yang, Richard William Earnshaw
  • Patent number: 11340561
    Abstract: Provided is a control system which can support a user with respect to the designation of a data group to be collected. The control system (1) includes: first and second controllers (100, 200); a drive device (300) which has a plurality of safety functions for a motor (400); a data tracing module (154) which traces a state value for indicating an operation state of the motor (400); and a support device (500) which receives a setting of the data group to be collected including the state value. The support device (500) includes: a storage (510) which stores collection candidate information in which a data group of collection candidates is associated with a type of a safety function; and an output section (508) which outputs, as the data group to be collected, the data group of collection candidates associated with one selected safety function.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 24, 2022
    Assignee: OMRON Corporation
    Inventors: Daisuke Tamashima, Asuka Sugiyama, Yuji Suzuki, Fumiaki Sato
  • Patent number: 11334278
    Abstract: A first operation is performed on a first portion of a plurality of data blocks. A request is received to perform a second operation associated with the plurality of data blocks. A rate of performance of the first operation on the first portion of the plurality of data blocks is determined. The second program operation is performed on a second portion of the plurality of data blocks based on the rate of performance of the first operation on the first portion of the plurality of data blocks.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yang Zhang
  • Patent number: 11328786
    Abstract: A memory module includes at least one semiconductor memory device, and a test pattern memory that stores first test pattern information for testing the at least one semiconductor memory device, and the first test pattern information stored in the test pattern memory is transferred to a host in a test operation. Through the memory module having the above-described function, a memory test is possible in consideration of a unique weak characteristic of the memory module.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jihyuk Oh, Jiseok Kang, Junho Jung
  • Patent number: 11320480
    Abstract: Various embodiments of the invention provide a system and a method for testing one or more devices under test (DUTs) and for checking one or more test setups. Each of the one or more test setups includes a test board having several sockets for receipt of a DUT. A custom hardware interface is used to electrically connect the test board, such as a burn-in board with a test system configuration having multiple modules that can be configured using a computer device and related software to provide customized testing of the DUTs. The system is scalable to accommodate any DUT having any number of channels and to provide customized testing. Results of the testing are sent to the computing device.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 3, 2022
    Inventor: Albert Gaoiran
  • Patent number: 11315654
    Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Yannis Jallamion-Grive, Cyrille Nicolas Dray, Frank David Frederick
  • Patent number: 11314278
    Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho Yeon Jeon, Ah Chan Kim, Jae Gon Lee
  • Patent number: 11307931
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: configuring the memory device with a zoned namespace comprising a plurality of zones; notifying a host system of a failure associated with a zone of the plurality of zones, wherein the failure affects stored data; receiving from the host system an indication to continue at a capacity that is reduced; recovering the stored data of the zone affected by the failure; and updating the set of memory devices to change the capacity to a reduced capacity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11307929
    Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11303429
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Patent number: 11294745
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The computing device obtains a data identifier associated with a data object and determines DSN address(es) associated with storage of one or more encoded data slice(s) (EDS(s)). The computing device selects slice names based on the DSN address(es) and issues at least a read threshold number of read slice requests using slice names to at least some storage units (SUs). When an insufficient number of EDSs is received, the computing device issues an alternate read slice request to an alternate SU. When a sufficient number of EDSs is received from the alternate SU and the computing device has received at least the read threshold number of EDSs, the computing device reconstructs the data segment.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 5, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Gary W. Grube, S. Christopher Gladwin
  • Patent number: 11295791
    Abstract: A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Atul Katoch, Ali Taghvaei
  • Patent number: 11288406
    Abstract: An embodiment is directed to a hardware circuit for performing operations on data transmitted between a processor and memory. The hardware circuit includes a first interface communicatively coupled to the processor. The first interface configured to emulate a first protocol of the memory. The hardware circuit further includes a second interface communicatively coupled to the memory. The second interface configured to emulates a second protocol of the processor. The hardware circuit also includes hardware logic configured with a bi-directional path, such that each of the first and second interfaces is associated with a different direction of the bi-directional path. The bi-directional path is configured to execute an operation on data received at both the first interface and the second interface.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 29, 2022
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Nhut Tran, J. Ryan Prince, Brian Nugent, Elliot Greenwald
  • Patent number: 11282824
    Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventor: Matthew H. Klein
  • Patent number: 11262924
    Abstract: Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 1, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William R. Alverson, Amitabh Mehra, Anil Harwani, Jerry A. Ahrens, Grant E. Ley, Jayesh Joshi
  • Patent number: 11263177
    Abstract: Disclosed is a novel system and process for automating the process of identifying deleted file chunks. The present invention has two components. A client component to identify data chunks and a server component for storage and indexing technology for the over 1 billion records relating to the data chunks necessary to run the software.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: March 1, 2022
    Assignee: Child Rescue Coalition, Inc.
    Inventors: Jose Omar Garcia-Fernandez, William Scott Wiltse
  • Patent number: 11251148
    Abstract: Semiconductor devices are disclosed. According to some embodiments, a semiconductor device may include a memory array area and a peripheral area. The memory array area may include a number of memory cells and a number of array pads configured to receive an input voltage. The peripheral area may include a number of peripheral pads for interfacing with the memory array area. In these or other embodiments, the peripheral area may be arranged adjacent to a first edge of the semiconductor device and the number of array pads may be arranged proximate to a second edge of the semiconductor device. The second edge may be perpendicular to the first edge. The memory array area may also include an array distribution conductor configured to variously electrically connect the number of memory cells to the number of array pads. A semiconductor-device package and system are also disclosed.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hisamitsu Kimoto
  • Patent number: 11249839
    Abstract: A system with multiple processing domains sharing a memory resource accessed via a shared memory controller detects a memory error. As data is written to the shared memory resource, each processing domain generates a diagnostic code as a function of the data, the memory address for the data, and of a unique identifier corresponding to the processing domain. The diagnostic code is stored with the data for verification when the data is read back. As the data is read back, the processing domain separates the diagnostic code from the data being read and generates another diagnostic code in the same manner as the original diagnostic code. The other diagnostic code is compared to the initial diagnostic code. If both diagnostic codes are the same, the processing domain can be confident that the data read from the shared memory resource is the same as the data that was originally written.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 15, 2022
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Anthony G. Gibart, Joseph P. Izzo, Jonathan R. Engdahl, Benjamin H. Nave
  • Patent number: 11249847
    Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Patent number: 11238204
    Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 1, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Scott David Huss, Loren B. Reiss, Fred Staples Stivers, Steven Martin Broome
  • Patent number: 11195563
    Abstract: A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Kyung Hoon Kim
  • Patent number: 11194519
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 7, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 11188417
    Abstract: An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Hoiju Chung
  • Patent number: 11158394
    Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Griffin, Dustin J. VanStee
  • Patent number: 11152077
    Abstract: A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 19, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Gary D. Hamor, Michael T. Brady, William A. Marcus, Larry J. Koudele