Memory Testing Patents (Class 714/718)
  • Patent number: 10847213
    Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 24, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 10804953
    Abstract: A method includes (a) switching a receiver path network of a front end module to a first matching mode in a receive mode. The method further includes (b) switching a transmitter path network of the front end module to a first resonance mode in the receive mode. The method further includes (c) switching the transmitter path network to a second matching mode in a transmit mode. The method further includes (d) switching the receiver path network to a second resonance mode in the transmit mode.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: En-Hsiang Yeh, Monsen Liu, Chuei-Tang Wang
  • Patent number: 10790039
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hyunui Lee, Chiaki Dono
  • Patent number: 10789184
    Abstract: In the present invention, computational efficiency degradation is suppressed when diagnosing a shared storage area in a vehicle control device in which a plurality of computing units are employed. This vehicle control device suppresses computational efficiency degradation by changing an access destination in a storage device while diagnosing a shared storage area that the storage device has.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 29, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsunamichi Tsukidate, Yusuke Abe, Takeshi Fukuda, Tomohito Ebina, Fumio Narisawa
  • Patent number: 10782349
    Abstract: A test interface board includes a first input terminal, a second input terminal, an output terminal, and a transmission line. The first input terminal receives a first test signal for testing a semiconductor device. The second input terminal receives a second test signal for testing the semiconductor device. The output terminal outputs the first test signal and the second test signal to the semiconductor device. The transmission line electrically connects the first input terminal, the second input terminal, and the output terminal such that the first test signal and the second test signal are merged.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yongjeong Kim
  • Patent number: 10783091
    Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 22, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Fabrice Romain
  • Patent number: 10776227
    Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 15, 2020
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Kyu Hyun Choi
  • Patent number: 10770151
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: September 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Jae Hyuk Bang
  • Patent number: 10762967
    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: APPLE INC.
    Inventors: Assaf Shappir, Barak Baum, Itay Sagron, Roman Guy, Guy Ben-Yehuda, Stas Mouler
  • Patent number: 10748613
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 18, 2020
    Assignee: MIcron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Patent number: 10725882
    Abstract: A method as well as a crypto-arrangement and a computer program product for monitoring an integrity of a test dataset, wherein a random sample of a test dataset is checked for integrity is provided. The method for monitoring an integrity of a test dataset includes the following steps: random sample-type selection of the test dataset from a dataset to be transferred via a communications connection; cryptographically protected provision of the selected test dataset to a test unit, wherein a communication via the communications connection is carried out uninfluenced by the selection and preparation; testing of the cryptographically protected test dataset for integrity by the test unit, based on cryptographic calculations and plausibility information.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: July 28, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Rainer Falk
  • Patent number: 10719398
    Abstract: Each SSD in an array is divided into splits that are contiguous LBA ranges of equal capacity. The splits are managed as if they were sub-drives or logical drives and used in RAID groups or other forms of redundancy schemes. A processor external to the SSD collects pending defect data log from the SSDs and determines which splits are associated with reported defects. Failed splits are rebuilt in spare splits using RAID or another redundancy scheme. Repaired splits are returned to service as spare splits. Irreparable splits are marked as lost. In the case of SSD failure the data splits of the SSD are rebuilt to a spare SSD. If enough failed splits of the failed SSD can be repaired then the repaired SSD may be returned to service.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 21, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jun Li, James Marriot Guyer, Michael D Garvey, Stephen Richard Ives
  • Patent number: 10714206
    Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Ryota Suzuki
  • Patent number: 10704885
    Abstract: An integrated circuit device and a high bandwidth memory device are disclosed. The integrated circuit device includes a plurality of warpage detection sensors at a plurality of different positions, respectively, and electrically connected in series. Each of the plurality of warpage detection sensors is configured to generate a clock signal with a period that is based on a resistance that varies based on a pressure at a corresponding position, and to generate digital data by performing a counting operation in response to the clock signal.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Pil Son, Woo Yeong Cho
  • Patent number: 10706951
    Abstract: In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 7, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kenichi Anzou
  • Patent number: 10705773
    Abstract: An object of the present invention is to suppress a printing apparatus from becoming unavailable due to the life of a nonvolatile memory ending. The present invention is a printing apparatus including: a volatile memory; a nonvolatile memory in which a rewrite of data is performed in units of blocks and whose number of times of rewrite has an upper limit; and a management unit configured to manage a use of the volatile memory and the nonvolatile memory as a spool buffer temporarily storing print data, and the management unit limits the use of the nonvolatile memory based on an estimated life of the nonvolatile memory, which is different from state information indicating a state of a defective block of the nonvolatile memory.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 7, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tatsunori Sasaki, Hironori Nakamura
  • Patent number: 10684793
    Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-ju Chung, Su-a Kim, Mu-jin Seo, Hak-soo Yu, Jae-youn Youn, Hyo-jin Choi
  • Patent number: 10679913
    Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Ah Hyun, Seok Bo Shim, Sang Ho Lee
  • Patent number: 10679720
    Abstract: A memory circuit and a testing method thereof are provided. The memory circuit includes multiple stage non-volatile memory (NVM) devices. An Nth stage NVM device includes a logic memory circuit, an NVM element, a write circuit and a read circuit. The logic memory circuit receives external data via a data input terminal in a normal mode and receives test data via a test input terminal in a test mode. The write circuit writes the test data or the external data to the NVM element during a writing period. The read circuit transmits stored data stored in the NVM element to an output terminal of the logic memory circuit during a reading period.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 9, 2020
    Assignee: Nuvoton Technology Corporation
    Inventor: Cheng-Chih Wang
  • Patent number: 10664372
    Abstract: An example data bus and testing system includes a data bus, first device, and second device. The first device is configured to transmit test data on the data bus, hold the transmitted test data on the data bus using a bus-hold feature, and read back the test data from the data bus during application of the bus-hold feature. The second device is configured to determine whether a fault condition exists on the data bus based on whether the read back test data differs from the transmitted test data. A method of testing a data bus is also disclosed.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 26, 2020
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Lon R. Hoegberg
  • Patent number: 10657002
    Abstract: A method for correcting improper repair actions in a computer system includes assigning a first algorithm identifier to a first algorithm and storing the first algorithm identifier and a first input to the first algorithm. The method includes executing the first algorithm with the first input and storing one or more results of the first algorithm, where the one or more results includes a repair action. The method includes determining that the repair action is faulty and storing the algorithm identifier for the first algorithm in a blacklist. The method also includes assigning a second algorithm identifier to a second algorithm and storing the second algorithm identifier and a second input to the second algorithm. The method includes executing the second algorithm with the second input, where the second algorithm corrects the faulty repair action caused by the first algorithm, and storing a result of the second algorithm.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicholas E. Bofferding, Andrew J. Geissler, Michael C. Hollinger, Adriana Kobylak
  • Patent number: 10641226
    Abstract: A system is disclosed which includes a remote generator interface controller and a generator interface device. The generator interface device receives generator operation information and transmits the generator operation information to the remote generator interface controller. The remote generator controller device includes a processor, a screen, and a wireless receiver connected wirelessly to receive generator operation information from the generator interface device connected to a generator. The generator interface device includes a processor connected to a generator which receives generator operation information from at least one of a generator computer and a generator sensor and a transmitter connected wirelessly to transmit the generator operation information wirelessly from the generator interface device to the remote generator controller device.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: May 5, 2020
    Assignee: Wheeler Machinery Co.
    Inventor: Scott Murdock
  • Patent number: 10628065
    Abstract: Some examples of the present disclosure generally relate to integrated circuits that include hardware logic for detecting an edge of a signal. In some examples, an integrated circuit includes a traffic generator, a memory communication path, a comparator, and edge detection hardware logic. The traffic generator, comparator, and edge detection hardware logic are configurable based on a calibration stage. The traffic generator is operable to generate commands to memory via a memory communication path. The comparator is operable to compare data from the memory communication path with known data and to responsively output a comparison status. The data from the memory communication path is in response to the commands generated by the traffic generator. The edge detection hardware logic is operable to detect an edge of a signal based on the comparison status.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Amit Vyas, Ramakrishna R. Gaddam
  • Patent number: 10628084
    Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
  • Patent number: 10622088
    Abstract: A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ahn Choi
  • Patent number: 10622077
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
  • Patent number: 10613142
    Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10593419
    Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: March 17, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Steven Lee Gregor, Puneet Arora, Norman Robert Card
  • Patent number: 10592338
    Abstract: Scale out data protection with erasure coding is presented herein. Based on an initial number of storage devices determined to have been included in an initial stage of a data storage cluster, an initial protection scheme for the initial stage can determine first coding fragment(s) for data stored within the data storage cluster to facilitate a first recovery, from the initial stage, of the data using the first coding fragment(s). Further, in response to a defined number of additional storage devices being determined to have been added to the data storage cluster to generate a modified data storage cluster, the initial protection scheme can be modified to obtain a modified protection scheme that can determine, for the modified data storage cluster, second coding fragment(s) for the data to facilitate a second recovery of the data using the first coding fragment(s) and the second coding fragment(s).
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 17, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Andrey Kurilov
  • Patent number: 10593421
    Abstract: One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 17, 2020
    Assignee: CNEX Labs, Inc.
    Inventor: Yiren Ronnie Huang
  • Patent number: 10593387
    Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Yeon Doo, Seungjun Bae, Sihong Kim, Hosung Song
  • Patent number: 10585138
    Abstract: Systems and methods for testing and/or operating remote devices are disclosed. The embodiments provide cost-effective, convenient, and flexible means for the sensing and/or probing of remote devices. Signals generated by remote devices may be received, analyzed, logged, and displayed, i.e., enhancements to the functionalities of an oscilloscope are achieved. Signals to remote devices may be provided, i.e. enhancements to the functionalities of a wave generator, logic analyzers, bus analyzers, and the like are achieved. More particularly, enhancements to the operability, capabilities, and functionality of such previously available testing equipment, are provided, via the operation of a remote, portable, and lightweight test bed. The test bed may be operated and controlled remotely via a user-computing device. The test bed senses, probes, and/or controls a remote device and test data is generated and/or acquired.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 10, 2020
    Assignee: AZ, LLC
    Inventor: Sana Rezgui
  • Patent number: 10579289
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes recording use information according to each physical erasing unit of a rewritable non-volatile memory module. The method also includes configuring a plurality of super physical units. An address offset value corresponding to a first unavailable physical programming unit of a first physical erasing unit in a first super physical unit is the same as an address offset value corresponding to a first available physical programming unit of a second physical erasing unit in the first super physical unit.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 3, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ming-Yen Lee
  • Patent number: 10567163
    Abstract: A processor using an internal memory to store constants Kt required in a secure hash algorithm (SHA). The latency due to loading the constants Kt from an external memory, therefore, is eliminated. The processor further introduces an instruction set architecture that provides one instruction for the processor to read the constants Kt from the internal memory and perform a particular process on the read constants Kt. Thus, the SHA works efficiently.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 18, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Zhi Zhang
  • Patent number: 10539617
    Abstract: A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
  • Patent number: 10535406
    Abstract: A copy-back method of a storage device includes reading a memory data from a source area of the storage device. A number of error bits of the memory data is determined. An inspection read operation is performed if the number of error bits exceeds a reference value. The memory data is written to a destination area of the storage device if the number of error bits does not exceed the reference value.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Intae Hwang, Jinwan Jun
  • Patent number: 10529438
    Abstract: The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 7, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10489243
    Abstract: According to one embodiment, for first data, which is read from a nonvolatile memory, for which a first data translation is performed, a second data translation that is a reverse translation of the first data translation is performed. Next, for the first data for which the second data translation is performed, the first data translation is performed. In addition, the read first data is compared with the first data for which the first data translation is performed, and check information is generated based on a result of the comparison.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuki Inoue, Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Youhei Fukazawa
  • Patent number: 10482989
    Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 19, 2019
    Inventors: Steven Lee Gregor, Puneet Arora, Norman Robert Card
  • Patent number: 10481974
    Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Zion S. Kwok, Santhosh K. Vanaparthy, Ravi H. Motwani
  • Patent number: 10481202
    Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Jain, Nishi Bhushan Singh, Rahul Gulati, Pranjal Bhuyan, Rakesh Kumar Kinger, Roberto Averbuj
  • Patent number: 10460786
    Abstract: Reverse pulse schemes for reducing write error rate in magnetoelectric random access memory applications can be implemented in many different ways in accordance with various embodiments of the invention. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell and applying a voltage of a polarity opposite the given polarity across the magnetoelectric junction bit at the end of the application of the voltage of the given polarity, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 29, 2019
    Assignee: Inston, Inc.
    Inventors: Albert Lee, Hochul Lee
  • Patent number: 10454759
    Abstract: Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10445283
    Abstract: Out-of-band management of data drives including receiving, from a user, a control command targeting a data drive communicatively coupled to a backplane, wherein the data drive is communicatively coupled to the computing device via an interconnect bus; generating, based on the control command, an out-of-band command targeting a baseboard management controller (BMC) communicatively coupled to the backplane, wherein the out-of-band command comprises a data drive location identifier; sending the out-of-band command to the BMC, wherein the BMC, in response, identifies the data drive on the backplane using the data drive location identifier and a cable topology table, and performs the out-of-band command on the data drive; and receiving, from the BMC, a first notification that the out-of-band command has been performed on the data drive identified by the data drive location identifier.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 15, 2019
    Assignee: Lenovo Enterprise Solutions (Singaore) Pte. Ltd.
    Inventors: Wilson Velez, Luke D. Remis, Mark E. Andresen
  • Patent number: 10447534
    Abstract: A system, computer program product, and computer-executable method of managing a converged infrastructure, the system, computer program product, and computer-executable method including receiving system configuration information and updating the converged infrastructure with the configuration information.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 15, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Dragan Savic, John S. Harwood
  • Patent number: 10438678
    Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Eric D. Hunt-Schroeder, Michael A. Ziegerhofer
  • Patent number: 10438679
    Abstract: A memory diagnosis apparatus to diagnose whether a fault occurs in a memory includes a diagnosis execution unit to divide the memory into a plurality of areas, select two or more base areas that are diagnostic targets from among the areas to carry out a memory diagnosis including a reading test and a writing test, and perform only the writing test in carrying out the memory diagnosis on a same base area for second or more times. The diagnosis execution unit is implemented by an arithmetic device that is a processing circuit that executes a memory diagnosis program stored in a storage device.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 8, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoya Ichioka, Ryoichi Sasaki, Takahiro Akimoto
  • Patent number: 10431296
    Abstract: A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input signals each having a second bit-width. A memory array is configured to receive each of the plurality of serialized input signals. The memory array is further configured to generate a plurality of serialized output signals. A de-serializer is configured to receive the plurality of serialized output signals and generate a non-serialized output signal. The plurality of serialized output signals each have a bit-width equal to second bit-width and the non-serialized output signal has a bit-width equal to the first bit-width.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Cheng Chen, Jack Liu
  • Patent number: 10409698
    Abstract: A method for performing a plurality of tests on a device under test comprises performing a plurality of tests on a device under test. Each test of the plurality of tests comprises a foreground process and a background process. The foreground process comprises a setup process during which a desired test mode is set. The background process comprises an upload process during which data captured from the device under test is provided. The foreground process is executed with a higher priority than the background process, thereby minimizing a delay between a start of consecutive tests of the device under test.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: September 10, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Martin Dresler, Johannes Hauf, Martin Schmitz
  • Patent number: 10409673
    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Tommaso Vali, Michele Incarnati