Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the memory zone to check the integrity of data read in the memory. The method can be applied to the securing of smart cards.

Abstract: A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

Abstract: A method for a bounds test includes receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value, and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A computer readable medium stores instructions for a bounds test, the instructions for causing a computer to perform: receiving a base value, a size value, and a test value; subtracting the base value from the test value to generate a result value in a signed format; comparing the result value and the size value; and passing the bounds test when the size value exceeds the result value interpreted as an unsigned value. A bounds test system includes a processor, wherein the processor supports two's-compliment notation; and a memory, operatively connected to the processor.

Abstract: Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.

Abstract: A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upon the stored test vector by a vector data generator within the vector data engine to update the stored test vector; and repeating the steps of transmitting and performing so as to continuously transmit continuously changing stored test vectors to the memory array.

Abstract: There is provided a test apparatus that tests a device under test.

Abstract: In some embodiments, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical OR operation is applied to each bit in the memory with a bit value as the first operand and a corresponding register value in the first register as the second operand. Additionally, the method includes initializing each bit in the memory to one. Also, a logical AND operation is applied to each bit in the memory with the bit value as the first operand and a corresponding register value as the second operand.

Abstract: A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operation on a flash memory using a predetermined logical address, a conversion unit which converts the logical address into a physical address, and a control unit which performs the data operation on the physical address and writes inverted data obtained by inverting error correction code (ECC) corresponding to data used in the data operation to a region indicating whether the ECC is erroneous.

Abstract: A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a second test value into remaining registers of the plurality of registers. A first set of operations is performed between the one of the plurality of registers and each of the remaining registers to produce a first set of results. A fault is indicated when one of the first set of results varies from a first predetermined result.

Abstract: A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to determine whether the semiconductor memory device is defective. The plurality of comparators are respectively controlled by a respective plurality of strobe signals having relative phase delays so that the test output pattern is compared to the expected output pattern at different times.

Abstract: In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting only configuration information of dynamic reconfiguration arithmetic cells needed to be changed. However, this results in an increase in area of the arithmetic circuit. According to the present invention, a shift register is the only hardware resource in the dynamic reconfiguration arithmetic block for changing the configuration information. The shift register is structured by connecting in series storage units corresponding one-to-one with each arithmetic cell. An output from the end terminal of the shift register and an output of the configuration information storage unit are input to the configuration information selector, and an output of the configuration information selector is connected to the front of the shift register. The cell address counter counts up from 0 and increments one at a time.

Abstract: On a CD-R, a UID that is unique identification information is pre-recorded. When the CD-R is loaded into an information terminal unit, the UID is read and transmitted to a management server through the Internet. The management server determines whether predetermined data can be recorded onto the CD-R in accordance with the received UID. For example, when the UID is valid, contents data is downloaded from the management server to the information terminal unit and recorded onto the CD-R. In addition, for example, when the UID is valid, a notification that represents that contents data is permitted to be copied or moved is transmitted from the management server to the information terminal unit. As a result, contents data recorded on another recording medium can be copied or moved to the CD-R.

Abstract: A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written, and a storage unit configured to store the data and the error detecting code in the memory cell.

Abstract: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

Abstract: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

Abstract: A method for easily detecting a memory error that may occur when a memory is accessed or an allocated memory is freed in the process of developing software is disclosed. The memory error detecting method includes: (a) generating an original block indication variable for indicating a starting memory block of a memory region allocated with respect to a variable included in a computer program; (b) detecting a memory error that may occur when the allocated memory region is accessed, by performing a certain operation (computing or arithmetic operation), before the allocated memory region is accessed, using a target block indication variable indicating memory block to be accessed in the allocated memory region and/or the original block indication variable; and (c) outputting information about a detected memory error.

Abstract: On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply redundancy resources is stored inside two arrays (fill_array, shift_array) on chip. A final diagnosis may apply redundancy resources based on this stored information. The first array (fill_array) is used to keep a minimum error mapping and the second array (shift_array) is used to control the fill of the first array.

Abstract: A vehicle having a system for validating a variable signal for input to a processor-performed function. An input module receives the signal. A processor tests first and second storage locations of a memory. After testing, the processor stores the signal in the first and second storage locations to obtain first and second stored values. The processor compares the first and second stored values and tests the first stored value for any corruption associated with receipt of the signal by said input module. The processor inputs the first and second stored values to first and second paths for performing the function to obtain two function results, and compares the results.

Abstract: A CPU is provided with an ability to modify its operation, with respect to error correction, as a programmable feature. An error correction scheme is selected to be performed by the error correcting circuit. The compiled program may have intentionally introduced errors which are predictably corrected by the selected error correction scheme. When a program is compiled, the program is modified by the intentional insertion of errors which would result from the execution of the program. By providing error correction schema selected during program compilation, errors can be inserted in the program code, but are handled in a predictable manner by the error correction.

Abstract: Described herein are one or more implementations for facilitation of computer software testing. One or more implementations, described herein, determine logical type of one or more test input-parameters based upon metadata placed on a function under test (FUT) of software. Using that determined logical type, an implementation generates data values. In some instances, those generated values are values selected from a repository of data values with associated logical types. The selection is based upon the determined logical type. After generating data values for testing the FUT, an implementation supplies the generated data values as input to the FUT.

Abstract: The invention relates to a method and device for operating and/or testing memory units, which make it possible to conduct a time-saving test of semiconductor memories during running operation. The inventive method for testing memory units having storage locations provides that, for the storage locations, a first item of test information is formed according to a variable parameter assigned to the respective storage location and according to the contents of the respective storage location.

Abstract: When ENG frames created in an ENG transceiver unit and ECT frames subjected to gateway processing in an ECT gateway processor are transmitted around the same time, a transmission mediating unit alternately transmits each of the ENG frames and the ECT frames. Therefore, as compared with a case where one type of frames are preferentially transmitted, transmission of both types of frames can be started at the earliest timing.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: A test method for electronic memories includes reading out a previously defined test pattern sequentially as a time-dependent signal from the memory, determining the associated spectrum from the time-dependent signal by Fourier transformation, and assessing the memory to be tested using the spectrum. Also included is a suitable test device for the method.

Abstract: An accelerated test method evaluates, under accelerated conditions (a temperature T2 and a voltage V2), an endurance characteristic of a ferroelectric memory device having a capacitor element including a ferroelectric film under actual operating conditions (a temperature T1 and a voltage V1). An acceleration factor (K) required to evaluate the endurance characteristic is derived by using an expression: logK=A(1/V1?1/V2)+B(1/V1T1?1/V2T2) (where each of A and B is a constant).

Abstract: A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.

Abstract: A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. Hashing is performed with respect to the plurality of data words to generate a first hash value. The host processor compares the first hash value with a second hash value to see whether the first and second hash values are the same or different. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

Abstract: An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.

Abstract: The present invention includes a method for characterizing semiconductor failure. The method includes determining the dimensions of certain characteristics of a memory chip. The method defines a group of characteristics for a semiconductor of given dimensions. The method defines a ratio based on variables supplied by production test systems. By comparing a set of characteristics for a specific semiconductor to the ratio to determine the dominant type of failure on the semiconductor chip. The invention is an efficient method of obtaining information regarding the types of failures common on semiconductor chips.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: A method and a system for data protection of fixed and learned control data of duplicated, program-controlled computers, in which the control parameters are stored in an EEPROM. The memory available in the EEPROM is divided into three areas. Each area is monitored using a check sum (check sum 1, check sum 2, check sum 3) that is stored therein. Only the self-learned variables are maintained redundantly. Thus, the ability to store more data than previously in the EEPROM with the same data protection and the same accessibility is provided, thus allowing more flexible solutions with respect to varying customer requirements to be offered.

Abstract: A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.

Abstract: An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area.

Abstract: The present invention provides a device, method and storage medium, stored with software programs, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, can shorten the time needed for full manual interpretation of the obtained results, by automatically interpreting the analyzed results obtained, and calculating the period of distribution patterns and the mix rate of regular patterned defects. First in defect number calculation process 71, the total defect number of bits is found; and in factor selection process 61, the factor f is then selected.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).

Abstract: A pattern generator for use in a semiconductor test device provided with a random access memory which has large capacity and runs at high speed and is capable of generating random pattern data having large capacity and running at high speed. Parts of random pattern data previously stored in a sequential pattern memory are transferred to addresses of a random pattern memory which are specified by the difference calculated by an arithmetic circuit between address data outputted from a control circuit and address data outputted from an address generator, and the transferred random pattern data are outputted to a semiconductor to be tested through a selection circuit.

Abstract: A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

Abstract: For processing data, particularly for transmission via a channel with an specifiably variable data rate, the data are classified into bit classes that are provided with different error redundancy. These bit classes are also weighted with weighting factors. The assignment of the code rates for the bit classes takes place as a function of the respective weighting factors. It is possible to provide a scalable.With the invention, it is possible to realize a scalable channel codec whose configuration is a function solely of the available channel codec bit rate. Such a channel codec is easy to adapt to different transmission techniques.

Abstract: Embodiments of the invention include a method and apparatus for modulating data retrieved from page-wise memory systems such as holographic memory systems. The inventive method uses the detection of one or more test signals included within stored data image pages to estimate the behavior of the retrieved data image pages and to normalize the retrieved information accordingly. The method includes allocating a portion of the data image pages of interest for one or more determinable test signals and incorporating the test signal information into the data image pages prior to storage of the data image pages within the storage medium. Upon retrieval of the data image pages from the storage medium, the test signals are detected and used to form the basis of estimated data member behavior across individual data image pages and, alternatively, from one data image page to another. Based on the estimated behavior, appropriate normalization is performed on the data image pages.

Abstract: In a digital system having non-volatile memory devices for storage of digital information therein, the digital information being organized in sectors, each sector having a data field and a corresponding extension field, a controller device for performing operations such as reading and writing to and erasing information from a selected plurality of sectors and further verifying successful erasure of the selected erased sectors, the controller device including an error detection circuit for detecting errors within each of the sector data fields using the corresponding sector extension field and a flash interface circuit coupled to the non-volatile devices through a data bus for receiving an erased sector of information therethrough and being operative to pass the data field of the erased sector information and a predetermined extension field to the error detection circuit wherein the error detection circuit calculates an extension field corresponding to the erased sector data field, compares the calculated exte