Clock Or Synchronization Patents (Class 714/731)
  • Patent number: 11017135
    Abstract: Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 25, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Athmanathan Vaidyanathan
  • Patent number: 10998890
    Abstract: A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 4, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Bin Li, David Bostedo, Landon J. Caley, Nicholas J. Chiolino, Patrick Fleming, David D. Moser
  • Patent number: 10979044
    Abstract: In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christoph Rumpler, Achim Dallmann
  • Patent number: 10921371
    Abstract: The disclosed technology facilitates programmable scan shift testing for a scan chain including at least a first segment of scan-flops connected in series with a second segment of scan-flops. The scan chain includes at least a first multiplexor positioned between the first segment and the second segment that is configured to selectively supply scan input from a test controller to the second segment while preventing the second segment from receiving an output of the first segment.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 16, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jay Shah, Aniruddha Mukund Bhasale
  • Patent number: 10901838
    Abstract: Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond Wong, Jie Zheng
  • Patent number: 10867689
    Abstract: A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael Richard Spica
  • Patent number: 10830488
    Abstract: The present disclosure includes an HVAC system that includes a plurality of dampers each corresponding to one building zone of a plurality of building zones, a plurality of sensors each corresponding to the one of the plurality of building zones, and a control board communicatively coupled with the plurality of dampers and sensors. The control board includes a plurality of status light sources, each corresponding to one damper the plurality of dampers, a plurality of communication light sources each corresponding to one sensor of the plurality of sensors, and a microcontroller programmed to control operation of equipment in the HVAC system. The microcontroller is configured to perform “a hardware test mode” to facilitate diagnosis of the plurality of dampers by causing the plurality of status light sources to sequentially execute a first light scheme or a second light scheme in response to instructions to the plurality of dampers.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: November 10, 2020
    Assignee: Johnson Controls Technology Company
    Inventor: Shaun B. Atchison
  • Patent number: 10747926
    Abstract: A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: August 18, 2020
    Assignee: Tsinghua University
    Inventor: Dong Xiang
  • Patent number: 10732850
    Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Takafumi Ito
  • Patent number: 10706948
    Abstract: A method for multi-level memory safety for a sensor integrated circuit can include loading a blocking bit into a volatile memory from a non-volatile memory and providing the blocking bit to a gating circuit from the volatile memory. Further, the method may include the gating circuit determining whether to provide a default value to a functional logic based upon the provided blocking bit.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 7, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Nicolas Rafael Biberidis, Octavio H. Alpago, Nicolas Rigoni
  • Patent number: 10665165
    Abstract: An organic light-emitting display panel, an organic light-emitting display apparatus and a driving method of the organic light-emitting display panel are provided. The organic light-emitting display panel includes a data line and a gate line intersecting the data line, a switching signal line, a pixel driving circuit including a first voltage terminal for supplying a high-level direct current voltage, a driving transistor, a light-emitting diode and a photosensitive switch electrically connected between the first voltage terminal and the light-emitting diode; a photosensitive element disposed at a non-display region of the organic light-emitting display panel; and a control circuit including a storage module and a control module. The photosensitive element is configured to sense environment brightness and is electrically connected with the control circuit.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: May 26, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Yue Li, Gang Liu, Zhonglan Cai
  • Patent number: 10605855
    Abstract: A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: March 31, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Sen Wang, Yuan-Yao Chang, Hung-Chi Chiu, Chia-Wei Huang
  • Patent number: 10545189
    Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 28, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Bala Tarun Nelapatla, Shantanu Sarangi, Rajendra Kumar reddy.S, Sailendra Chadalavada
  • Patent number: 10496771
    Abstract: In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: December 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroyuki Iwata
  • Patent number: 10453520
    Abstract: A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10451674
    Abstract: Described is an apparatus which comprises: a circuitry to selectively switch between a functional clock or a scan clock; a first plurality of circuitries to generate a plurality of pulses according to the scan or functional clocks; and a second plurality of circuitries to generate a plurality of clocks according to the plurality of pulses, wherein the plurality of clocks are for testing one or more circuitries.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Dhruv S. Dani, Uday Padmanabhan, Richard Murphy, Aniket Bharaswadkar, Boris Razmyslovitch
  • Patent number: 10446251
    Abstract: A method of screening for configuration-related defects in integrated circuits is provided. To detect configuration defects, test pattern configuration data and error correction data for that test pattern are loaded into configuration memory. Existing cyclic redundancy check circuitry on the integrated circuit is recruited to compute check-sum signatures based on the data stored in each frame of the memory array. Defects in configuration memory cells and configuration-related circuitry are identified by comparing the error correction data of frame to the computed check-sum signature of a frame. Localized freezing of programmable logic associated with configuration memory is optionally applied to eliminate data contention and ensure maximum coverage of the memory array during screening. Several test patterns of configuration data are also provided.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Kalyana Ravindra Kantipudi
  • Patent number: 10410699
    Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan Borole, Muhammad M. Khellah, Pascal A. Meinerzhagen
  • Patent number: 10395691
    Abstract: A data storage drive has two controllers with respective digital control outputs and serial channels. The drive has a serial test channel operable to communicate with a testing system. A switching circuit is coupled to the digital control outputs, the serial channels, and the serial test channel. The switching circuit is configured to, in response to respective combinations of binary values set via the digital control outputs, switch lines of the serial test channel between the respective serial channels of the controllers. The controllers are configured to set the combinations of binary values in response to one or more command received via a receive line of the serial test channel.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 27, 2019
    Assignee: Seagate Technology LLC
    Inventors: Kyaw Sin Maung, Aaron M. Schmidt
  • Patent number: 10379161
    Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 10359970
    Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: George Pax, Jonathan Parry
  • Patent number: 10360329
    Abstract: Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert J. Allen, Vasant B. Rao, William J. Wright, Xin Zhao
  • Patent number: 10353000
    Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Seok Yoon, Min-Su Kim, Chung-Hee Kim, Dae-Seong Lee, Hyun Lee, Matthew Berzins, James Lim
  • Patent number: 10228419
    Abstract: An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: March 12, 2019
    Assignee: INNOTIO INC.
    Inventor: Jaehoon Song
  • Patent number: 10088520
    Abstract: An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.
    Type: Grant
    Filed: January 13, 2018
    Date of Patent: October 2, 2018
    Assignee: INNOTIO INC.
    Inventor: Jaehoon Song
  • Patent number: 10078547
    Abstract: Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond Wong, Jie Zheng
  • Patent number: 10073139
    Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 11, 2018
    Assignee: Oracle International Corporation
    Inventors: Ali Vahidsafa, Sriram Anandakumar
  • Patent number: 9990453
    Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 5, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Namit K. Gupta, Jean-Marc A. Forey, Mahantesh D. Narwade, Horia A. Toma
  • Patent number: 9989593
    Abstract: The present invention relates to an arrangement for providing a testing environment for the testing of test objects. The testing environment includes a first test object receiving apparatus and a second test object receiving apparatus, each of which are configured to receive a test object. The testing environment also includes a connection interface configured to connect the first test object receiving apparatus and the second test object receiving apparatus to the testing environment. In one embodiment, the first test object receiving apparatus has a first external connection interface, and the second test object receiving apparatus has a second external connection interface, wherein said first and second external connection interfaces are configured to be selectively coupled with the connection interface of the testing environment.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: June 5, 2018
    Assignee: Airbus Deference and Space Gmbh
    Inventors: Philipp Wager, Bernd Schumacher
  • Patent number: 9927491
    Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: March 27, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9891279
    Abstract: An apparatus has a large block of synchronous logic arranged to include a first partition and a second partition. The first partition is configured to receive a first clock signal during a functional mode and during a test mode. The second partition is configured to receive the first clock signal during the functional mode, and the second partition configured to receive a second clock signal during a test mode. The second clock signal has the same frequency as the first clock signal. The second clock signal has a different phase from the first clock signal.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics International N.V.
    Inventor: Ajay Kumar Dimri
  • Patent number: 9885753
    Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 6, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Amit Sanghani, Farideh Golshan, Venkata Kottapalli, Milind Sonawane, Ketan Kulkarni
  • Patent number: 9864005
    Abstract: One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 9, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Douglas Carmean, Burton J. Smith
  • Patent number: 9835683
    Abstract: An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC can be drastically reduced compared to that required by conventional X-bounding methodologies.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, INC.
    Inventors: Priya Khandelwal, Himanshu Arora, Abhilash Kaushal
  • Patent number: 9746528
    Abstract: A method for detecting a series arc in a photovoltaic device, operating in direct current mode, including N (N=1 or N>1) photovoltaic modules, connected to a charging device having a capacitive behavior for the modules, the method including: a) detecting, across n of the N modules (1?n?N), time evolution of voltage; b) identifying a voltage variation between a first zone of stable voltage and a second zone of stable voltage for a duration of at least 5 ?s, which immediately follows the voltage variation; and c) determining whether the voltage variation is between a value Vmin higher than or equal to 0.2 V and a value Vmax lower than or equal to 20 V, with rise time of the variation between a duration Tmin higher than or equal to 0.5 ?s and a duration Tmax lower than or equal to 5 ?s.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: August 29, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Nicolas Chaintreuil, Vincent Chauve
  • Patent number: 9735791
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: August 15, 2017
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 9733307
    Abstract: A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerard M. Salem, Andrew A. Turner
  • Patent number: 9714981
    Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 9672305
    Abstract: A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Suparn Vats, Daniel J. Flees, Rohit Kumar
  • Patent number: 9641161
    Abstract: In some embodiments, a flip-flop is laid-out on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made of a first plurality of devices which are circumscribed by a master switch perimeter residing within the flip-flop region. Scan mux input circuitry is operably coupled to an input of the master switch circuitry. The scan mux input circuitry is made up of a second plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region and which is non-overlapping with the master switch perimeter. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter which resides within the flip-flop region and which is non-overlapping with both the master switch perimeter and the scan mux perimeter.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
  • Patent number: 9500703
    Abstract: There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Suresh Uppal, Manjunatha Prabhu, William McMahon
  • Patent number: 9495495
    Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Chung Lin, Ming-Zhang Kuo, Sang Hoo Dhong, Ho-Chieh Hsieh, Kuo Feng Tseng
  • Patent number: 9484968
    Abstract: An input signal having at least one modulated signal is captured. At least four analog sample streams are generated from the input signal. Each analog sample stream is generated by sampling the input signal at a frequency substantially equal to the frequency at which each other analog sample stream is generated and at a phase separate from that at which each other analog sample stream is generated. For each analog sample stream, multiple analog samples of the analog sample stream are combined to create a bandwidth adjusted signal. The bandwidth adjusted signals are jointly representative of the input signal.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: November 1, 2016
    Inventor: David K Nienaber
  • Patent number: 9455691
    Abstract: Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 27, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gaurav Goyal, Ashis Maitra, Ateet Mishra
  • Patent number: 9372501
    Abstract: A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventor: Shrinivas Venkatraman
  • Patent number: 9335377
    Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 10, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 9291676
    Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 22, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Atchyuth K Gorti, Aditya Jagirdar, Bikash Kumar Agarwal, Eric Quinnell
  • Patent number: 9264049
    Abstract: A semiconductor chip includes on-chip clock controllers (OCCs) capable of synchronizing multiple clock signals on the device. Each OCC controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators. The OCC receiving the slowest generated clock signal passes it through internal meta-stability registers and provides an external synchronization signal to the OCCs handling faster clock signals. These faster-clock OCCs can use the external synchronization signal to synchronize their clocks and generate testing clock pulses.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: February 16, 2016
    Assignee: STMicroelectronics International N.V.
    Inventors: Swapnil Bahl, Shray Khullar
  • Patent number: 9261560
    Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements. Each packing element includes k number of flip-flops. Each flip-flop of the k number of flip-flops receives a scan output of the M scan outputs and a phase-shifted scan clock of the k number of phase-shifted scan clocks, and generates a slow scan output of the kM slow scan outputs.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajesh Kumar Mittal, Mudasir Shafat Kawoosa, Sreenath Narayanan Potty
  • Patent number: 9242858
    Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: January 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel