Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) Patents (Class 714/726)
  • Patent number: 10896111
    Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 19, 2021
    Assignee: Arm Limited
    Inventors: Mohammadi Shabbirhussain Bharmal, Kauser Yakub Johar, Francisco João Feliciano Gaspar
  • Patent number: 10895998
    Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Hyun Hwang, Jong Chern Lee
  • Patent number: 10890623
    Abstract: Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Huott, Yuen Chan, Pradip Patel, Daniel Rodko
  • Patent number: 10884058
    Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 5, 2021
    Assignee: Cryptography Research, Inc.
    Inventor: Matthew Pond Baker
  • Patent number: 10877088
    Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Punit Kishore, Tomer Rafael Ben-Chen, Sharon Graif
  • Patent number: 10861394
    Abstract: A gate driving circuit and a light emitting display apparatus including the same has a simplified circuit that outputs a stable emission control signal. The gate driving circuit includes an emission control shift register including a plurality of emission control stages that each respectively supply an emission control signal to one of a plurality of emission control lines, each emission control line connected to at least one pixel of a plurality of pixels in a light emitting display panel. For an emission control line, when at least one of first input signal and the second input signal has a first voltage level, an emission control stage outputs the emission control signal having a gate-off voltage level, and when both of the first input signal and the second input signal have a second voltage level, the corresponding emission control signal has a gate-on voltage level.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 8, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: YongHo Jang
  • Patent number: 10862462
    Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Steven K. Hsu, Amit Agarwal, Simeon Realov
  • Patent number: 10830815
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Yu Huang
  • Patent number: 10825836
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10795399
    Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf Kuehnis, Enrico Carrieri
  • Patent number: 10796043
    Abstract: Systems and methods for re-ordering test patterns for circuit design or testing. A method includes receiving a set of scan chains and associated test patterns, and computing a penalty score for each test pattern in the set of test patterns. The method includes selecting a first pattern of the set of test patterns that has a lowest computed penalty score in the set of test patterns, and removing the first pattern from the set of test patterns and adding the first pattern to a set of ordered patterns. The method includes, for each remaining test pattern, computing an accumulated penalty score for each remaining pattern, selecting a next pattern of the set of test patterns that has a lowest accumulated penalty score in the set of test patterns, removing the next pattern from the set of test patterns, and adding the next pattern to the set of ordered patterns.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Jakub Janicki, Szczepan Urban
  • Patent number: 10788533
    Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
  • Patent number: 10769996
    Abstract: An electro-optical device includes a first data transfer line that intersects a scan line, a second data transfer line, a first transistor that controls coupling between the first data transfer line and the second transfer line. The two or more second data transfer lines are respectively coupled to the first data transfer line via first capacitors, and when a collection of pixel circuits that are coupled to the same first data transfer line via the second data transfer lines is referred to as a pixel string, the second data transfer lines are provided to pixel circuits less than the pixel circuits included in the pixel string.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Takeshi Koshihara
  • Patent number: 10739403
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a launch signal synchronized with a first clock signal in a first clock domain. The second circuit may be configured to (i) receive a second clock signal in a second clock domain and (ii) generate a plurality of pulses in each of a third clock signal and a fourth clock signal based on the second clock signal and the launch signal. A frequency of the pulses in the fourth clock signal may be an integer multiple of another frequency of the pulses in the third clock signal. An initial one of each of the pulses in the third clock signal and the fourth clock signal may be synchronized with each other.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 11, 2020
    Assignee: Ambarella International LP
    Inventors: Praveen Kumar Jaini, Karthik Narayanan Subramanian, SriHari Raju Saripella
  • Patent number: 10712389
    Abstract: A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10699054
    Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-hyun Lee
  • Patent number: 10685730
    Abstract: In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Seagate Technology LLC
    Inventors: Komal Shah, Jay Shah, Sachin Bastimane
  • Patent number: 10685157
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 10659017
    Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 19, 2020
    Assignee: Marvell International Ltd.
    Inventors: Krishnan S. Rengarajan, Alok Chandra, Chethan Ramanna
  • Patent number: 10650905
    Abstract: An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Iwao
  • Patent number: 10613144
    Abstract: A semiconductor device includes a processing block which comprises one or more intellectual property (IP) blocks; a scan chain which is electrically connected to the IP blocks, wherein the scan chain block has a scan in (SI) terminal and a scan out (SO) terminal; a pattern generating circuit which generates a data pattern having a plurality of bits and inputs the data pattern to the scan in (SI) terminal of the scan chain; and an analyzing circuit which determines the degree of degradation of each of the IP blocks based on a result pattern output from the scan out (SO) terminal of the scan chain.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suh Ho Lee, Ihor Vasyltsov
  • Patent number: 10608643
    Abstract: A method for manufacturing a semiconductor device includes forming a circuit including a plurality of flip-flops, a plurality of first switches, a second switch and a signal line on a wafer, the flip-flops being connected in series through the first switches, respectively, and the signal line being connected to the second switch, and being configured to supply a signal in parallel to the flip-flops; testing the flip-flops by turning off the first switches, turning on the second switch, and supplying a test signal in parallel through the signal line to the flip-flops; and cutting at least one interconnect of a switch portion in the circuit, the switch portion including the first switches and the second switch, so that the first switch is turned on and the second switch is turned off.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 31, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Koji Shinohara
  • Patent number: 10605863
    Abstract: Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 31, 2020
    Assignee: Synopsys, Inc.
    Inventors: Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
  • Patent number: 10608763
    Abstract: Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: John G. Rell, III, Michael W. Harper, Mack W. Riley, Michael B. Spear
  • Patent number: 10585783
    Abstract: An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyung-Il Woo
  • Patent number: 10567993
    Abstract: There is provided a method for managing buffer status reporting for a wireless communication device in a wireless communication system. The method comprises checking (S1) condition(s) for suppressing at least one Buffer Status Report, BSR, which is up for transmission, and suppressing (S2) the BSR if the condition(s) is/are fulfilled, wherein the BSR is suppressed when the BSR indicates less than or equal to a first threshold amount of bytes and/or when one or more previous BSRs indicate less than or equal to a second threshold amount of bytes.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 18, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Mattias Bergström, Magnus Stattin
  • Patent number: 10551435
    Abstract: Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 4, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nitin Parimi, Krishna Vijaya Chakravadhanula, Patrick Wayne Gallagher, Vivek Chickermane, Brian Edward Foutz
  • Patent number: 10551436
    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin
  • Patent number: 10545188
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10545190
    Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
  • Patent number: 10527674
    Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
  • Patent number: 10520549
    Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 31, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
  • Patent number: 10520550
    Abstract: A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Givargis Avareh Danialy, Martin Keim
  • Patent number: 10520551
    Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: December 31, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10497317
    Abstract: An integration driver includes a plurality of stages. Each of the plurality of stages includes a scan signal generator including first to third nodes and a fifth node and an emission control signal generator including a fourth node and sixth node. The scan signal generator is configured to generate a first signal provided to a first node, a second signal provided to a second node, and a third signal provided to a third node using a first clock signal, a second clock signal, and a start signal or a carry signal, and generate a scan signal using the second signal and the third signal. The emission control signal generator is configured to generate a fourth signal provided to a fourth node using the third signal and the second clock signal, and generate an emission control signal using the first signal and the fourth signal.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Keun Lim, Ji-Eun Park, Young-Wook Yoo, Hassan Kamal
  • Patent number: 10436840
    Abstract: A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 8, 2019
    Assignee: NVIDIA Corp.
    Inventors: Jau Wu, Saurabh Gupta
  • Patent number: 10429440
    Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li
  • Patent number: 10417104
    Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 17, 2019
    Assignee: NXP USA, INC.
    Inventors: Colin MacDonald, Alexander B. Hoefler, Jose A. Lyon, Chris P. Nappi, Andrew H. Payne
  • Patent number: 10393804
    Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni
  • Patent number: 10394307
    Abstract: Provided is an information processing apparatus including a processor configured to control a system of the information processing apparatus, a power source controller configured to perform control of power supply to the system and to turn off a power source of the power source controller in standby mode in which a power source of the processor is turned off, a memory configured to store information in standby mode, and a power supply unit configured to perform power supply to the memory in standby mode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 27, 2019
    Assignee: SONY CORPORATION
    Inventors: Takeshi Masuda, Toshimasa Tsuchida, Takahiro Imai, Yoshiyuki Tanaka, Kiyotaka Akasaka, Kenichi Onishi, Norifumi Yoshida
  • Patent number: 10386414
    Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 20, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Marc Daveau, Philippe Roche, Didier Fuin
  • Patent number: 10381093
    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Hoe Sam Jeong
  • Patent number: 10375618
    Abstract: An apparatus which transfers information addressed to a master node, comprises a generation unit configured to generate an assessment value representing logical proximity to the master node; a transmit unit that sends/receives the assessment value to/from other apparatuses; and a communication unit that, when this apparatus is an apparatus that is logically closest to the master node within a communication range, receive information addressed to the master node from other apparatuses, otherwise, transmit information addressed to the master node to the logically closest apparatus, wherein the communication unit is configured to generate a delay time based on the assessment value when transferring the information received from the other apparatuses to yet another apparatus.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 6, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Ryokichi Onishi, Masaaki Sasahara
  • Patent number: 10366253
    Abstract: A Hardware-Embedded Delay Physical Unclonable Function (“HELP PUF”) leverages entropy by monitoring path stability and measuring path delays from core logic macros. Reliability and security enhancing techniques for the HELP PUF reduce bit flip errors during regeneration of the bitstring across environmental variations and improve cryptographic strength along with the corresponding difficulty of carrying out model building attacks. A voltage-based enrollment process screens unstable paths on normally synthesized (glitchy) functional units and reduces bit flip errors by carrying out enrollment at multiple supply voltages controlled using on-chip voltage regulators.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: July 30, 2019
    Assignee: STC.UNM
    Inventor: James Plusquellic
  • Patent number: 10347351
    Abstract: Discussed are a display device and a method of driving the same. The display device can include a panel in which a pixel is formed in each of a plurality of intersection areas between a plurality of gate lines and a plurality of data lines, a built-in gate driver built into a non-display area of the panel, and configured to include a shift register including a plurality of scan stages which output a scan pulse, and a timing controller configured to generate first to nth clocks, a reset signal, and a start signal. In initial driving of the built-in gate driver, the timing controller continuously supplies a pulse of the reset signal to the plurality of scan stages while a pulse of the nth clock and a pulse of the first clock to a pulse of the (n?1) clock are each output once in a first frame.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 9, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Eun Cheol Eom, Young Ho Kim
  • Patent number: 10346557
    Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John Waicukauski
  • Patent number: 10345380
    Abstract: A method and circuit are provided for implementing enhanced scan data testing with over masking removal in an on product multiple input signature register plus (OPMISR+) test due to common Channel Mask Scan Registers (CMSRs) loading, and a design structure on which the subject circuit resides. An OPMISR plus satellite includes a multiple input signature register (MISR) for data collection and a plurality of associated scan channels. A common Channel Mask Scan Registers (CMSR) logic is used with the multiple input signature register (MISR). Unique CMSR data is loaded into at least one OPMISR plus satellite for implementing enhanced scan data testing. Scan pausing is used to reduce the amount of CMSR scan load data by loading the unique CMSR data only when needed.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Matthew B. Schallhorn, Mary P. Kusko, Amanda R. Kaufer, Michael J. Hamilton
  • Patent number: 10338139
    Abstract: According to one general aspect, in a large digital integrated circuit with on-chip scan test compression hardware, an apparatus may include a digital circuit receiver circuit and a scan chain reorder circuit. The digital circuit receiver circuit configured to: receive a circuit model file that includes logic circuits that are represented by respective cells, wherein a plurality of cells are arranged in an ordered scan chain, and insert, in to the circuit model file, a dummy cell as an end cell at an end of the ordered scan chain. The scan chain reorder circuit configured to reorder the ordered scan chain to a reordered scan chain based, wherein the scan-chain reorder circuit is configured to maintain a start cell and an end cell of the ordered scan chain as a start cell and an end cell of the reordered scan chain.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guangyuan Kelvin Ge, Yu-Ming Chiang, Rajesh Rajagopalan Kashyap
  • Patent number: 10338930
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 2, 2019
    Assignee: Eta Compute, Inc.
    Inventors: Ben Melton, Bryan Garnett Cope
  • Patent number: 10331506
    Abstract: Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 25, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Vivek Chickermane, Christos Papameletis, Krishna Vijaya Chakravadhanula, Brian Edward Foutz