Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

Abstract: An electronic system includes: a host; and a storage device configured to exchange data with the host using an interface protocol. The host provides a fault insertion command, including a fault type, a target location, and a fault condition, to the storage device, based on the interface protocol. The storage device performs a fault detection operation, selected based on the fault type among an assert code execution operation, a memory polling operation, an interrupt polling operation, and a latency detection operation, on the target location in response to the fault insertion command, and stores a snapshot of the storage device when the fault condition is detected as a result of performing the fault detection operation. The host obtains the stored snapshot using the interface protocol, and debugs the storage device using the obtained snapshot.

Abstract: Scan forest can effectively compress test data volume, however, CPU time and memory consumption must be well-controlled to handle industrial designs. The present disclosure provides a method to establish a scan forest, which reduces memory consumption and CPU time significantly. A new low-power test application scheme is proposed, which does not need to increase the test application cost but can be of help to compress test data volume. Another new test application algorithm is proposed to reduce capture cycle power and shift cycle power by just doubling the test application time, which does not sacrifice the test data compression performance.

Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

Abstract: Methods and apparatuses for reporting buffer status are disclosed. A method of reporting buffer status, comprising: sending a control element including buffer status information for a logical channel group on which first packets transmit and buffer status information for a corresponding logical channel group on which duplicated packets transmit.

Abstract: A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

Abstract: Flexible input/output (I/O) allocation techniques for integrated circuit scan testing are disclosed. The techniques implement configurable definition of the core circuitry blocks comprising the scan domain under test and their mapping to the scan test pads. Scan testing of the scan domain is performed by receiving a test pattern on the set of one or more scan-in test pads, transmitting the test pattern to the scan domain via the set of one or more scan input channels, receiving a test response on the set of one or more scan output channels, and transmitting the test response to the set of one or more scan-out test pads.

Abstract: The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

Abstract: Systems, methods, apparatuses, and computer program products for physical broadcast channel extension are provided. For example, a method can include mapping, by the network element, symbols of a physical channel to a first set of resource elements. The method can also include identifying, by the network element, a portion of the symbols of the physical channel mapped outside a second set of resource elements. The second set of resource elements can be a subset of the first set of resource elements, The method can further include preparing, by the network element, replacement symbols corresponding to a first portion of the physical channel outside the second set of resource elements. The method can additionally include mapping, by the network element, the replacement symbols to the second set of resource elements in extension symbols. The method can also include transmitting, by the network element, the physical channel and the extension symbols.

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

Abstract: A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.

Abstract: A method for determining the distance between an authentication device carried by a user and a motor vehicle, each including a wireless communication module so as to exchange a data frame, the data frame being modulated by changing the phase of a reference signal. The method includes the following steps of: the vehicle receiving a modulated reference signal, sent by the device, demodulating the received signal in order to extract an in-phase component and a quadrature component therefrom, computing the power value of the signal on the basis of the maximum amplitude value of the in-phase component and of the maximum amplitude value of the quadrature component, and determining the distance between the device and the vehicle on the basis of the computed power value.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising generating a super management unit (SMU) memory access command; splitting the SMU memory access command into a plurality of management unit (MU) memory access commands; indexing, in an index data structure, each MU memory access command of the plurality of MU memory access commands; issuing, to the memory device, a sequence of MU memory access commands from the plurality of MU memory access commands; receiving an indication that a MU memory access command from the sequence of MU memory access commands is completed; and responsive to determining that the completed MU memory access command satisfies a criterion, issuing an available MU memory access command based on an index value of the available MU memory access command.

Abstract: A display device can include a display panel configured to display an image through sub pixels, a first scan driver configured to supply a plurality of first scan signals to a plurality of first gate lines connected to the sub pixels, and an emission control driver configured to supply a plurality of emission control signals to a plurality of third gate lines connected to the sub pixels. The emission control driver includes a plurality of emission control stages configured to supply the plurality of emission control signals, respectively. Each of the plurality of emission control stages can include an output buffer including a first output transistor configured to output a clock signal to an output line by controlling a Q node, and a second output transistor configured to output a high potential power supply voltage to the output line by controlling a QB node.

Abstract: An electronic device is provided. The electronic device includes a pixel array, a gate driver and a bias control signal driver. The pixel array includes a pixel unit. The gate driver is configured to generate a plurality of gate control signals. The bias control signal driver is electrically connected to the pixel unit and the gate driver. The bias control signal driver is configured to generate a bias signal to drive the pixel unit according to a part of the plurality of gate control signals.

Abstract: A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Abstract: Disclosed are a pixel circuit, a driving method of the pixel circuit and a display device, the pixel circuit including a reset unit, a voltage writing unit and a light-emitting control unit, the reset unit is connected to a reset control signal terminal, and resets the pixel circuit under the control of the reset control signal; the voltage writing unit stores a data signal and a threshold voltage of a driving transistor under the control of the scan control signal; the light-emitting control unit is connected to a light-emitting control signal terminal and includes the driving transistor, and use the data signal and the threshold voltage to generate a current under control of the light-emitting control signal; the light-emitting control unit includes a first type transistor, the reset unit and the voltage writing unit include a second type transistor different from the first type transistor.

Abstract: A scan driver includes a plurality of stages, each of the plurality of stages including: a first controller to control voltage levels of a first control node and a second control node in response to a first start signal and a second start signal, and to output a first carry signal; a second controller to control voltage levels of a third control node and a fourth control node in response to the first start signal and the second start signal, and to output a second carry signal; and an output circuit including: a pull-up transistor having a gate connected to the first control node; and a pull-down transistor having a gate connected to the third control node. The output circuit is to output a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor.

Abstract: A circuit, for generating ultrahigh-precision digital pulse signals comprises: a pulse edge control circuit used for delaying a signal on an input pin and accurately controlling positions of a rising edge and a falling edge of the pulse signal to accurately control the width of pulses and generate ultrahigh-precision pulses; a static calibration circuit used for calculating step size information representing the relationship between a work clock period of a system and a delay of delay cells in the pulse edge control circuit when the system is powered on to work, and storing the step size information, wherein the step size information is the number of delay cells through which the signal is propagated and passes within one system clock period; and a dynamic calibration circuit used for dynamically calculating step size information when a rising edge or a falling edge of each pulse in the input pin arrives.

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

Abstract: The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Abstract: A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

Abstract: The present disclosure relates to an apparatus comprising: a host device or a System-on-Chip: a memory component having an independent structure and including at least an array of memory cells organized in sub-arrays with associated decoding and sensing circuitry; a JTAG interface in said at least an array of memory cells including a boundary-scan architecture; an instruction register in said boundary-scan architecture of the JTAG interface including at least a couple of Bits indicative of the presence of a Test Data Input (TDI) signal. The apparatus has an extended TDI functionality using the data IO to improve the overall performances. A method for improving the communication between a Host or SoC device and an associated independent memory component is also disclosed.

Abstract: The present disclosure describes systems and methods for augmented reality inventory tracking and analysis that identifies devices based on a combination of features, retrieves a configuration or other characteristics of the selected device and presents the configuration as a rendered overlay on a live image from the camera.

Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.

Abstract: To enable detection of occurrence of abnormality in a more preferable manner when the abnormality occurs in signal processing applied to pixel signals.

Abstract: Provided herein is a method for registering an IoT device with a DNS registry. The method can include obtaining, at a DNS server, an identifier, IP address, and a public key of an asymmetric key pair associated with the IoT device from a network gateway device that is in communication with the IoT device, wherein the asymmetric key pair is provisioned onto the IoT device and an associated private key stored within a memory of the IoT device at a time that IoT device is manufactured or during a predetermined time window after manufacturing; creating at least one DNS record for the IoT device; assigning a domain name associated with the internet protocol (“IP”) address to the IoT device; storing the identifier, IP address, the domain name, and the public key in the at least one DNS record; and providing confirmation of the registration to the IoT device.

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract: A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether an error exists in the plurality of scan chains or not according to the plurality of scan output data by a decoding circuit.

Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Abstract: Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

Abstract: A safety analysis method is based on a safety-specific design structural analysis and cone of influence (COI) that does not require fault simulation. The method for performing a safety analysis of an integrated circuit based on a safety-specific design structural analysis and cone of influence comprises generating with a processor a computed set of basic design elements by intersecting two transitive cones of influence, wherein a first cone of influence is a transitive fanin cone of influence starting from a TO element and a second cone of influence is a transitive fanout cone of influence starting from a FROM element.

Abstract: A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

Abstract: The invention relates to a microchip with a multiplicity of reconfigurable test structures, wherein the microchip has a test input (TDI) and a test output (TDO), wherein the multiplicity of test structures can be connected to the test input (TDI) and the test output (TDO), wherein one intermediate memory is provided for each of the multiplicity of test structures, wherein each of the multiplicity of test structures can be tested separately and concurrently with the aid of the respective intermediate memory and a corresponding individual control.

Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

Abstract: A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a ?-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the ?-bit protected Obfuscation Key generated by the LFSR, and output k??×??-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

Abstract: To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit.

Abstract: There is provided a method for managing buffer status reporting for a wireless communication device in a wireless communication system. The method comprises checking (S1) condition(s) for suppressing at least one Buffer Status Report, BSR, which is up for transmission, and suppressing (S2) the BSR if the condition(s) is/are fulfilled, wherein the BSR is suppressed when the BSR indicates less than or equal to a first threshold amount of bytes and/or when one or more previous BSRs indicate less than or equal to a second threshold amount of bytes.