Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) Patents (Class 714/726)
  • Patent number: 11223344
    Abstract: A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: January 11, 2022
    Inventors: Raheel Azmat, Jaehyoung Lim, Taehyung Kim, Jinwoo Jeong, Jaeseok Yang
  • Patent number: 11222098
    Abstract: A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a ?-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the ?-bit protected Obfuscation Key generated by the LFSR, and output k??×??-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: January 11, 2022
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Mark M. Tehranipoor, Domenic J. Forte, Farimah Farahmandi, Adib Nahiyan, Fahim Rahman, Mohammad Sazadur Rahman
  • Patent number: 11209880
    Abstract: To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 11201621
    Abstract: A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 14, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu-Cheng Lo, Yu-Jen Pan, Wei-Chih Shen, Chien-Wei Shih, Jiunn-Way Miaw
  • Patent number: 11199580
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: December 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11193974
    Abstract: A failure diagnostic apparatus includes a path calculation unit which calculates, for each input pattern to a diagnosis target cell, a path affecting an output value of the diagnosis target cell when a failure is assumed as an activation path, a path classification unit which classifies the activation path associated with the input pattern for which the diagnosis target cell has passed a test and the activation path associated with the input pattern for which the diagnosis target cell has failed the test, a path narrowing unit which calculates a first failure candidate path, a second failure candidate path and a normal path of the diagnosis target cell based on classified activation paths, and a result output unit which outputs information on the first failure candidate path, the second failure candidate path and the normal path.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihisa Funatsu, Kazuki Shigeta
  • Patent number: 11176030
    Abstract: Aspects of the disclosure relate to conducting automated software testing using a centralized controller and one or more distributed test host servers. A computing platform may receive a test execution request. Subsequently, the computing platform may retrieve test specification details information and may identify one or more tests to execute. Then, the computing platform may generate one or more remote test execution commands directing a test host server farm to execute the one or more tests. In addition, generating the one or more remote test execution commands may include constructing one or more command line instructions to be executed by the test host server farm and inserting the one or more command line instructions into the one or more remote test execution commands. Thereafter, the computing platform may send the one or more remote test execution commands to the test host server farm.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Bank of America Corporation
    Inventor: Gedaliah Friedenberg
  • Patent number: 11144677
    Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventors: Stefan Doll, Thomas Henry Luedeke, Nikila Krishnamoorthy, Hubert Glenn Carson, Jr., Anurag Jindal, Hilario Manuel Garza, Kamel Musa Khalaf, Joel Ray Knight, Adrian Lee Carleton
  • Patent number: 11143703
    Abstract: A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type. A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 12, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Michael Fridburg, Erez Menahem, Peter Brokhman
  • Patent number: 11137446
    Abstract: A test apparatus is configured to test a DUT that does not support synchronous control from an external circuit. A main controller is configured based on an architecture that tests a device by synchronous control with the main controller itself as the master. A MIU is configured as an interface between the main controller and the DUT. The MIU establishes asynchronous control between it and the DUT with the DUT as the master, and establishes control between it and the main controller with the main controller as the master.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANTEST CORPORATION
    Inventors: Shuichi Inage, Kazuhiro Iezumi, Tomoyuki Itakura, Keisuke Kusunoki, Yoshihiro Kato, Kazuhiro Tsujikawa, Naoya Kimura, Yuki Watanabe, Yuichiro Harada, Koji Miyauchi
  • Patent number: 11132483
    Abstract: According to an embodiment, a method for forming an electronic circuit is provided including forming a netlist of an electronic circuit having a multiplicity of flip-flops, selecting groups of flip-flops from the multiplicity of flip-flops, providing, for each selected group of flip-flops, an error detection circuit for the flip-flops of the group and forming the electronic circuit based on the netlist to include the provided error detection circuits.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Marco Bucci, Raimondo Luzzi
  • Patent number: 11120733
    Abstract: A display device includes a plurality of pixels. Each pixel includes a light emitting unit and a driving circuit. The driving circuit drives the light emitting unit in a pulse width modulation mode to present a first gray level lower than or equal to a predetermined gray level, and drives the light emitting unit in a current mode to present a second gray level higher than the predetermined gray level.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 14, 2021
    Assignee: InnoLux Corporation
    Inventor: Kazuyuki Hashimoto
  • Patent number: 11113444
    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 7, 2021
    Inventors: Sandeep Kumar Goel, Yun-Han Lee, Vinay Kotha, Ankita Patidar
  • Patent number: 11092645
    Abstract: A test pattern is shifted into scan chains in a circuit in a first direction. The scan cells on each of the scan chains are further coupled to corresponding scan cells on two other scan chains in the scan chains such that data bits stored in the scan cells can be shifted circularly in a second direction orthogonal to the first direction based on a control signal. The loaded test pattern is then shifted in the second direction for a number of clock cycles equal to the number of the scan chains. The test pattern is then shifted in the first direction out of the scan chains to generate a chain test result. Faulty scan cell candidates on faulty scan chains may be determined based on part of the chain test result for one of good scan chains.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 17, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Wu-Tung Cheng, Yu Huang
  • Patent number: 11094395
    Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
  • Patent number: 11087680
    Abstract: A display device comprises a pixel area in which a plurality of pixels are arranged, and a dummy pixel area which is provided around the pixel area and in which a plurality of dummy pixels are arranged. Each of the pixel and the dummy pixel includes a light-emitting element including a first electrode and a second electrode, and a driving transistor. The first electrode of the light-emitting element is connected to the driving transistor in the pixel, and in the dummy pixel, the light-emitting element is not connected to the driving transistor, a first potential is supplied to the first electrode, a second potential is supplied to the second electrode, and the light-emitting element does not emit light at a potential difference between the first potential and the second potential.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 10, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiromasa Tsuboi, Yasushi Matsuno, Takehiko Soda
  • Patent number: 11067623
    Abstract: A test system includes a plurality of test core devices and a plurality of first buses. The plurality of test core devices are electrically connected to a device under test (DUT). The plurality of first buses are electrically connected to the test core devices, where at least one set of test core devices selected from the plurality of test core devices are merged to be a merged test core device through one or more of the plurality of first buses.
    Type: Grant
    Filed: May 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Test Research, Inc.
    Inventors: Ming-Hsien Liu, Hsin-Wei Huang
  • Patent number: 11056046
    Abstract: A display device includes: a data line; a first scan line configured to sequentially receive a first scan pulse and a second scan pulse, each of which has a turn-on level; an emission line configured to sequentially receive a first emission pulse, a second emission pulse, a third emission pulse, and a fourth emission pulse, each of which has a turn-on level; and a pixel configured to receive the data signal according to the first and second scan pulses, the pixel being further configured to emit light based on the received data signal according to the first to fourth emission pulses, wherein the first emission pulse is generated before the first scan pulse, the second emission pulse and the third emission pulse are generated in a period between the first scan pulse and the second scan pulse, and the fourth emission pulse is generated after the second scan pulse.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: July 6, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min Ku Lee, Ji Hyun Ka, Eun Ju Kim, Kwang Sae Lee
  • Patent number: 11025246
    Abstract: A switch control circuit and a switch control system includes a plurality of parallel-connected signal processing units. A first voltage signal and second voltage signal control turning-on and turning-off of the first controllable switch, and converting the first voltage signal into a third voltage signal; and the third voltage signal being connected with the first port of the controller; and the controller, configured to send a switch control instruction to a to-be-controlled terminal based on the third voltage signal. This circuit converts a electrical signal of a high voltage in strong electricity into a stable electrical signal of a low voltage in weak electricity, implements multiplex switch control in conjunction with the controller, and only processes voltage signals in the whole circuit, thereby avoiding processing signals of a plurality of types, and guaranteeing the reliability of the multiplex switch control.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 1, 2021
    Assignee: Wenzhou MTLC Electric Appliances Co., Ltd.
    Inventors: Lidong Ni, Wei Gao
  • Patent number: 11016145
    Abstract: An integrated circuit sensor can have a test program generator that is configured to receive a portion of a scan vector, where the scan vector includes a test mode signal and a scan enable signal. The test program generator is configured to retrieve a launch-off-capture test sequence from the scan vector and use the launch-off-capture test sequence and the test mode signal to generate a launch-off-capture test signal. A test signal generator is configured to generate a launch-off-shift test signal using the launch-off-capture test signal and the scan enable signal. A built-in self-test circuit is configured to test the integrated circuit sensor using the launch-off-shift test signal.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Ignacio Lesser, Nicolas Rigoni, Octavio H. Alpago, Lautaro Casella
  • Patent number: 10997891
    Abstract: A display panel, a method for driving a display panel and a display apparatus are provided. The display panel includes a plurality of pixels, a plurality of gate lines and a plurality of data lines; a multiplexer including a plurality of selectors; a plurality of control lines electrically connected to the plurality of selectors, and a plurality of shift register groups. Each of the plurality of control lines is used to control an output terminal of the selector to output a data signal to the data line. Each shift register group includes a plurality of cascaded shift registers and each shift register is electrically connected to at most two of the plurality of gate lines. There are N rows of pixels between pixels corresponding to two of the plurality of gate lines electrically connected to a same shift register and N is a positive integer.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 4, 2021
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Mengmeng Zhang, Xingyao Zhou, Yue Li, Shuai Yang
  • Patent number: 10996271
    Abstract: An IC includes testing circuitry including a Test Access Port (TAP) controller and Segment-Insertion-Bit circuits (SIBs) arranged in multiple hierarchy levels. Some of the SIBs are connected to hardware units, and some of the SIBs are root-SIBs that connect between neighbor hierarchy levels. A test bus runs in a daisy-chained loop path starting at the TAP controller, passing via at least some of the SIBs and ending at the TAP controller. Each root-SIB has an Open state and a Closed state. The TAP controller, for a selected subset of the hardware units that are to be tested, selects one or more root-SIBs that, when set to the Open state, make the selected subset of hardware units reachable by the test bus, and sends via the daisy-chained test bus a data stream comprising one or more instructions that set two or more of the selected root-SIBs to the Open state.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: May 4, 2021
    Assignee: APPLE INC.
    Inventor: Chananiel Weinraub
  • Patent number: 10991331
    Abstract: The present disclosure provides a driving circuit and driving method for a display panel and a display device, an output scanning signal is controlled through a scanning signal control circuit, such that a first-array-substrate-row driving circuit on a first lateral side of the display panel outputs a scanning signal according to a first enabling control signal, and a second-array-substrate-row driving circuit on a second lateral side of the display panel outputs a scanning signal according to a second enabling control signal, and driving of one side or two sides of the display panel is implemented.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 27, 2021
    Assignee: HKC CORPORATION LIMITED
    Inventor: Feilin Ji
  • Patent number: 10977400
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Patent number: 10976365
    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10955472
    Abstract: An integrated circuit includes first and second cores. Each core has a power-switchable portion in a first power domain in which an operating power is turned on or off in response to a power control signal. The first power domain includes a first scan chain, and the first power domain also includes a plurality of outputs. Each core also includes an always-on portion in a second power domain in which the operating power is maintained during testing of the integrated circuit. The second power domain also has a second scan chain. The second power domain further includes respective isolation gates coupled to the plurality of outputs of the first power domain, and the second scan chain includes a respective wrapper cell coupled to some isolation gates. The integrated circuit is configured to power off and isolate the power-switchable portion in the first power domain based on a scan test result.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Dan Trock, Valentin Bader, Shlomi Vilozny, Shimon Rahamim, Danny Sapoznikov, Yair Armoza, Itai Avron
  • Patent number: 10955474
    Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin
  • Patent number: 10955467
    Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 23, 2021
    Assignee: NXP USA, INC.
    Inventors: Kumar Abhishek, Srikanth Jagannathan, Hector Sanchez
  • Patent number: 10949295
    Abstract: A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Adam J. McPadden, Anuwat Saetow, David D. Cadigan
  • Patent number: 10896111
    Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 19, 2021
    Assignee: Arm Limited
    Inventors: Mohammadi Shabbirhussain Bharmal, Kauser Yakub Johar, Francisco João Feliciano Gaspar
  • Patent number: 10895998
    Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Hyun Hwang, Jong Chern Lee
  • Patent number: 10890623
    Abstract: Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William Huott, Yuen Chan, Pradip Patel, Daniel Rodko
  • Patent number: 10884058
    Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 5, 2021
    Assignee: Cryptography Research, Inc.
    Inventor: Matthew Pond Baker
  • Patent number: 10877088
    Abstract: A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: December 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Punit Kishore, Tomer Rafael Ben-Chen, Sharon Graif
  • Patent number: 10862462
    Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Steven K. Hsu, Amit Agarwal, Simeon Realov
  • Patent number: 10861394
    Abstract: A gate driving circuit and a light emitting display apparatus including the same has a simplified circuit that outputs a stable emission control signal. The gate driving circuit includes an emission control shift register including a plurality of emission control stages that each respectively supply an emission control signal to one of a plurality of emission control lines, each emission control line connected to at least one pixel of a plurality of pixels in a light emitting display panel. For an emission control line, when at least one of first input signal and the second input signal has a first voltage level, an emission control stage outputs the emission control signal having a gate-off voltage level, and when both of the first input signal and the second input signal have a second voltage level, the corresponding emission control signal has a gate-on voltage level.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 8, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: YongHo Jang
  • Patent number: 10830815
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Yu Huang
  • Patent number: 10825836
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10796043
    Abstract: Systems and methods for re-ordering test patterns for circuit design or testing. A method includes receiving a set of scan chains and associated test patterns, and computing a penalty score for each test pattern in the set of test patterns. The method includes selecting a first pattern of the set of test patterns that has a lowest computed penalty score in the set of test patterns, and removing the first pattern from the set of test patterns and adding the first pattern to a set of ordered patterns. The method includes, for each remaining test pattern, computing an accumulated penalty score for each remaining pattern, selecting a next pattern of the set of test patterns that has a lowest accumulated penalty score in the set of test patterns, removing the next pattern from the set of test patterns, and adding the next pattern to the set of ordered patterns.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Jakub Janicki, Szczepan Urban
  • Patent number: 10795399
    Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrik Eder, Rolf Kuehnis, Enrico Carrieri
  • Patent number: 10788533
    Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Kishore Kasichainula, Satheesh Chellappan, Lay Chen Ong, Harish G. Kamat
  • Patent number: 10769996
    Abstract: An electro-optical device includes a first data transfer line that intersects a scan line, a second data transfer line, a first transistor that controls coupling between the first data transfer line and the second transfer line. The two or more second data transfer lines are respectively coupled to the first data transfer line via first capacitors, and when a collection of pixel circuits that are coupled to the same first data transfer line via the second data transfer lines is referred to as a pixel string, the second data transfer lines are provided to pixel circuits less than the pixel circuits included in the pixel string.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hitoshi Ota, Takeshi Koshihara
  • Patent number: 10739403
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a launch signal synchronized with a first clock signal in a first clock domain. The second circuit may be configured to (i) receive a second clock signal in a second clock domain and (ii) generate a plurality of pulses in each of a third clock signal and a fourth clock signal based on the second clock signal and the launch signal. A frequency of the pulses in the fourth clock signal may be an integer multiple of another frequency of the pulses in the third clock signal. An initial one of each of the pulses in the third clock signal and the fourth clock signal may be synchronized with each other.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 11, 2020
    Assignee: Ambarella International LP
    Inventors: Praveen Kumar Jaini, Karthik Narayanan Subramanian, SriHari Raju Saripella
  • Patent number: 10712389
    Abstract: A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10699054
    Abstract: An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-hyun Lee
  • Patent number: 10685730
    Abstract: In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 16, 2020
    Assignee: Seagate Technology LLC
    Inventors: Komal Shah, Jay Shah, Sachin Bastimane
  • Patent number: 10685157
    Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ankita Patidar, Sandeep Kumar Goel, Yun-Han Lee
  • Patent number: 10659017
    Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 19, 2020
    Assignee: Marvell International Ltd.
    Inventors: Krishnan S. Rengarajan, Alok Chandra, Chethan Ramanna
  • Patent number: 10650905
    Abstract: An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Iwao
  • Patent number: 10613144
    Abstract: A semiconductor device includes a processing block which comprises one or more intellectual property (IP) blocks; a scan chain which is electrically connected to the IP blocks, wherein the scan chain block has a scan in (SI) terminal and a scan out (SO) terminal; a pattern generating circuit which generates a data pattern having a plurality of bits and inputs the data pattern to the scan in (SI) terminal of the scan chain; and an analyzing circuit which determines the degree of degradation of each of the IP blocks based on a result pattern output from the scan out (SO) terminal of the scan chain.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suh Ho Lee, Ihor Vasyltsov