Signature Analysis Patents (Class 714/732)
  • Patent number: 11928210
    Abstract: This document described a module and method for monitoring systems of a host device for anomalous activities or security weaknesses. The module is configured to passively monitor the content contained within the main memory of the host device and data received by hardware components in the host device for anomalies or security weaknesses. When such anomalies are detected, the module will then initiate countermeasures to prevent the anomalies from affecting the host device and/or any storage/peripheral devices linked to the host device.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: March 12, 2024
    Assignee: FLEXXON PTE. LTD.
    Inventors: Mei Ling Chan, Nizar Bouguerra
  • Patent number: 11879941
    Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11863820
    Abstract: Example device meters disclosed herein include a signature reporter to report, to a data processor, media signatures of a first type to monitor media presented by a media device Disclosed example device meters also include a signature generator to (i) generate the media signatures of the first type, (ii) generate media signatures of a second type, different from the first type, to continue monitoring the media presented by the media device after receipt, from the data processor, of an indication that a first media signature of the first type is associated with first reference media, and (iii) in response to detection at the device meter of a change in a source of the media presented by the media device, revert to generation of the media signatures of the first type to monitor the media presented by the media device.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 2, 2024
    Assignee: The Nielsen Company (US), LLC
    Inventor: Francis Gavin McMillan
  • Patent number: 11863821
    Abstract: Example local devices disclosed herein include memory including a set of reference fingerprints corresponding to media, the set of reference fingerprints from a remote device different from the local device and one or more processor circuits to execute machine readable instructions to generate a monitored fingerprint of the media presented at a location and compare the monitored fingerprint to at least some of the set of reference fingerprints from the remote device. Additionally, the one or more processor circuits are to determine an amount of time that has passed since the media started and after a match between the monitored fingerprint and one or more reference fingerprints of the set of reference fingerprints, cause transmission of audience measurement information to identify the media, the audience measurement information including data indicative of the amount of time that has passed since the media started.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: January 2, 2024
    Assignee: The Nielsen Company (US), LLC
    Inventor: Francis Gavin McMillan
  • Patent number: 11854643
    Abstract: A signal processing system includes a digital signal processing circuit, a power management unit, and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. When in a calibration mode the digital control circuit controls the power management unit to set the first voltage at a minimum preset value, controls the digital signal processing circuit to operate under a first calibration target frequency, triggers the digital signal processing circuit to perform a built-in self-test, raises the first voltage when the built-in self-test fails, triggers the digital signal processing circuit to perform the built-in self-test again, and stores the first calibration target frequency and a value of the first voltage corresponding to the first calibration target frequency to a non-volatile memory when the built-in self-test has succeeded.
    Type: Grant
    Filed: May 16, 2021
    Date of Patent: December 26, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Pin Chang, Tsung-Peng Chuang
  • Patent number: 11815555
    Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 14, 2023
    Assignee: Siemens Industry Software Inc.
    Inventors: Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer, Bartosz Wlodarczak
  • Patent number: 11580055
    Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning, Paul D. Dlugosch
  • Patent number: 11573921
    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA Corporation
    Inventors: Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P Singh, Ching-Yu Hung
  • Patent number: 11427348
    Abstract: A method and device for optimizing tests of systems, in particular of an aircraft, including a first display module displaying a list of tests that can be executed by systems, a selection module allowing an operator to select a set of tests to be executed and communicate it to an optimization module which determines a sequence of tests representing an optimized execution of the set of tests to be executed, the sequence of tests being displayed by a second display module for an operator, a decision module generating either a first signal if the operator validates the sequence of tests, or a second signal if the operator cancels the sequence of tests, and a control module which, if the first signal is generated, commands the execution of the sequence of tests by each of the systems, and generates results of the execution thereof.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 30, 2022
    Assignee: Airbus Operations (S.A.S.)
    Inventors: Anne-laure Desclaux-Chevalier, Serge Passemar, Christelle Senegas, Jean-Christophe Rey, Emmanuelle Escorihuela, Christophe Bressy
  • Patent number: 11431326
    Abstract: A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: San Ha Kim, Taek Kyun Shin, Min Su Kim
  • Patent number: 11394726
    Abstract: The present invention relates to a method for transmitting a message sequence via a data bus. The method comprises the transmission of an informational message containing an informational signal during an active phase, the transmission of a security message for initiating a rest phase and the transmission of rest messages containing a rest signal at the interval of a rest cycle time during the rest phase, wherein the informational signal and the rest signal differ from each other and wherein the security message and the rest messages differ from each other. Furthermore, the invention relates to a device for transmitting a message sequence via a data bus as well as a method and a device for detecting an attack on a message sequence transmitted via a data bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: July 19, 2022
    Assignee: VOLKSWAGEN AKTIENGESELLSCHAFT
    Inventors: Birger Kamp, Viktor Bunimov, Anke Jentzsch, Steven Michna, Christoph Riechel
  • Patent number: 11301543
    Abstract: A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be decoded, decoding a column position X and a row position Y of a last non-zero coefficient in the transform block from the encoded video bit stream, selecting a column-row inverse transform order when the scan pattern type is a first type, selecting a row-column inverse transform order when the scan pattern type is a second type, and performing one dimensional (1D) inverse discrete cosine transformation (IDCT) computations according to the selected transform order to inversely transform the transform block to generate a residual block.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Madhukar Budagavi, Vivienne Sze
  • Patent number: 11281530
    Abstract: The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rengaraja Sudarmani, Prathiksha Gautham, Uday Kumar N B, Abhinav Sharma, Sachin Suresh Upadhya
  • Patent number: 11232826
    Abstract: A semiconductor device may include a main circuit component and a spare circuit component including a plurality of spare elements and selected to change a function of the main circuit component, wherein each of the plurality of spare elements is configured to block a source voltage supply.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventor: Ki Hyuk Sung
  • Patent number: 11227091
    Abstract: Various aspects of the disclosed technology relate to predicting physical failure analysis-oriented diagnosis resolution. Fault simulation is performed on a circuit design to derive test responses for a set of faults and test patterns for testing circuits fabricated according to the circuit design. The set of faults is grouped into groups of equivalent faults based on the test responses. A group of equivalent faults consists of faults having the same test responses for all test patterns in the test patterns that can activate the faults. A PFA (physical failure analysis)-oriented diagnosis resolution evaluation value is computed by averaging weighted sizes of the groups of equivalent faults. The weight factors for the groups of equivalent faults with sizes greater than a certain number being smaller than the weight factors for rest of the groups of equivalent faults.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: January 18, 2022
    Assignee: Siemens Industry Software Inc.
    Inventors: Huaxing Tang, Jakub Janicki
  • Patent number: 11199579
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: December 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 11196567
    Abstract: A database management system receives a request to perform a transaction. The database management system commits the transaction, and in response to committing the transaction, generates a cryptographic hash based on an attribute of the transaction. The cryptographic hash is stored in a leaf-region of a hash tree. In response to a request to verify the transaction, signatures are retrieved from the tree based on a traversal of the tree to locate the node corresponding to the transaction. The retrieved signatures are used to verify the transaction.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 7, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Tate Andrew Certain, Yannis Papakonstantinou, Allan Henry Vermeulen, Christopher Richard Jacques de Kadt
  • Patent number: 11152922
    Abstract: A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: San Ha Kim, Taek Kyun Shin, Min Su Kim
  • Patent number: 11112451
    Abstract: A test method for a semiconductor device includes: loading a test tray having semiconductor devices of first and second lots arranged thereon into a test chamber; storing lot information of each of the semiconductor devices; performing a test program on each of the semiconductor devices; obtaining ID information of each of the semiconductor devices; matching the ID information with the lot information to generate lot sorting information; and sorting the semiconductor devices based on results of the test program and the lot sorting information.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Min Lee, Tae-Kyung Ko, Jin-Seong Kim, Hyeong-Gon Son, Seung-Woo Hong, Dong-Gu Lee, Sang-Jae Rhee
  • Patent number: 10963612
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 30, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10747928
    Abstract: Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel IP Corporation
    Inventors: Robert Pelt, Balatripura Chavali
  • Patent number: 10747923
    Abstract: Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a circuit under test (CUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the CUT on the programmable device. To help emulate a power gating event for the ASIC design, the programmable device may be provided with an encoder at the input of the CUT, a decoder at the output of the CUT, and a pseudorandom number generator (PRNG) that outputs a value for adjusting the encoder and decoder. The value output from the PRNG stays fixed when there is no power loss, but will change to a new value during a power gating event. Operated in this way, the data read out from the CUT after the power gating event is effectively corrupted.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Jing Zhang, Yan Li
  • Patent number: 10585142
    Abstract: An embodiment of the present invention provides a computer-implemented method for functional test and diagnostics of integrated circuits. The computer-implemented method includes executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints, applying dynamic clock switching to a clock of the device under test to identify one or more likely causes of a failure identified at the one or more checkpoints, and includes iteratively invoking a portion of the functional execution sequence between a plurality of the checkpoints to progressively isolate the one or more likely causes of the failure as a most likely failure source based at least in part on the applied dynamic clock switching.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10473711
    Abstract: A multi-channel device with a single diagnosis status pin may be configured to detect if one or more channels has a fault. The multi-channel device, which may operate within a system, can communicate which channel, of a plurality of channels, has the fault using only a single diagnosis status pin and no additional diagnosis control pins. The multi-channel device may output a fault signal on the diagnosis status pin and in response to an interrogation input signal on the same channel as a fault channel indicate to the system which channel is the fault channel.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Markus Ladurner, Albino Pidutti, Daniel Mayer
  • Patent number: 10438383
    Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 8, 2019
    Assignee: HITACHI, LTD.
    Inventors: Tadanobu Toba, Takumi Uezono, Yusuke Kanno, Masahiro Shiraishi, Hideo Harada, Satoru Akasaka
  • Patent number: 10402595
    Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 3, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Yiren Ronnie Huang, Xiaojie Zhang
  • Patent number: 10120024
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Patent number: 10095591
    Abstract: Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 9, 2018
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Sung Ho Kang, In Geol Lee
  • Patent number: 10025287
    Abstract: An industrial controller for safety control is disclosed. The controller comprises an interface for receiving a download of a safety control program, a memory for storing at least one safety control program and at least one processing unit for executing a safety control program stored in the non-volatile memory. The at least one processing unit is configured to determine whether a safety control program is verified and to limit an execution of an unverified safety control program according to an unverified run mode. An indicator is configured to indicate the execution of an unverified safety control program. A method of assigning a verification ID to an industrial controller comprises steps of configuring and downloading a safety control program, validating the configured safety control program for the target industrial controller, and assigning a verification ID. Execution of the configured safety control program is limited before the verification ID is assigned.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 17, 2018
    Assignee: Rockwell Automation Germany GMBH & Co. KG
    Inventors: Bradley Alan Prosak, Thomas Helpenstein, Rudolf Papenbreer, Mussa Tohidi Khaniki, Norbert Machuletz, Oliver Heckel
  • Patent number: 9904595
    Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saket Jalan, Indu Prathapan, Abhishek Ganapati Karkisaval
  • Patent number: 9891639
    Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Fabrice Marinet
  • Patent number: 9810932
    Abstract: A driver chip, a driver board and a test method thereof, and a display device. The driver chip includes a first internal interface, a second internal interface and a test circuit for performing a short-circuit detection on the internal interfaces, including an input unit and a test unit. The input unit is connected to a test signal input terminal and the first internal interface for transmitting a test signal inputted to the test unit and the first internal interface when in an ON state. The test unit is connected with the second internal interface and a test signal output terminal used for preventing a signal outputted by the input unit from being outputted from the test unit when in an OFF state. The test method detects whether a short-circuit has occurred to interfaces on the driver chip.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: November 7, 2017
    Inventors: Shuai Xu, Zhengxin Zhang, Zhiyong Wang
  • Patent number: 9678101
    Abstract: Provided is a sensor signal output apparatus that outputs a sensor signal at times of the sensor being in steady operation and outputs the operational status of the sensor instead of the sensor signal when the sensor is at fault or in non-steady operation in order to thereby to have a receiver machine obtain a correct sensor signal. The sensor signal output apparatus includes a sensor detecting a physical quantity, a diagnosis part diagnosing the operating state of the sensor, and a communication part transmitting the result of detection by the sensor and the result of diagnosis by the diagnosis part. When the sensor is determined to be normally operating, the communication part selectively outputs the result of detection by the sensor. When the sensor is not determined to be normally operating, the communication part selectively outputs a signal indicative of the operating state of the sensor.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: June 13, 2017
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Toshiaki Nakamura, Masahide Hayashi, Masaru Yamashita
  • Patent number: 9529671
    Abstract: An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: December 27, 2016
    Assignee: ARM Limited
    Inventors: Vikas Chandra, Robert Campbell Aitken
  • Patent number: 9477559
    Abstract: A control device according to an exemplary aspect of the present invention, which is included in a sub-system of a plurality of sub-systems included in a fault tolerant system, includes: a packet reception unit that receives data from a processor unit included in the plurality of sub systems each including: the processor unit; an input-output unit; and a signal transmission path, the control device being connected between the processor unit and the input-output unit; and a first transmission unit that transmits error detection data being generated from the data of accessing from the processor unit to the input-output unit in an own sub-system to an companion sub-system when the processor unit is in the lockstep synchronous state, and transmits the data of accessing from a processor unit to the input-output unit in the own sub-system to the companion sub-system when the processor is in a lockstep asynchronous state.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: October 25, 2016
    Assignee: NEC CORPORATION
    Inventor: Yasuyuki Shirano
  • Patent number: 9476941
    Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: October 25, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9448282
    Abstract: A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Dale Edward Meehl
  • Patent number: 9424123
    Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 23, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Garrett Leischner, Andrew J. Lagattuta, Matthew Jeremiah Eason, Landy Wang, John R. Douceur, Baskar Sridharan, Edmund B. Nightingale
  • Patent number: 9411007
    Abstract: The system and method described herein relate to a bug positioning system for post-silicon validation of a prototype integrated circuit using statistical analysis. Specifically, the bug positioning system samples output and intermediate signals from a prototype chip to generate signatures. Signatures are grouped into passing and failing groups, modeled, and compared to identify patterns of acceptable behavior and unacceptable behavior and locate bugs in space and time.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: August 9, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Valeria Bertacco, Andrew DeOrio, Daya Shanker Khudia
  • Patent number: 9310436
    Abstract: A system has in an integrated circuit a seed memory coupled to seed a vector generator that provides a vector to at least one scan chain of a first functional unit. A signature generator is configured to generate a signature from scan chain data, the signature is compared to an expected signature in a signature memory. A state memorizer is provided for saving a state of the functional unit and to restore the state of the functional unit as testing is completed. The system also has apparatus configured to determine an idle condition of the functional unit despite a non-idle state of the system; and a control unit configured to operate a test sequence when the functional unit is idle, the test sequence saving a state of the unit, generating vectors and signatures and verifying the signatures, and restoring the state of the unit.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 12, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jenny Picalausa, Kristoffer Koch
  • Patent number: 9298572
    Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nisar Ahmed, Anurag Jindal, Nipun Mahajan
  • Patent number: 9269072
    Abstract: In various embodiments, an attendee of a live online meeting selects screen data from an earlier point in time in the online meeting for playback while the meeting is still ongoing. Automatically generated image thumbnails of the screen data for the online meeting may be employed to navigate to the earlier point in time. Attendees may annotate screenshots associated with the thumbnails, and a summary document may be generated that includes the screenshots and the annotations.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 23, 2016
    Assignee: Citrix Systems, Inc.
    Inventors: Albert Alexandrov, Bernd Oliver Christiansen, Balineedu Chowdary Adsumilli
  • Patent number: 9270477
    Abstract: Network data gap is determined and reported to enable a user to validate that all the traffic that was intended to be monitored is being monitored in monitoring and/or troubleshooting tools for observation of network traffic and network installation and maintenance. Span port oversubscription, incomplete span configuration, incorrectly placed network taps and monitoring device packet drop may thereby be detected and reported as data gap.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: February 23, 2016
    Assignee: Airmagnet, Inc.
    Inventor: Dan Prescott
  • Patent number: 9250992
    Abstract: In some implementations, a built-in self-test (BIST) circuitry of a memory device is configured to perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated, enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error, detect an error in data read from the memory device after enabling error logging, and store information associated with the detected error.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: February 2, 2016
    Assignee: Marvell International Ltd.
    Inventors: Kit Sang Tam, Winston Lee, Robert Bateman, Kresten V. McGrath, David Lippincott
  • Patent number: 9244756
    Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
  • Patent number: 9244757
    Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
  • Patent number: 9222971
    Abstract: System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xiaoxiao Wang, Orman G. Shofner, Dat T. Tran, Leroy Winemberg, Ender Yilmaz
  • Patent number: 9170301
    Abstract: A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 27, 2015
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Patrick Gallagher, Krishna Chakravadhanula, Rajesh Khurana
  • Patent number: 9170297
    Abstract: A contactless smartcard type integrated circuit needing only two pins for performing a standard ATPG test is disclosed. A scan test may be performed using one pin for the clock and the other pin for the input and input of the scan test data. Additionally, security is enhanced by using an embedded signature generator to avoid observation of the data shifted out.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 27, 2015
    Assignee: NXP B.V.
    Inventor: Paul-Henri Pugliesi-Conti
  • Patent number: 9152749
    Abstract: A system and method of licensing electronic circuit designs within target electronic circuits or devices that allows secure delivery and reliable accounting of the licensed circuit designs on a per-usage basis. The method includes determining whether an electronic circuit design is licensable for use within a target electronic circuit by verifying licensing information included in a set of predetermined vectors associated with the electronic circuit design. In the event it is determined that the electronic circuit design is licensable for use within the target electronic circuit, the set of vectors is applied to the target electronic circuit by a licensing controller. Next, in response to a predetermined event, an attribute of the licensing information is updated to indicate the licensed use of the electronic circuit design within the target circuit.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: October 6, 2015
    Assignee: Intellitech Corp.
    Inventors: Michael Ricchetti, Christopher J. Clark