Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: An integrated circuit includes a self-description data store that stores a self-description of at least a portion of the integrated circuit device. The self-description includes at least some connectivity information indicating a structure of the integrated circuit device. The integrated circuit self-description may be referred to as a circuit netlist attachment or CNA.

Abstract: A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (210); providing the simulation model with a plurality of test patterns (220); receiving a plurality of simulated test responses to said test patterns (230); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (240); providing the integrated circuit with a further plurality of test patterns (250); receiving a plurality of test responses to said further plurality of test patterns (260); and checking the plurality of responses for the presence of the signature (270). This method provides improved fault detectability for an IC subjected thereto.

Abstract: A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

Abstract: A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.

Abstract: A method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the method provides boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.

Abstract: A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled.

Abstract: There is provided a testing apparatus that tests a device under test.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: An interface that communicates with first and second interface modules, an analyzer and an integrated circuit comprises a first path from the first and second interface modules and the analyzer to the integrated circuit. The first path includes a first serializer that serializes at least one of first control data and/or test data from at least one of the first and/or second interface modules. A second path from the integrated circuit to the first and second interface modules and the analyzer includes a high speed deserializer that deserializes serial data containing at least one of test result data and/or second control data from the integrated circuit. A frame sync module synchronizes data from the high speed deserializer to identify frames. The high speed deserializer outputs the second control data to at least one of the first and/or second interface modules. The frame sync module outputs the frames to the analyzer.

Abstract: The invention relates to an arrangement for testing integrated circuits, to a test system (2), to a circuit (1) to be tested, and to a method of testing logic circuits, where the test system (2) includes a programmable algorithmic test vector generator (4) which generates test vectors in real time so as to transfer these vectors to the circuit (1) to be tested.

Abstract: Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing.

Abstract: An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In response, the DUT produces a response waveform. The response waveform is compressed before transferring it to a storage device or over a data transfer interface. If the response waveform is analog, it is converted to digital before compression. The compressed waveform is decompressed for further analysis or display by a host computer. Features of the response waveform can be calculated from the compressed or uncompressed waveform data. Several configurations that include compression and decompression of stimulus and/or response waveforms in test systems are described.

Abstract: A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a predetermined number of scan chains. During each scan cycle, the signature register system combines a set of data values with a set of recirculated data values to provide a set of data signature values. The signature register system recirculates the data signature values from the preceding scan cycle to provide the recirculated data values. The space compaction system compresses the data signature values to provide a compressed scan chain signature for the scan chains. The compressed scan chain signature can be compared with a set of expected values to determine whether the scan chains include any erroneous values and, if so, to identify a source of the erroneous values.

Abstract: A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manufacturing defects in the manufacturing environment. The mechanism adjusts pre-emphasis and equalization in real time in high speed devices, allowing for much greater variation to compensate for design margins and specification variances. While the card is under test with wrap-backs installed, the pre-emphasis and receiver equalization are brought to the limits while logging the bit error rate to a non-volatile memory element. The mechanism then compares the bit error rate information to empirically derived signatures for failure isolation.

Abstract: An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Abstract: This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

Abstract: The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: A method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device is provided. With the method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Abstract: A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.

Abstract: Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. This is repeated with the first input bit pattern at a lower test speed to produce a second output bit pattern. Differences between the first and second output bit patterns are then detected to determine whether operation of the digital circuit at the normal operating speed causes errors that are not generated at the lower test speed.

Abstract: A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cycle, a signature being formed in the shift registers after a certain number of data words and cycles, a code generator which generates at least one additional bit position in at least one additional shift register from each data word in the signature also being provided.

Abstract: A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each time period using an incrementing value, and make that tag and the signature readable by a test controller. The MISR has the flexibility to be reset to a known initial state (or otherwise load a seed value) at the beginning of each time period or to continue accumulating signatures without being reset (or using the seed value). Accumulation of signatures over an extended period of time allows a test controller to validate that no errors occurred during a long term test without having to closely monitor the intermediate results.

Abstract: Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry coupled to target logic under test, where the test circuitry is configured to perform logic tests on the target logic using input data and thereby generate signature data. The system includes a first number of I/O ports that are shared for input and output and alternately convey the input data to the test circuitry and output the signature data generated by the test circuitry. The signature data includes a second number of bits greater than the number of I/O ports. The test circuitry is configured in a first mode to successively output multiple segments of the signature data through the I/O ports, where each segment has a number of bits no greater than the number of I/O ports.

Abstract: An apparatus that edits a test pattern used in a circuit function test includes a generator that generates a regular pattern that includes a plurality of unit patterns, by inserting a redundant pattern into a test pattern, and a pattern number reduction editor that defines the regular pattern as one unit pattern in the circuit function test.

Abstract: An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.

Abstract: A method for recording at least one information block in a first volatile memory external to a circuit, a first digital signature being calculated based on information and data internal to the circuit and a second digital signature being calculated based on first signatures of a group of information blocks and on a digital quantity internal to the circuit and assigned to said group. A method for checking the content of an information block recorded by this recording method.

Abstract: A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

Abstract: A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.

Abstract: Signature circuits are used during testing of an integrated circuit. Test vectors are applied as inputs to a circuit under test. A signature circuit stores a “signature” for the circuit under test based on a combination of signals from the circuit under test in response to test vectors and a previous stored state of the signature register. The value contained in the signature register at the end of the test is the signature. A fault-free circuit generates a particular signature for the applied test vectors. Faults can be determined by detecting variances from the expected signature. In one embodiment, the signature circuit uses a combination of two error detection codes.

Abstract: A model train command protocol using front and back error bytes is disclosed. The front error byte is used to encode the data so that it is securely transmitted. The back error byte checks for proper transmission of the data itself. The entire encoded data sequence is known as a signature. The signature is sent by a user via a remote base through a communication link in a model train system. A receiver located within the model train system decodes the signature and executes the command.

Abstract: Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit assembly under test, and then generates a series of Boundary-Scan test vectors wherein each test vector is derived from corresponding bits of the binary signatures.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.

Abstract: A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's boundary latch module. The initialization data is selected from a plurality of scan paths of the integrated circuit, and the initialization data from at least one of the latches is provided as input to a logic circuit of the IC or output of the IC. In another aspect, the method includes selecting a datum from an external input or test-pattern generator of the integrated circuit for capture in at least one of the latches and input to a multiple-input signature register, which stores a signature of the integrated circuit resulting from the logic built-in self-testing.

Abstract: A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being verified is electrically coupled to the tested I/O circuit. A result of verifying of the at least one external signal path is manifested in the integrated circuit's signature, which characterizes a response of the I/O circuit to the LBIST. In another aspect, the verifying of the at least one external signal path includes concurrently testing another I/O circuit of another integrated circuit, which is also electrically coupled to the external signal path.

Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Abstract: A data access method for serial bus is provided. During a write/read cycle, the write/read cycle is divided into a plurality of transmitting intervals and a plurality of suspending intervals. In each of the transmitting intervals, a clock signals is transmitted on a clock pin and a data signals is transmitted on a data pin. In each of the suspending intervals, the clock signals stop being transmitted on the clock pin. In other words, the present invention uses an interrupted clock signal, such that an embedded controller can directly write a received data in a flash memory or directly output the data read from the flash memory, so as to avoid using any register. Therefore, the present invention can decrease the cost of the embedded controller and reduce the area of integrated circuit.

Abstract: Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not received. This allows fast/complex ATE Rx memory to be replaced by slower and smaller MISR pattern memory. At the end of a test period, the LFSRs or MISRs generate signatures which are then compared to a set of possible valid signatures for non-deterministic data. A pass/fail result is produced. By masking indeterminate states, fewer valid signatures need to be stored. Masking of the MISRs or LFSRs may be based on the fact that indeterminate states and good data in a serial output data stream tend to occur in predictable patterns, or that good data may follow alignment characters. MISR or LFSR output signatures may also be employed to test individual pattern segments instead of the entire input test pattern.

Abstract: A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged in a plurality of scan chains wherein each latch holds data for a logical cone. The LBIST is performed on one scan chain at a time. Once the first latch is located, a first limiting cone (i.e., the cone for which the first latch is holding data) may be isolated. After isolating the first limiting cone, the data from the first latch is masked out and the LBIST is repeated on the scan chain. The data is masked out in order to facilitate the identification of any other latch that may fail the test. Again, if another latch fails the test a corresponding limiting cone may be isolated.

Abstract: The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input and a scan clock signal input; wherein: in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is operable to isolate said scan input from said master latch, and said master latch is operable in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation said data input tristateable device is op

Abstract: A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial data bits by m bits (m?4) in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester. The tester compares a computed signature signal to a 1-bit signature signal to determine whether the DUT is operating poorly or not.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

Abstract: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.

Abstract: Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of signals of the user design, and for each set of signals, generates a respective supplement of a subset of the user design supplementing the subset with a logic analyzer coupled to the set of signals. The compiler generates a respective configuration for each supplement. The selector selects a configuration or multiple configurations responsive to the specified set of signals and the sets of signals. The PLD implements the user design after the PLD is programmed with the selected configuration or configurations. The monitor accesses the specified set of signals in the PLD via the logic analyzer corresponding to each of the selected configuration or configurations.

Abstract: A device (10) for validating a circuit (1) comprising at least one microprocessor (3) and a specialized unit (2) provided with registers includes a base (11) for receiving the circuit, a memory (4, 5) simulating an external memory with which the circuit is intended to cooperate and a computer (20) controlling the validation. The memory (4, 5) contains software for processing data received by the circuit and instructions for executing a validation sequence, making it possible to form a data flow representing a flow received by the circuit in normal operation, to compare data contained in registers of the circuit with theoretical values and to supply a signature representing a result of these comparisons.