Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

Abstract: Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.

Abstract: An apparatus that improves Built-In-Self-Test (BIST) flexibility. A compilable address magnitude comparator facilitates BIST testing of different size memory arrays without requiring customization of the BIST controller. The compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller be compilable. The compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses not existing in the memory. The BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. The BIST controller is able to test memory arrays without regard for their particular size. A single BIST controller can be used to test multiple memory arrays of different sizes in the ASIC, reducing device complexity.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: Disclosed are novel methods and apparatus for efficiently providing concurrently programmable dynamic memory built-in self-testing (BIST). In an embodiment of the present invention, a method of utilizing a BIST system is disclosed. The method includes: loading setup data into a configuration register; loading a first instruction into a shift register; loading the first instruction into an update register; executing the loaded first instruction to perform a memory test; upon receiving a first update command, loading a second instruction into the shift register; and upon receiving a second update command, loading the second instruction into the update register.

Abstract: A test system includes a test data generator to provide test data (e.g., a test pattern) to a subject circuit (e.g., a digital television video circuit). The test data is functionally to verify the subject circuit. The functional verification of the subject circuit is performed utilizing an output of the subject circuit generated responsive to the test data in accordance with an operational functionality of the subject circuit. The test data generator is also coupled to provide the test data to a built-in self-test (BIST) circuit so as to enable the built-in self-test circuit to receive the test data.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract: A method and an apparatus are provided for isolating faulty semiconductor devices in a multiple stream graphics system. The apparatus includes a buffer adapted to receive a plurality of data streams. The apparatus further includes a convolver comprising at least one convolution signature register; a router adapted to route the data streams from the buffer to the convolver, wherein the router comprises at least one router signature register; and an analyzer adapted to access the convolution and router signature registers, wherein the analyzer is capable of isolating at least one of a faulty semiconductor device and a faulty interconnection using the contents of the convolution and router signature registers.

Abstract: Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code that, when compiled into machine test code, interfaces with the test engine. The machine test code is executed with the processor to test the memory cache to detect one or more faulty memory blocks in the memory cache. If any of the faulty memory blocks are detected, the test engine is instructed, through the machine test code, to set one or more bits in registers to functionally replace the faulty memory blocks with redundant blocks of the memory cache.

Abstract: A program-controlled unit has debug resources that outputs trace information including selected addresses, data and/or control signals and that can be used to trace the course of the operations occurring within the program-controlled. The debug resources monitor whether a predefined change in the level of one or more predefined bits of the addresses, data and/or control signals contained in the trace information has taken place, and start or terminate the generation of trace information as a function of the result of this check. Additionally or alternatively, the trace information that is output is a component of messages having a variable length portion that contains the trace information. Additionally or alternatively, the trace information that is output is a component of messages, and it is possible to determine which trace information is located at which point within the message.

Abstract: An integrated circuit (14) with an application circuit (1) to be tested and a self-testing circuit (5-13), which is provided for testing the application circuit (1) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates (6, 7, 8) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit (1) for testing purposes, wherein the output signals occurring through the application circuit (1) as a function of the test patterns are evaluated by means of a signature register (13), wherein, by means of second logic gates (10, 11, 12) and signals fed to said gates, those bits of the output signals of the application circuit (1) which, due to the circuit structure of application circuit (1), have undefined states, are blocked during testing.

Abstract: A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

Abstract: A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Abstract: A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.

Abstract: In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.

Abstract: A method and apparatus are presented for on-chip testing of circuits in testing channels. In an embodiment of the present invention, the system includes a weight selector that allows for a wide variety of weighting of test data that is to be supplied to the testing channels. For example, the weight selector may be used to weight all bits in all channels or individual bits in a particular channel. Clock control and diagnostic logic may also be provided to selectively supply scan, functional, and/or stop clock signals to the testing channels. Channel filtering logic may be also provided to mask output data from a selected testing channel as desired. The method and apparatus may provide improved testing performance and power savings.

Abstract: A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell having an ATAP for applying analog tests. The bus is coupled with the ATAP simulation. The bus is operative to transmit and receive analog test simulation data. The ATAP test bench file is configured to receive the simulation data. The output file is operative to store the simulation data and deliver the simulation data to the ATAP simulation circuitry. The test program is generated by the ATAP simulation circuitry in the output file. The test program is configured to automatically generate ATAP test benches based upon chip-specific information. A method is also provided.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.

Abstract: An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a plurality of input signals and present one of the plurality of input signals as a data signal in response to a control signal. The second circuit may be configured to generate the control signal and generate a trace data stream in response to the data signal. The third circuit may be configured to receive and store the trace data stream and read and present the stored trace data stream in response to one or more commands.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: A semiconductor device is disclosed that include a built-in self test system. The device comprises a logic function and a self test engine coupled and integrated with the logic device. The device includes a performance code storage coupled and integrated with the logic function. The performance code storage contains at least one critical path pattern that will be run on the logic function to determine the performance of the logic function when the self test engine causes the logic function to be in a performance test mode. In summary, a performance sort/validate integrated custom logic device, like a microprocessor core can be tested without the need for a separate, high-performance tester. A performance built-in self test (PBIST) approach provides a basic test procedure to be utilized within the device. An integrated memory array, such as the L1-cache, is provided wherein a select set of SRAM memory words are preconditioned at the time of manufacture to contain predefined functional patterns.

Abstract: A system and method for dynamically determining a route through one or more switch devices at program execution time. A program operable to perform a programmatic request to dynamically determine a route may be created. For example, the request may specify a first endpoint (e.g., channel) of a first switch device and a second endpoint (e.g., channel) of a second switch device. In response to the request, the system may dynamically determine a route from the first endpoint to the second endpoint during execution of the program. Information indicating the determined route may be returned to the program.

Abstract: An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

Abstract: Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Abstract: A built-in, self-test (BIST) network employs a hierarchy of Universal BIST schedulers (UBSs) for scheduling and coordinating testing of elements, such as regular structure BISTed (RSB) elements and random logic BISTed (RLB) elements. Individual UBSs are preferably positioned in local areas, or sections, of an integrated circuit for testing of RSB and RLB elements within the local area. Testing of RSB and RLB elements within the local area allows the BIST network to minimize effects of delay and clock skew by employing relatively short interconnect routing between BISTed elements. Each of the individual UBSs are, in turn, controlled by a master UBS (MUBS) via simplified timing of control signals. The MUBS also may interface with an external testing device that initiates BISTed testing.

Abstract: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM.

Abstract: A program-controlled unit is described. The program-controlled unit has a central processing unit (CPU), peripheral units that are connected to the CPU via an internal bus, and debug resources that can be used to trace and influence operations taking place in the program-controlled unit. The program-controlled unit that is described is characterized in that the debug resources and the peripheral units, which output data from the program-controlled unit and/or can receive and pass on data which is supplied to the program-controlled unit from the outside, are connected to one another via a second internal bus. The data that is to be transmitted between the debug resources and devices provided outside the program-controlled unit are transmitted via the second internal bus and individual, a plurality of, or all the peripheral units connected thereto.

Abstract: An apparatus for sampling a power supply current value for performing frequency analysis of the power supply current flowing in an integrated circuit with a test signal applied to the integrated circuit has a power supply generating a prescribed supply of power for the integrated circuit (DUT: device under test), a current detection means for observing the power supply current value supplied from the power supply to the DUT, a test signal generation means for generating a prescribed test signal to be applied to an input/output terminal other than a power supply terminal of the DUT and for generating a test signal application signal during application of the test signal to the DUT, a sampling means for sampling the power supply current value signal, a sampling time determining means for instructing the sampling means with regard to the start and end timing for sampling, based on the test signal application signal, a sampling data storage means for storing data sampled by the sampling means, a Fourier transform

Abstract: A BIST circuit for an IC measures the time delay a rising or falling edge experiences as it passes through a signal path within the IC. A strobe circuit within the BIST circuit generates edges in two signals A and B in delayed response to edges of a STROBE signal. A path probe generates a signal C edge at the signal path input in response to each signal A edge. The STROBE-to-B edge delay within the strobe generator is iteratively adjusted to determine a first delay for which the path probe detects the B and C signal edges at nearly the same time and thereafter iteratively adjusted to determine a second delay for which the path probe detects the B and D signal edges at nearly the same time. The first delay is measured by causing the strobe signal generator to produce a periodic signal having a period proportional to the first delay and counting the number of cycles of a reference clock occurring during K cycles of the periodic signal. The second delay is measured in a similar manner.

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a BIST engine and a register. The BIST engine is capable of executing a built-in self-test and storing the results thereof, wherein the results include an indication of whether an executed built-in self-test is completed. The register is capable of storing the results of the executed built-in self-test, including the indication. A method for performing a built-in self-test comprises performing a BIST, including generating a indication of whether the built-in self-test is completed, and storing the indication.

Abstract: A circuit and a method determine at least one electrical characteristic variable for an integrated circuit. Two or more successively produced states of a reference signal are recorded and counted in a first recording unit to produce an output voltage in a voltage generator circuit for the integrated circuit, and the number of detected states is stored. Furthermore, a time duration within which the states of the reference signal are recorded is recorded in a second recording unit. The numerical values are output via an output circuit for determining the electrical characteristic variable. At least one electrical characteristic variable such as a voltage, current and/or power value for the integrated circuit, is calculated from the number of successively recorded states of the reference signal and from the time duration. It is therefore possible to obtain accurate values relating to the operation of the integrated circuit with comparatively little complexity.

Abstract: A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.

Abstract: A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

Abstract: A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a logic built-in self-test (“LBIST”) engine capable of executing a LBIST and storing the results thereof and a multiple input signature register (“MISR”). The LBIST engine includes a LBIST state machine; and a pattern generator seeded with a first primitive polynomial. The MISR is capable of storing the results of an executed LBIST, the contents thereof being stored per a second primitive polynomial. A method for performing a LBIST comprises seeding a pattern generator in a LBIST engine with a first polynomial; executing a LBIST using the contents of the pattern generator; and storing the results of an executed LBIST in a MISR utilizing a second primitive polynomial.

Abstract: A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, a receiver section coupled to the transmitter section, and a test data analyzer coupled to the receiver section, wherein the test data analyzer includes a second pseudo-random number generator, which allows the operator to input the data value via a data bus coupled to the test data analyzer. Both the self-test data generator and the test data analyzer are independently controllable.

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract: An existing trace array on a chip is used to store the locations of bit failures from the automatic self-testing of an SRAM array. If a system is having problems, a technician can trigger the automatic test and then scan the trace array, thereby locating a large number of errors on the SRAM array very quickly.

Abstract: An integrated circuit (IC) and methods of manufacturing and operating ICs. In one embodiment, the IC includes: (1) a plurality of interchangeable hard macrocells, (2) at least one programmable logic block (PLB), (3) a bus intercoupling said plurality and said at least one programmable logic block and (4) a self-repair program, associated with said at least one programmable logic block, that causes said PLB to test at least some of said plurality and place at least a functioning one of said plurality into an operational status.

Abstract: In a method for the analysis and evaluation of measured values of an open test system, a test piece is monitored during a test run by at least one signal channel which sends a signal to an evaluation unit for further processing whereby at least one plausibility node is coupled with at least one signal channel. In order to allow a statement to be made about the value of plausibility nodes and their results in relation to a specific measuring task, an evaluated plausibility is ascertained for at least one of the measured values from the type and number of plausibility nodes as well as their possible, variable interconnection.

Abstract: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Abstract: A method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during manufacturing testing and/or during normal on-line operation. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. Within the self-testing area, programmable interconnect resources of the FPGA are grouped and comparatively tested for faults. Upon the detection of one or more faults within a group of programmable interconnect resources, the group of resources is subdivided for further comparative testing in order to minimize a region of the group of resources including the fault for each fault. Once the region of the group of resources which includes the fault is minimized, the wires within the minimized region are comparatively tested in order to determine which wire includes the faulty resource or resources.

Abstract: A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.

Abstract: An integrated circuit having a DRAM array connected to a power supply is tested for excessive current draw by selectively applying voltage to a single wordline or bitline, measuring current drawn, comparing the result with a reference number representing acceptable leakage, and replacing columns of the array having excessive leakage, thereby identifying and repairing latent defects that may become a cause of failure.

Abstract: An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

Abstract: A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.

Abstract: A first dynamic logic circuit has an output node on which a scan value is provided during scan, a second dynamic logic circuit, and one or more third dynamic logic circuits. The first dynamic logic circuit and the second dynamic logic circuit are in a first dynamic phase during functional operation. The third dynamic logic circuits are in a second dynamic phase during functional operation, and an output of the third dynamic circuits is sampled in response to the scan value during scan. In one embodiment, a first clock controls evaluation of the second dynamic logic circuit, and the second clock controls evaluation of the third dynamic logic circuits. The clocks may be generated responsive to a scan clock and/or a scan mode signal to generate at least one evaluate pulse on the first clock and the second clock prior to sampling the output of the third dynamic circuits.

Abstract: IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.