Abstract: A method for reducing terminal temperature includes: connecting to a first network; and monitoring a chip temperature of a terminal, and sending rate reduction information to a network device when the chip temperature is greater than a first predetermined threshold, and the rate reduction information being used to trigger reduction in a transmission rate between the network device and the terminal. As such, the terminal temperature can be reduced by reducing the transmission rate while maintaining the network connection, and user experience can be improved.

Abstract: The invention relates to a measurement system for detection of conduction faults of a device or equipment, comprising an evaluation unit and at least one sensor unit, wherein the measurement system is furthermore adapted to determine, in regard to a fault, whether the fault is higher or lower in frequency with respect to a predetermined limit frequency, and the measurement system is furthermore adapted to provide data in regard to one fault or multiple faults.

Abstract: An acoustic noise reduction (ANR) headphone described herein has current detection circuitry that detects current consumed by an acoustic driver amplifier as a result of pressure changes due to a tapping of the headphone. Tapping may be performed to change an audio feature or operating mode of the audio system for the headphone. The current detection circuitry senses a characteristic of the current consumed by the acoustic driver amplifier that can be used to determine an occurrence of a tap event. Examples of a characteristic include an amplitude, waveform or duration of the sensed current. Advantageously, the ANR headphones avoid the need for control buttons to initiate the desired changes to the audio feature or operating mode.

Abstract: A touch Bluetooth headset includes a housing, a touchpad, a main board, a Bluetooth antenna, a first thimble and a second thimble. The touchpad is a flexible touchpad, the main board and the touchpad are opposite and fixed on the housing, and the touchpad is provided with a plurality of metal contacts. The first thimble and the second thimble have one end fixed to the main board and other end extending toward the touchpad and abutting against the metal contacts. The Bluetooth antenna is laid on the touchpad and connected to the metal contacts. The touch Bluetooth headset may be designed to be more miniaturized; additionally, an additional Bluetooth antenna is added in the touchpad and the Bluetooth antenna is jacked up by the above thimbles, which reduces the electromagnetic shielding, thereby the micro Bluetooth headset has a better signal transmission distance.

Abstract: A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: Systems and methods that provide manual test cases and scripted test cases automatically based on metadata included in a software application. In an embodiment, an application may include elements that generate an output file containing information corresponding to one or more forms with one or more fields in an application. The information may be utilized by a test device or application to automatically generate manual test cases, automated scripted test cases, or a combination of manual and automated test cases based on the information. In an embodiment, a manual test case may include a sequence of instructions in a natural language format. In an embodiment, an automated test case may be in a script language configured to interact with the application or an appropriate application emulator.

Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract: A method and apparatus for system control of a central processing unit (CPU) maximum power detector are provided. In accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the CPU is to be altered. When the response is to be altered, a modified input level is provided to the maximum power detector to alter the response. As an example, the modified input level can prevent the maximum power detector from triggering a power throttling function. When the response is not to be altered, an existing input level for the maximum power detector is maintained. In accordance with at least one embodiment, an apparatus or information handling system can comprise a voltage regulator (VR), a current sensor, a CPU comprising a maximum power detector, and a digital to analog converter (DAC).

Abstract: An audio signal processing apparatus includes a tapping detection unit to which an audio signal picked up by a microphone is input and that detects a tapping input operation on the basis of an energy increase/decrease determination process for making a determination as to whether an increase and a decrease of an energy level of low-frequency components of the audio signal occur within a first time period; and a control unit that performs a certain control process that is set for a tapping input operation in response to a tapping input operation being detected by the tapping detection unit.

Abstract: A system and method for monitoring a process tool of an integrated circuit manufacturing system are disclosed. An exemplary method includes defining zones of an integrated circuit manufacturing process tool; grouping parameters of the integrated circuit manufacturing process tool based on the defined zones; and evaluating a condition of the integrated circuit manufacturing process tool based on the grouped parameters.

Abstract: A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Abstract: Embodiments include a method and apparatus for processing a downlink shared channel. In one embodiment, a Node-B includes circuitry configured to process control information for a user equipment (UE) and to produce an N bit cyclic redundancy check (CRC) associated with the control information. The Node-B includes circuitry configured to modulo 2 add the N bit CRC with an N bit UE identity to produce an N bit field, wherein the UE identity is any one of a plurality of UE identities associated with the UE. The Node-B includes circuitry configured to transmit a wireless signal of a control channel, wherein the wireless signal comprises the N bit field and the control information.

Abstract: Data is processed by selecting one or more bits in a codeword to replace with an erasure. The selected bits in the codeword are replaced with the erasure and error correction decoding is performed on the codeword with the erasure in place for the selected bits.

Abstract: A computer implemented method and system including techniques for developing and executing automated test cases are described herein. In one embodiment, a test case automation tool provides functionality for defining an automated test set and associated test cases within a testing user interface without the use of scripting languages or compiled programming. The definition of each test case may occur within a testing user interface, including displaying and receiving user selection of available methods for testing; displaying user parameter fields and receiving user parameter values in response for testing; abstracting parameter types in the user parameter values; and generating XML-format definitions of the test case. The test case automation tool may then execute the selected methods of the software application using parameters provided in the XML-format definitions, and return testing results of the test case execution.

Abstract: In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.

Abstract: An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.

Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

Abstract: A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

Abstract: A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss.

Abstract: A method and circuits for implementing aperture function calibration for Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. The aperture function calibration uses aperture calibration data, and an LBIST calibration channel having a predefined number of scan inversions between the aperture calibration data and a multiple input signature register (MISR). LBIST is run selecting the LBIST calibration channel and masking other LBIST channels to the MISR. A change in the MISR value, for example, from zero to a non-zero value, is identified and an aperture adjustment is calculated and used to identify any needed adjustment of aperture edges.

Abstract: A data reading method for a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical pages. The data reading method includes grouping the physical pages into a plurality of physical page groups and configuring a corresponding threshold voltage set for each of the physical page groups. The data reading method also includes respectively reading data from the physical pages of the physical page groups by using the corresponding threshold voltage sets. The data reading method further includes when data read from one of the physical pages of one of the physical page groups cannot be corrected by using an error checking and correcting (ECC) circuit, updating the threshold voltage set corresponding to the physical page group.

Abstract: A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.

Abstract: A memory controller has a first interface, for connection to an external memory device; a second interface, for connection to at least one other component; and a third JTAG interface, for connection to an external user device. The memory controller further includes a processor, which performs calibration processes, in order to synchronize operations of the memory controller and the external memory device, and also runs test software for testing operation of the first interface and the external memory device, and for providing test results to the external user device over the third interface. The memory controller further includes an internal memory, for storing the instructions defining the test software.

Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.

Abstract: In a memory testing method for testing a memory module of a computing device, an operating voltage of the memory module is adjusted to a first voltage or a second voltage. A predetermined data set is written into the memory module after the operating voltage of the memory module is adjusted, and the written data set is read out from the memory module, to accomplish a data writing and reading process of the memory module. A register value that presents how many memory errors have occurred during the data writing and reading process is acquired from an ECC register of the memory module, to determine whether the memory module is stable during the adjusting of the operating voltage according to the register value.

Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.

Abstract: A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits.

Abstract: An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indicates whether the extended JTAG features are to be disabled. The level sensor monitors an external voltage signal, and indicates that the external voltage signal is at a legal level. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. The blow controller receives a voltage, and blows a selected fuse within a fuse array responsive to a valve of the voltage.

Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

Abstract: A system and method is disclosed for managing bookmark buttons on a web browser toolbar. A web browser stores the number of times it is used to navigate to a website. On navigating to a website a predetermined number of times, a bookmark button that links to the website is automatically generated and displayed on the toolbar. The number of bookmark buttons displayed at any one time is limited, and they are arranged by the number of times their associated websites have been viewed. On determining that a new website has been viewed more than a website associated with a currently displayed bookmark button, the currently displayed bookmark button is replaced by a new bookmark button that links to the new website.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of turbo decoding. For example, a device may include a turbo decoder to decode a turbo-encoded input according to a turbo code, the turbo-encoded input including a plurality of soft-decision information-bit values and a plurality of soft-decision parity-bit values corresponding to the soft-decision information bit values, wherein the turbo decoder is to output a plurality of extrinsic soft-decision parity-bit values corresponding to the plurality soft-decision parity-bit values. Other embodiments are described and claimed.

Abstract: A method and apparatus is disclosed wherein a user equipment (UE) receives control information on a first channel and uses the control information to process a second channel.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: A system and method for generating a migration plan for migrating data from a first electronic medium to a second electronic medium is provided. The system comprises a migration readiness assessment module for determining a migration recommendation; an effort estimation module for determining a total effort required for migrating data from a first electronic medium to a second electronic medium; and a migration plan generator module for generating a migration plan based on the determined migration recommendation and the total estimated effort.

Abstract: A power supply controlling apparatus includes: a control portion that measure a consumption current value of a current supplied to a controlled device, and controls on/off of the current supplied to the controlled device; a communication portion that transmits a given command to the controlled device, and receives a response to the given command; and a monitor portion that monitors a state of the controlled device based on the consumption current value of the controlled device measured by the control portion, and a life or death state of the controlled device by the given command.

Abstract: A method for testing an integrated circuit to detect delay faults resulting from a signal path from a first block of the integrated circuit to a second block of the integrated circuit, wherein first and second blocks are running at different application speeds. The method may include shifting first data into scan memory cells of the integrated circuit at a first frequency; applying a launch test clock pulse to the first block at a second frequency; applying a capture test clock pulse to the second block at the second frequency, wherein the first edges of the launch and capture pulses are delayed with respect to each other by a period that is a reciprocal of the second frequency; shifting second data from the scan memory cells to an output at the first frequency; and comparing the second data at the output with expected values.

Abstract: This invention is a method of operating a system having multiple finite state machines and a controller controlling an operational state of each finite state machine. Upon selection by the controller of a changed operational state, each finite state machine determines if it supports the changed operational state. If the finite state machine supports the changed operational state, it enters the changed operational state. If the finite state machine does not support the changed operational state, it enters an offline state. The controller may also determine whether a changed operational state is supported by each finite state machine.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: A method executes computerized instructions within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics.

Abstract: Tuning limits are set for operational parameters in a processing stage within a data processing apparatus for processing a signal and outputting it at an output time. If a signal output between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, an error is signaled. A tuning circuit adjusts an operational parameter of the processing stage in accordance with a tuning limit. A signal passing along a critical path of the processing stage tuned to the tuning limit is expected to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.