Hamming Code Patents (Class 714/777)
  • Patent number: 11190217
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Patent number: 11119996
    Abstract: A method for applying bloom filter on a large data set consisting of key-value pairs, using at least one processor includes: partitioning large data-set of key-value pairs into data chunks; determining Bloom filter Vector and number of segments in the vector for each data chunk; Encoding all keys of a given Chunk into a Bloom filter vector; Determining the segment-id of a given key using H (0) hash function; Encoding Key into a Bloom filter segment with the determined segment-id, using a K-bit array produced by H1, . . . Hk functions; and Packing of segments into extent data structures where each extent includes segments of different chunks, but with the same segment-id wherein a single extent filters multiple chunks, depending on a packing factor (the number of segments packed into a single extent).
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 14, 2021
    Assignee: SQREAM TECHNOLOGIES LTD.
    Inventors: Israel Gold, Yanai Nani Eliyahu
  • Patent number: 11108494
    Abstract: A method and a device for channel coding in a terminal and a base station are disclosed. The base station performs channel coding and transmits a first radio signal in sequence. A first bit block is for an input to the channel coding based on a polar code. An output after the channel coding is for generating the first radio signal. The first bit block comprises bit(s) in a first and a second bit sub-block. A value of the first bit sub-block or the first bit sub-block is related to a number of bits in the second bit sub-block or in the first bit block. Position(s) of bit(s) in the first bit sub-block in the first bit block is(are) determined by default. An advantage of the present disclosure is to lift the burden on blind detections of the UE and support a more flexible information transmission format.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 31, 2021
    Assignee: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventor: XiaoBo Zhang
  • Patent number: 10838797
    Abstract: Methods, apparatus, systems and articles of manufacture providing an image modality smart symptom maintenance are disclosed. The example apparatus includes a system processor to identify a distinguishing symptom of a first subset of issues corresponding to an imaging device. The apparatus further includes an interface to transmit a prompt corresponding to an identification of the distinguishing symptom. The apparatus further includes a filter to filter out issues of the first subset of issues based on a response to the prompt to generate a second subset of issues. The apparatus further includes the system processor to transform the first subset of issues into a solution for servicing the imaging device by applying at least one of the symptom or the first subset of issues to an artificial intelligence model corresponding to the imaging device.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 17, 2020
    Assignee: General Electric Company
    Inventors: Sridhar Nuthi, Nicholas Allen, Fabio Almeida
  • Patent number: 10685037
    Abstract: Cohorts may be created on storage nodes in an object-redundant storage system that uses replication and/or a redundant encoding technique. In a cohort with N nodes, M data elements (replicas or shards) of an object are stored to M of the nodes that are randomly (or otherwise) selected from the N nodes. Metadata for locating other data elements for an object in the cohort may be stored with one or more of the data elements in the cohort. To retrieve an object from a cohort, a subset of the nodes may be queried; the subset may be randomly or otherwise selected. If enough data elements are retrieved for the object from the queried nodes, the object is provided to the requester. Otherwise, additional data elements may be retrieved according to the metadata returned with a data element or by querying additional nodes.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: June 16, 2020
    Assignee: Amazon Technology, Inc.
    Inventors: Paul David Franklin, Bryan James Donlan
  • Patent number: 10608934
    Abstract: A bloom filter and an implementation method thereof are provided. The implementation method has a ternary rule encoded as a rule binary codeword according to a predetermined encoding rule; has a packet encoded as at least one packet binary codeword according to the predetermined encoding rule; and comparing the rule binary codeword and the at least one packet binary codeword to decide a following processing of the packet. The predetermined encoding rule includes: tagging 0 or 1 into most significant bit (MSB) of the output binary codeword based on mask length of the input codeword; placing the prefix of the input codeword right after MSB of the output binary codeword; and tagging a string to last bits of the output binary codeword based on the mask length, and the bit number of the string equals to the mask length.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 31, 2020
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Sheng-Chun Kao, Ding-Yuan Lee, An-Yeu Wu, Ting-Sheng Chen
  • Patent number: 10496680
    Abstract: A method for classification includes extracting respective classification keys from a collection of data items and defining a set of patterns for matching to the classification keys. A plurality of memory banks contain respective Bloom filters, each Bloom configured to indicate one or more patterns in the set that are candidates to match a given classification key. A respective first hash function is applied to the classification keys for each pattern in order to select, for each classification key, one of the Bloom filters to query for the pattern. The selected Bloom filters are queried by applying a respective second hash function to each classification key, so as to receive from the Bloom filters an indication of the one or more candidate patterns. The data items are classified by matching the respective classification keys against the candidate patterns.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 3, 2019
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Gil Levy, Pedro Reviriego, Salvatore Pontarelli, Efim Yehiel Kravchik
  • Patent number: 10379944
    Abstract: A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 13, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Shrikanth Ganapathy, Steven Raasch
  • Patent number: 10055278
    Abstract: A computer-implemented method is provided for increasing the failure tolerance of an array of storage elements in a storage system. The computer-implemented method includes configuring an array to include a plurality of storage elements in n>1 sets of storage elements. The computer-implemented method also includes configuring an erasure-correcting code such that at least one column of the storage elements of the array stores row parity information, and at least one row of the storage elements of the array stores column parity information. Still yet, the computer-implemented method includes, subsequent to a failure of one of the storage elements storing data, selecting a recipient storage element from the array, and rebuilding at least a portion of the data onto the recipient storage element by performing a parity exchange operation that retains a failure tolerance of the set of storage elements containing the failed storage element.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven R. Hetzler
  • Patent number: 9979417
    Abstract: Memory systems may include a memory storage, and a controller suitable for receiving a plurality of codewords, determining whether each codeword is decodable, estimating a location of an error in a codeword determined to be undecodable by calculating a syndrome of the undecodable codeword when at least two codewords of the plurality of codewords are determined to be undecodable, performing error recovery on the undecodable codewords, and hard decoding the plurality of codewords including the error recovered codewords.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, June Lee, Yu Cai
  • Patent number: 9886378
    Abstract: A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyotaek Leem
  • Patent number: 9740797
    Abstract: Technologies are generally described for a scheme for computing a counting number of a keyword. In some examples, a method performed under control of a computing device may include obtaining a result of a j-th set of hash functions with regard to a key; marking a head marker into a bit array of a bloom filter based at least in part on the result of the j-th set of hash functions, if the j is zero; and marking a tail marker into the bit array of the bloom filter based at least in part on the result of the j-th set of hash functions, if the j is the same as or larger than 1.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: August 22, 2017
    Assignee: Inha-Industry Partnership Institute
    Inventor: DaeHun Nyang
  • Patent number: 9703894
    Abstract: A system comprises a hashing logic, which executes instructions to convert raw data into a first logical address and payload data, where the first logical address describes metadata about the payload data. A hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device. A hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device. A content addressable store is associated with a reference to the logical addressed data in this location addressable high dimensional store, where the content addressable store is searched for the desired content word using at least one temporal attribute to retrieve the corresponding references with low latency. A hardware exclusive OR (XOR) unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Samuel Scott Adams, Suparna Bhattacharya, Robert R. Friedlander, James R. Kraemer
  • Patent number: 9633810
    Abstract: A combination switch 10 outputs operation command signals to a driving system of a vehicle according to a switching operation of a switching unit 11 and includes a storage part 21 that stores determination information 21a indicating whether combinations of operation command signals to be outputted from switches of the switching unit 11 are abnormal or normal, a determination part 22 that refers to the determination information 21a in the storage part 21, determines whether or not a combination of the operation command signals is abnormal, and if an abnormal combination of the operation command signals continues longer than a predetermined time, adds, to the operation command signals, abnormality information indicating that the combination of the operation command signals is abnormal, and a communication part 13 that transmits the operation command signals added with the abnormality information.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: April 25, 2017
    Assignee: YAZAKI CORPORATION
    Inventors: Takeshi Iwanabe, Yoshizumi Hirayama, Hidetoshi Ichiyanagi
  • Patent number: 9501239
    Abstract: The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 22, 2016
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Jong Moo Choi, Sung Roh Yoon, Jong Hwa Kim, Ik Joon Son, Sang Yup Lee
  • Patent number: 9444580
    Abstract: In various embodiments, a computer-implemented method for optimized data transfer utilizing optimized code table signaling is disclosed. In one embodiment, a computer-implemented method comprises receiving, by a processor, a digital bit stream and transforming, by the processor, the digital bit stream to an encoded digital bit stream. The encoded digital bit stream comprises at least one of a gateway channel, a composite channel, or a data channel, and any combination thereof. The computer-implemented method further comprises providing, by the processor, the encoded digital bit stream to a transmission system for transmission.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 13, 2016
    Assignee: OptCTS, Inc.
    Inventor: Bruce Conway
  • Patent number: 9405860
    Abstract: A content addressable memory (CAM) system can include a comparator core in which all of the keys of the CAM are embedded in comparator blocks. A search key can be provided to each of the comparator blocks, which can compare the search key to its embedded key and determine whether the search key matches the embedded key. The comparator blocks can be organized into paged sets in the comparator core such that only one of the comparator blocks in each paged set is selected and compares its embedded key to the search key at any given time. The comparator block selected in each paged set can be incremented until the search key has been compared to the keys embedded in all of the comparator blocks of the comparator core.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 2, 2016
    Assignee: L-3 Communications Corp.
    Inventor: Larry R. Trout
  • Patent number: 9378192
    Abstract: A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moshe Schwartz, Hong Rak Son, Jun Jin Kong, Jung Soo Chung
  • Patent number: 9164835
    Abstract: An operating method of a nonvolatile memory device controller includes generating a code word through polar encoding of information bits, reading a mapping pattern, generating a repeated mapping pattern through iteration of the mapping pattern, and mapping each bit of the code word onto a specific bit of multi-bit data of the nonvolatile memory device, based upon the repeated mapping pattern.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 20, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Kijun Lee, Dong-Min Shin, Kyeongcheol Yang, Seung-Chan Lim, Junjin Kong, Myungkyu Lee
  • Patent number: 9043683
    Abstract: A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert
  • Patent number: 9009558
    Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 14, 2015
    Assignee: LG Electronics Inc.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 8977936
    Abstract: The invention provides WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. In one coding, if the code corrects two/three errors, it has two/three parts of redundancy bits. For double error correction, if only one part of the redundancy bit has no errors then it is possible to correct one error. For triple error correction, if only one/two parts of the redundancy bits have no errors then it is possible to correct one/two errors. Codes that correct/detect a single, two and three cell-erasures are provided. A code that has three roots, ?1, ?2, ?3, each of which is a primitive element and where every pair of roots generates a double error correcting code, is provided. Codes and coding utilizing a triple error correcting WOM code that can correct an arbitrary number of errors are provided.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 10, 2015
    Assignee: The Regents of the University of California
    Inventors: Eitan Yaakobi, Paul Siegel, Alexander Vardy, Toby Wolf
  • Patent number: 8972828
    Abstract: A method of error mitigation for transferring packets over a chip-to-chip data interconnect using a high speed interconnect protocol, the method including grouping a pre-selected number of high speed interconnect protocol words to form a protection frame, adding at least one additional error protection bit to each word in the group, adding a synchronization bit to each word, using the synchronization bit in a first word in each frame for synchronization of the protection frame and detecting and correcting a single bit error in the protection frame using the additional error protection bits, thereby reducing packet drop when the frames are transferred over the high speed data interconnect.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 3, 2015
    Assignee: Compass Electro Optical Systems Ltd.
    Inventors: Niv Margalit, Eyal Oren, Rami Zemach, Dan Zislis
  • Patent number: 8938662
    Abstract: A data storage system includes a data storage array configured for de-duplication of duplicate data therein by: identification of a plurality of portions of data; a comparison of each portion of the data to identify duplicate data and identification of a link associated with each duplicate data; a determination of whether a Hamming link-separation-distance of the identified link is greater than twice a Hamming radius of an error correction code in the data storage system; and replacement of the duplicate data with the identified link when it is determined that the Hamming link-separation-distance is greater than twice the Hamming radius.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert Haas, Nils Haustein, Craig Anthony Klein, Ulf Troppens, Daniel James Winarski
  • Patent number: 8917194
    Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 23, 2014
    Assignee: Apple, Inc.
    Inventor: Colin Whitby-Strevens
  • Publication number: 20140365847
    Abstract: Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 11, 2014
    Inventor: Hanan WEINGARTEN
  • Patent number: 8887020
    Abstract: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols (subject to the resolution of the key used) can be generated, if needed. The output symbols are information additive such that a received output symbol is likely to provide additional information for decoding even when many symbols are already received. The output symbols are such that a collection of received output symbols can provide probabilistic information to support error correction.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: November 11, 2014
    Assignee: Digital Fountain, Inc.
    Inventor: M. Amin Shokrollahi
  • Patent number: 8887028
    Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Bueb
  • Patent number: 8854241
    Abstract: A method and system for monitoring an output of an electronic processing component which detects an out-of-range value in the output of the electronic processing component during one time period during which one channel of input channels of a time multiplexer provides an input signal to the electronic processing component. Corrective actions are performed based on the detected out-of-range value. The corrective actions including excluding further multiplexing of signals from the one channel of the input channels.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 7, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Gary Hess, Kirk Lillestolen
  • Patent number: 8843802
    Abstract: The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1<w0 and w1<w0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w1.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Makoto Noda
  • Patent number: 8826107
    Abstract: A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag. A hamming distance may be calculated between the first codeword and the second codeword. If the hamming distance is less than or equal to a threshold, a cache hit may be signaled. If the hamming distance is above the threshold, a cache miss may be signaled.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Arkady Bramnik
  • Publication number: 20140237316
    Abstract: A method of encoding a data set including one or more n-bit pre-coded symbols in an encoder of a computing system includes determining a plurality of n+2-bit code words, each of the plurality of n+2-bit code words having two or greater Hamming distance from one another. The method further includes mapping each of the plurality of n+2-bit code words to a corresponding source symbol, receiving the one or more n-bit pre-coded symbols at the encoder, matching each n-bit pre-coded symbol to a corresponding n+2-bit code word based on the mapping to produce encoded data. and outputting the encoded data.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Inventor: Andras Tantos
  • Patent number: 8806305
    Abstract: A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 12, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Steven Przybylski
  • Patent number: 8799747
    Abstract: Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: August 5, 2014
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Seekins, Mark Allen Gaertner, Kevin Gomez
  • Patent number: 8793550
    Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 20 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 20-bit length corresponding to columns of the code generation matrix. If “A” is 10, individual basis sequences of the code generation matrix correspond to column-directional sequences of a specific matrix composed of 20 rows and 10 columns. The specific matrix is made from 20 rows of the (32,10) code matrix used for TFCI coding were selected.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: July 29, 2014
    Assignee: LG Electronics Inc.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 8782493
    Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke
  • Patent number: 8775899
    Abstract: An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Limited
    Inventor: Shiro Kamoshida
  • Publication number: 20140189472
    Abstract: A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag. A hamming distance may be calculated between the first codeword and the second codeword. If the hamming distance is less than or equal to a threshold, a cache hit may be signaled. If the hamming distance is above the threshold, a cache miss may be signaled.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Alexander GENDLER, Arkady BRAMNIK
  • Patent number: 8769384
    Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: July 1, 2014
    Assignee: ATI Technologies ULC
    Inventors: Sergiu Goma, Milivoje Aleksic
  • Patent number: 8745459
    Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: June 3, 2014
    Assignee: LG Electronics Inc.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 8745462
    Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of minimum Hamming distance.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 3, 2014
    Assignee: LG Electronics Inc.
    Inventors: Dong Wook Roh, Joon Kui Ahn, Nam Yul Yu, Jung Hyun Cho, Yu Jin Noh, Ki Jun Kim, Dae Won Lee
  • Patent number: 8732553
    Abstract: The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Nagadomi, Daisaburo Takashima
  • Patent number: 8732543
    Abstract: In embodiments, data may be encoded based on a tensor product code by encoding incoming data to produce first codewords, and encoding the first codewords to produce second codewords. The incoming data may be combined with the second codewords to produce messages, which can then be transmitted and/or stored. Decoding a received message may include encoding a data portion to produce an intermediate code, and decoding the intermediate code using a codeword portion of the message to produce a corrected codeword. The data portion may then be decoded using the corrected codeword to recover data from the message.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8732551
    Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incoporated
    Inventors: Kai Chirca, Timothy D. Anderson, Amitabh Menon
  • Patent number: 8718184
    Abstract: In a chip-to-chip communication system and apparatus, a set of physical signals to be conveyed over a communication bus is provided, and mapped to a codeword of a vector signaling code using the physical signals and a state information, wherein a codeword is representable as a vector of plurality of real-valued components, and wherein a vector signaling code is a set of codewords in which the components sum to zero and for which there is at least one component and at least three codewords having different values in that component; and wherein the state information is a plurality of information present in continuous or discrete form which may have been obtained from previous codewords transmitted over the communication bus.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 6, 2014
    Assignee: Kandou Labs S.A.
    Inventors: Harm Cronie, Amin Shokrollahi
  • Patent number: 8719684
    Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to techniques for accurately determining a number of data symbols in a data packet. The techniques provided herein may allow a receiving terminal to correct number of symbol calculations based on such ambiguous length field values.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 6, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Didier Johannes Richard Van Nee, Geert Arnout Awater
  • Patent number: 8707128
    Abstract: An apparatus and a method are provided for encoding and decoding in a broadcasting/communication system using a Low Density Parity Check (LDPC) code. A weight-1 position sequence conversion procedure is performed on an initial parity check matrix. Shortening is applied on an information word. A codeword is generated by LDPC encoding the information word using a parity check matrix generated by performing the weight-1 position sequence conversion procedure. Puncturing is then applied to the codeword.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Se-Ho Myung, Hong-Sil Jeong
  • Patent number: 8694872
    Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m?1 is received. A code word with length N=2m?1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: April 8, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Manish Goel
  • Patent number: 8694867
    Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Christopher Bueb
  • Patent number: 8694862
    Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: April 8, 2014
    Assignee: ARM Limited
    Inventors: Yiannakis Sazeides, Emre Özer, Daniel Kershaw, Jean-Baptiste Brelot