Forward Correction By Block Code Patents (Class 714/752)
  • Patent number: 11003375
    Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 10999011
    Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 4, 2021
    Inventors: Hong-Sil Jeong, Sung-Ryul Yun, Hyun-Koo Yang, Se-Ho Myung, Alain Mourad, Ismael Gutierrez
  • Patent number: 10999004
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 4, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10992321
    Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rater is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 27, 2021
    Assignee: Saturn Licensing LLC
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
  • Patent number: 10985780
    Abstract: Provided herein may be an error correction circuit, and a memory controller and a memory system. The error correction circuit may include an encoder configured to generate a codeword comprising a message part, a first parity part, and a second parity part, and a decoder configured to perform error correction decoding using read values corresponding to at least a portion of the codeword, wherein, the decoder is configured to perform error correction decoding based on a first or a second error correction ability such that error correction decoding using the first error correction ability is performed using partial read values corresponding to a partial codeword including the message part and the first parity part, and error correction decoding using the second error correction ability is performed using read values corresponding to the entire codeword, and wherein the second error correction ability is greater than the first error correction ability.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Kwang Hyun Kim
  • Patent number: 10983858
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first sub-data of a plurality of sub-data of a first data and generating a first error detecting code corresponding to the first sub-data; receiving a second sub-data of the plurality of sub-data of the first data and generating a second error detecting code corresponding to the second sub-data; combining the first error detecting code and the second error detecting code to obtain a third error detecting code, wherein the third error detecting code is used to check whether a second data formed by combining the first sub-data and the second sub-data has an error; and storing the second data and the third error detecting code into a rewritable non-volatile memory module.
    Type: Grant
    Filed: September 28, 2019
    Date of Patent: April 20, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Li-Chun Liang
  • Patent number: 10979175
    Abstract: Encoded information corresponding to the encoded source frames and the one or more previous frames is unpackaged from each data packet. Each data packet in the plurality contains encoded information corresponding to a source frame in a sequence encoded at a first bitrate and one or more previous frames in the sequence encoded as forward error correction (FEC) frames at a second bitrate that is equal to or lower than the first bitrate. The encoded source frames are decoded to generate corresponding decoded source frames. Encoded FEC frames that correspond to a given source frame for which encoded information is missing are decoded to generate corresponding decoded FEC frames. A reconstructed frame is generated corresponding to the given source frame using the one or more decoded FEC frames. The decoded source to frames and the reconstructed missing frame are stored in a memory and/or presented with a display.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 13, 2021
    Assignee: SONY INTERACTIVE ENTERTAINMENT LLC
    Inventors: Kim-Huei Low, Kelvin Yong
  • Patent number: 10977125
    Abstract: A data storage system performs operations including receiving a data write command specifying data to be written; selecting an irregular LDPC encoding scheme of a plurality of available irregular LDPC encoding schemes available to the encoder in accordance with (i) a working mode of the data storage system, (ii) device-specific criteria and/or (iii) a data type of the specified data; and encoding the specified data to be written using the selected irregular LDPC encoding scheme.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Evgeny Mekhanik, Ran Zamir, Eran Sharon
  • Patent number: 10979210
    Abstract: Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventor: Ben J. Jones
  • Patent number: 10970363
    Abstract: Examples are disclosed that relate to reading stored data. The method comprises obtaining a representation of a measurement performed on a data-storage medium, the representation being based on a previously recorded pattern of data encoded in the data-storage medium in a layout that defines a plurality of data locations. The method further comprises inputting the representation into a data decoder comprising a trained machine-learning function, and obtaining from the data decoder, for each data location of the layout, a plurality of probability values, wherein each probability value is associated with a corresponding data value and represents the probability that the corresponding data value matches the actual data value in the previously recorded pattern of data at a same location in the layout.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 6, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ioan Alexandru Stefanovici, Benn Charles Thomsen, Alexander Lloyd Gaunt, Antony Ian Taylor Rowstron, Reinhard Sebastian Bernhard Nowozin
  • Patent number: 10965398
    Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 10965399
    Abstract: Method and apparatus for transmission and reception with polar codes are provided to support up to 16 permutations or transformation mappings. For example, 16 versions of copies able to be soft-combined for PBCH or any other data channel or control channel are suggested if the mother code length is 256 or 512 or 1024. With the new design, up to 16 different versions can be used to soft combined to improve the performance. Some sequences are provided as examples to support 16 different permutation patterns. The inverse of these sequences also have the feature to support 16 different permutation patterns.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 30, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Vladimir Gritsenko, Aleksei Eduardovich Maevskii, Hejia Luo, Rong Li, Jun Wang
  • Patent number: 10951408
    Abstract: A method for securing a blockchain and incentivizing the storage of blockchain data using a publicly verifiable proof of retrievability (PoR) includes receiving a PoR transaction having a PoR proof; determining whether the PoR proof is a verified PoR proof; and based upon determining that the PoR proof is a verified PoR proof, incorporating, by a block creator node, the PoR transaction into a new block of the blockchain.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 16, 2021
    Assignee: NEC CORPORATION
    Inventors: Wenting Li, Ghassan Karame
  • Patent number: 10951241
    Abstract: A transmitting device for generating a digital television broadcast signal incudes circuitry configured to receive data to be transmitted in a digital television broadcast signal and perform LDPC (low density parity check) encoding on input bits of the received data according to a parity check matrix initial value table of an LDPC code having a code length of 16200 bits and a code rate of 10/15 to generate an LDPC code word. The LDPC code enables error correction processing to correct errors generated in a transmission path of the digital television broadcast signal. The LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Saturn Licensing LLC
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 10944429
    Abstract: A data accessing method using data protection with aid of a parity check matrix having partial sequential information, and associated apparatus such as memory device, memory controller, and decoding circuit thereof are provided. The data accessing method may include: in response to a read request, starting receiving protected data corresponding to the read request from predetermined storage space; generating the parity check matrix; performing syndrome calculation based on the parity check matrix according to a codeword to generate and output a syndrome for the codeword; performing error detection according to the syndrome to generate and output a decoding result signal, and performing error location decoding according to the syndrome to generate and output an error location; performing error correction of the codeword, to correct an error at the error location of the codeword; and performing further processing according to the one or more codewords obtained from the protected data.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: March 9, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10944508
    Abstract: This application provides a data processing method and a communications device. The data processing method includes: determining, by a first communications device, NCB, based on a size of the circular buffer of the communications device and an information processing capability of a second communications device; and obtaining, by the first communications device, a second encoded bit segment from a first encoded bit segment having a length of NCB. According to the data processing method and the communications device provided in this application, decoding complexity of the communications device can be reduced and communication reliability can be improved.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chen Zheng, Liang Ma, Xin Zeng, Xiaojian Liu, Yuejun Wei
  • Patent number: 10944425
    Abstract: Devices and methods are disclosed for generating on the basis of a first protograph matrix P1 of size m×n, wherein the first protograph matrix P1 defines a first code H1, a second protograph matrix P2 of size (m+d)×(n+d), wherein the second protograph matrix P2 defines a second code H2. The device comprises a processor configured to: generate an auxiliary protograph matrix P? of size (m+d1)×(n+d1) on the basis of the first protograph matrix P1 using row splitting; generate d2 random integer numbers, wherein d2=d?d1; generate a binary matrix M of size d2×(n?m), wherein rows of the binary matrix M are generated on the basis of the d2 random integer numbers; generate a matrix M? by lifting the binary matrix M; Other operation steps are also included.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 9, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Vasily Stanislavovich Usatyuk, Nikita Andreevich Polianskii, Ilya Viktorovich Vorobyev
  • Patent number: 10944476
    Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using nDSQ format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices, such as spine switches and leaf switches, within a spine-leaf network architecture, which allows large amount of data to be shared among servers.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 9, 2021
    Assignee: INPHI CORPORATION
    Inventors: Jamal Riani, Sudeep Bhoja
  • Patent number: 10938514
    Abstract: A data transmission method, a data sending device, and a data receiving device are provided. The method includes: encoding, by a data sending device, information data by using a low-density parity-check (LDPC) code matrix, to obtain a bit sequence, where the bit sequence includes a first bit sequence, and the first bit sequence includes at least one information bit in the bit sequence; interleaving, the first bit sequence to obtain a first interleaved bit sequence; performing, modulation based on the first interleaved bit sequence to obtain a sending signal, and sending the sending signal. The method also includes: demodulating, by a data receiving device, a receiving signal to obtain a soft value sequence; and de-interleaving, the soft value sequence, to obtain a soft value sequence of a first bit sequence. This can improve a capability of an LDPC code resisting burst interference.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaojian Liu, Yuejun Wei, Xin Zeng
  • Patent number: 10931307
    Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Ting Luo
  • Patent number: 10931397
    Abstract: This application provides a method for communicating a modulation and coding scheme (MCS). A terminal device obtains a modulation order, a code rate, or a spectral efficiency, determines an index of a reference MCS from a mapping table based on the obtained modulation order, code rate, or spectral efficiency, and reports the index of the reference MCS to a network device. The mapping table includes one or more mapping relationships between an MCS index and a modulation order, a code rate, or a spectral efficiency. The terminal device may process uplink or downlink data based on the determined MCS, thereby improving data transmission reliability.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 23, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jian Wang, Lingchen Huang, Yunfei Qiao, Rong Li, Jun Wang, Yinggang Du, Yiqun Ge
  • Patent number: 10931400
    Abstract: The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate beyond the 4G communication system such as LTE. A decoding method using a polar code according to an embodiment of the present disclosure comprises the steps of: determining a first function for decoding input bits and a second function, which is independent from a log likelihood ratio (LLR) value of a previous input bit by the first function; and decoding the input bits in parallel using the first function and the second function. Also, the method comprises the steps of: determining an internal frozen bit using at least one input frozen bit which has a predetermined value of a predetermined position from among the input bits; and determining LLR values for layer bits sequentially from the higher layers of N layers.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Jang, Woo-Myoung Park, Jae-Yoel Kim, Seok-Ki Ahn, Chi-Woo Lim
  • Patent number: 10924210
    Abstract: Embodiments provide a polar code encoding and decoding method in a communications system. Under the method, a basic quantized sequence can be obtained. The basic quantized sequence includes a quantized value used to represent reliability corresponding to a polarized subchannel. A target quantized sequence based on the basic quantized sequence can also be obtained. A relative magnitude relationship between elements in the target quantized sequence is nested with a relative magnitude relationship between elements in the basic quantized sequence. K largest quantized values in the target quantized sequence can be determined based on a non-fixed bit length K and polarized subchannels corresponding to the K largest quantized values can be used as a non-fixed bit position set. Polar code encoding or decoding can be performed based on the non-fixed bit position set.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: February 16, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ying Chen, Rong Li, Huazi Zhang, Hejia Luo, Gongzheng Zhang
  • Patent number: 10924136
    Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. LDPC coding for information bits with an information length K=N×r is performed on the basis of an extended parity check matrix having rows and columns each extended by a predetermined puncture length L with respect to a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16, so that an extended LDPC code having parity bits with a parity length M=N+L?K is generated. Then, a head of the information bits of the extended LDPC code is punctured by a puncture length L, so that a punctured LDPC code with the code length N of 69120 bits and the coding rate r is generated. The extended parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 16, 2021
    Assignee: SONY CORPORATION
    Inventors: Makiko Yamamoto, Yuji Shinohara
  • Patent number: 10922964
    Abstract: A method is disclosed, performed by at least one apparatus, the method comprising: obtaining probe data comprising a plurality of probe samples of a multi-dimensional probe sample space, the probe data being representative of a potentially multi-modal traffic scenario; performing a cluster analysis for at least a part of the probe samples of the probe data, said cluster analysis comprising: associating at least a part of the probe samples with respective clusters, each cluster being representative of a mode of the potentially multi-modal traffic scenario.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 16, 2021
    Assignee: HERE GLOBAL B.V.
    Inventor: James Fowe
  • Patent number: 10924135
    Abstract: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus transmits, from two antennas, LDPC encoded data formed by LDPC encoding blocks. In a case of a retransmittal, the multi-antenna transmitting apparatus uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 16, 2021
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Yutaka Murakami, Kiyotaka Kobayashi, Choo Eng Yap
  • Patent number: 10911068
    Abstract: There are provided an error correction circuit and a method of operating the same. The circuit may performs error correction decoding within a maximum global iteration number G, and may include a mapper configured to generate read values quantized into g+1 levels to be used in a g-th global iteration by using read values corresponding to g number of read voltages, a node processing component configured to perform error correction decoding, during the g-th global iteration, by using the read values quantized into g+1 levels, a syndrome information management component configured to manage syndrome information corresponding to the g-th global iteration, and a global iteration control component configured to, when error correction decoding fails in the g-th global iteration, determine whether the syndrome information corresponding to the g-th global iteration satisfies a condition defined in a global iteration skip policy, and decide whether to skip (g+1)th to (G?1)th global iterations.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyung Bum Kim
  • Patent number: 10908987
    Abstract: An error handling technique for a computing device includes detecting a memory error during execution of the program instructions to generate a computational result, and generating an error message containing information about the memory error. The error message can be stored in a notification memory space, and be made available for access, for example, by a host system. The execution of the program instructions is allowed to continue to generate the computational result despite detecting the memory error. When the computation result becomes available, a confidence level of the computational result can be determined based on which program instruction or which computational stage resulted in the memory error. The confidence level can be used to assess whether the computational result is acceptable.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 2, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Amit Pandey, Ron Diamant
  • Patent number: 10911069
    Abstract: Disclosed herein are memory devices, systems, and methods of content-aware decoding of encoded data. In one aspect, an encoded data chunk is received and one or more characteristics, such as source statistics, are determined. A similar data chunk (that may, e.g., contain data of a similar type) with comparable statistics may be sought. The similar data chunk may, for example, have source statistics that are positively correlated to the source statistics of the encoded data chunk to be decoded. Decoder parameters for the encoded data may be set to correspond with decoder parameters suited to the similar data chunk. The encoded data chunk is decoded using the new decoder parameters. Decoding encoded data based on content can enhance performance, reducing decoding latency and/or power consumption.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: February 2, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Stella Achtenberg, Omer Fainzilber, Dudy David Avraham
  • Patent number: 10892860
    Abstract: There are provided a communication apparatus, method and system, and the communication apparatus, comprises: a transmitter configured to transmit a first data to a terminal and retransmit a second data to the terminal under a retransmission condition after transmitting the first data; and a circuitry configured to control a retransmission scheme for the retransmission of the second data based on at least one of a systematic bit degree and a preempted resource degree for the transmission of the first data.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 12, 2021
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Lilei Wang, Hidetoshi Suzuki
  • Patent number: 10892784
    Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Omer Fainzilber, Tommer Kuper Lotan, Eran Sharon, Ofir Pele, Stella Achtenberg, Ran Zamir
  • Patent number: 10892779
    Abstract: An error correction device includes a bit reliability value determination circuit configured to determine bit reliability values corresponding to hard decision bits, based on soft decision bit sets corresponding to the hard decision bits; and a decoder including a variable node configured to receive and store the hard decision bits and the bit reliability values, and perform a decoding operation for the hard decision bits by restoring reliability values from the bit reliability values. The reliability values correspond to elements except a decision symbol configured by the hard decision bits, in a Galois field (GF) defined in the variable node. All necessary reliability values are not transmitted to each variable node, instead, compressed reliability values are transmitted to the variable node. The variable node receives and retains the compressed reliability values, restores necessary reliability values, and uses them in a decoding operation.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Kim
  • Patent number: 10892776
    Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During each LDPC decoding iterative operation in the decoding phase: the check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit is configured to: determine a syndrome weight according to the syndrome from the check-node circuit; obtain a previous codeword from a variable-node memory without obtaining a channel value from a channel-value memory; perform bit-flipping on one or more codeword bits in the previous codeword according to the calculated syndrome weight to generate an updated codeword; and subtract the previous codeword from the updated codeword to obtain the codeword difference.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 12, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10892874
    Abstract: A first channel for carrying Layer 2 messages carries data that will not be retransmitted and for which decoding-related information need not be retained by the receiving node in the event of an unsuccessful decoding of the data, while a second channel carries data that will be retransmitted in the event that a negative acknowledgement is received by the transmitting node. In an example method, first and second subsets of Layer 2 messages are received on first and second physical data channels, respectively. Decoding-related information for unsuccessfully decoded messages in the first subset is retained for use with subsequent retransmissions, while decoding-related information for unsuccessfully decoded messages in the second subset is discarded without waiting for retransmissions. Acknowledgements or negative acknowledgements are sent for messages in the first subset, but may or may not be sent for messages in the second subset, in various embodiments.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 12, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Jonas Fröberg Olsson, Erik Eriksson, Pål Frenger, Martin Hessler
  • Patent number: 10886944
    Abstract: A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 5, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsie-Chia Chang, Yen-Chin Liao, Shu Lin
  • Patent number: 10886946
    Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 5, 2021
    Assignee: PANASONIC CORPORATION
    Inventor: Mihail Petrov
  • Patent number: 10880040
    Abstract: Overhead associated with data re-protection during scaling out and/or scaling up of a distributed cloud storage system can be reduced. A coding matrix that is to be utilized for erasure coding in a potential final configuration of the distributed cloud storage can be determined. During initial data protection, a portion of the coding matrix can be utilized to determine coding chunks for protecting data chunks stored within different geographical zones of the distributed cloud storage system. When additional zones are added to the distributed cloud storage system, a larger portion of the coding matrix can be utilized to erasure code the new configuration and accordingly, the existing coding chunks are considered as partially complete. Further, the partially complete coding chunks can be combined with data chunks stored within the newly added zones and coefficients of the larger portion of the coding matrix to generate complete coding chunks.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 29, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Konstantin Buinov
  • Patent number: 10879939
    Abstract: The present disclosure relates to decoding methods and devices. One example method includes receiving N LLRs corresponding to a to-be-decoded signal, where N is a code length, classifying K decoded bits into reliable bits and unreliable bits based on at least one of a prior LLR or a posterior LLR, generating M decoding paths based on the N LLRs and a preset rule, and selecting each stage of target decoding path based on PM values of the M decoding paths to obtain a decoding result of each stage of decoded bit.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jun Wang, Rong Li, Huazi Zhang, Xian Meng, Xiaocheng Liu
  • Patent number: 10879928
    Abstract: A receiver is configured for receiving a signal including a training field and a payload over a communication channel. The receiver includes a channel estimator, a scaling factor calculator, a metric calculator and a decoder. The channel estimator is configured to estimate values of a parameter of the communication channel based on the training field of the received signal. The scaling factor calculator is configured to calculate a scaling factor based on the values of the parameter of the communication channel. The metric calculator is configured to calculate soft decoding metrics for use in decoding data carried by the payload of the received signal, including scaling the soft decoding metrics by the scaling factor. The decoder is configured to decode the data carried by the payload of the received signal using the scaled soft decoding metrics.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 29, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Vijay Ahirwar, Sri Varsha Rottela, B Hari Ram
  • Patent number: 10879935
    Abstract: A semiconductor memory system includes: a semiconductor memory device for storing a code word; a decoder for decoding stored the code word based on a parity check matrix formed of sub-matrices to generate decoded data; and a channel for coupling the semiconductor memory device to the decoder and providing the decoder with the stored code word, wherein the decoder includes: a variable node selecting device for sequentially selecting sub-matrices sharing the same layer of the parity check matrix and sequentially selecting variable nodes respectively corresponding to columns forming the selected sub-matrices; a variable node updating device for updating the selected variable nodes based on a channel message and check node messages provided to the selected variable nodes; and a check node updating device for updating the check nodes based on variable node messages provided to the check nodes coupled to the selected variable nodes.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae-Sung Kim
  • Patent number: 10879931
    Abstract: The present disclosure relates to methods and apparatuses for generating a low-density parity-check code basis matrix. One example method includes obtaining a low-density parity-check code mother matrix, and generating a 1st matrix to a qth matrix one by one, where q is a preset positive integer. A Pth matrix in the 1st matrix to the qth matrix is generated in the following manner: selecting a to-be-replaced matrix element in a (P?1)th matrix, where the to-be-replaced matrix element is a matrix element having a value that is not ?1 in the (P?1)th matrix, determining a Pth shift factor corresponding to the to-be-replaced matrix element, and replacing the to-be-replaced matrix element in the (P?1)th matrix with the Pth shift factor to obtain the Pth matrix whose cycle length property is better than a cycle length property of the (P?1)th matrix.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chen Zheng, Yuejun Wei, Liang Ma, Xin Zeng
  • Patent number: 10873343
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong, Daniel Ansorregui Lobete, Belkacem Mouhouce
  • Patent number: 10873346
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 22, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10868636
    Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. Example embodiments of a modulation and coding scheme (MCS) for generating a rate 1/2 length 1344 LDPC codeword are described. The method includes segmenting a stream of data bits into 336 bit size segments, adding 336 padding bits to each 336 bit size segment to generate corresponding 672 bit size source words, applying a 1/2 rate low density parity check (LDPC) coding to each 672 bit size source word to generate a corresponding 1344 bit size codeword that includes 672 parity bits; and for each codeword, substituting the 336 padding bits with 336 bits derived from the data bits included in the codeword, to provide a 1344 bit size codeword that includes a concatenation of the 336 data bits, the 336 bits derived from the data bits, and 672 parity bits.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yan Xin, Min Yan
  • Patent number: 10868566
    Abstract: An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyeongcheol Yang, Sunghye Cho, Youngjun Hwang, Junjin Kong, Hong Rak Son, Dong-Min Shin, Kijun Lee
  • Patent number: 10868567
    Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. The Methods and devices use a LDPC matrix Hn of lifting factor Z. The LDPC matrix Hn comprises a plurality of submatrices, each submatrix having a size of Z×Z, and at least one submatrix has m1 diagonals of “1” m1 is an integer>=2.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Guido Montorsi, Sergio Benedetto, Yan Xin, Wei Lin, Min Yan
  • Patent number: 10862510
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Joong Kim, Se-ho Myung, Hong-sil Jeong
  • Patent number: 10855315
    Abstract: Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: December 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Sun, Taesang Yoo, Tao Luo
  • Patent number: 10853187
    Abstract: Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 1, 2020
    Assignee: Quantum Corporation
    Inventors: Suayb S. Arslan, Turguy Goker, Roderick B. Wideman
  • Patent number: 10848868
    Abstract: In an example, an audio signal may be routed to an audio device based on an indication of audio device historical usage, a measure of audio quality of the audio device, or a combination thereof.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 24, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Mohit Gupta