Forward Correction By Block Code Patents (Class 714/752)
  • Patent number: 11316541
    Abstract: A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: April 26, 2022
    Inventors: Linfang Wang, Rekha Pitchumani, Zongwang Li
  • Patent number: 11316539
    Abstract: Various embodiments provide for encoding and decoding data channel information with polar codes where the frozen bits of the information block can be set to a scrambling identifier based on the device ID, cell ID, or some other unique identifier instead of being set to null. The frozen bits can be identified based on the type of polar code being used, and while the non-frozen bits can be coded with the data link data, the frozen bits can be coded with the scrambling identifier. In an example where there are more frozen bits than bits in the scrambling identifier, the most reliable of the frozen bits can be coded with the scrambling identifier. In another example, the frozen bits can be set to the CRC bits, which can then be masked by the scrambling identifier.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 26, 2022
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Arunabha Ghosh
  • Patent number: 11316535
    Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11316534
    Abstract: Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0?R1?1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0?R2?R1?1.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 26, 2022
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Jin Xu, Jun Xu, Liguang Li
  • Patent number: 11316545
    Abstract: Embodiments of this application provide a data transmission method, a communications device, and a storage medium to reduce a quantity of cross-connections of an intermediate node in a network. In the embodiments of this application, Q first code block streams that are obtained are multiplexed into one second code block stream for transmission, a coding type of the first code block streams is M1/N1 bit coding, a coding type of the second code block stream is M2/N2 bit coding, and bits corresponding to code blocks in the Q first code block streams are carried in a payload area of a code block in the second code block stream. In other words, in the solutions provided by the embodiments of this application, the code block streams are multiplexed and demultiplexed based on a code block granularity.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 26, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qiwen Zhong, Xiaofei Xu, Xiaojun Zhang, Lehong Niu
  • Patent number: 11309915
    Abstract: A hardware efficient implementation of a threshold modified attenuated min-sum algorithm (TAMSA”) and a threshold modified offset min-sum algorithm (“TOMSA”) that improve the performance of a low density parity-check (“LDPC”) decoder by reducing the bit error rate (“BER”) compared to the conventional attenuated min-sum algorithm (“AMSA”), offset min-sum algorithm (“OMSA”), and the min-sum algorithm (“MSA”). Embodiments of the present invention preferably use circuit optimization techniques, including a parallel computing structure and lookup tables, and a field-programmable gate array (“FPGA”) or application specific integrated circuit (“ASIC”) implementation.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 19, 2022
    Assignee: Arrowhead Center, Inc.
    Inventors: David G. Mitchell, Yanfang Liu
  • Patent number: 11309972
    Abstract: A machine-implemented method of constructing multidimensional constellations having increased minimum distances between the constellation symbols thereof compared to those of comparable conventional constellations, e.g., QPSK and QAM constellations. An example multidimensional constellation so constructed may have eight or more dimensions and may be mapped onto degrees of freedom selected from, e.g., time, space, wavelength, polarization, and the in-phase and quadrature-phase components, of the optical field. The disclosed method is beneficially used to generate multidimensional modulation formats characterized by constant total optical transmit power per modulation time slot and/or applicable to the transmission of multidimensional constellation symbols having separate parts thereof primarily carried by different respective guided modes of the optical fiber. Example methods and apparatus for implementing such multidimensional modulation formats are also disclosed herein.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 19, 2022
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Juan Ignacio Bonetti, Rene-Jean Essiambre, Muralidharan Kodialam
  • Patent number: 11303461
    Abstract: The inventive concept provides a security device capable of reducing an area of a die required for implementation of a stable PUF by increasing the value of entropy from a predefined number of entropy sources and/or minimizing a blind zone of a validity checking module. The security device uses an asynchronous configuration to minimize a blind zone. In various embodiments of the inventive concept, the blind zone is generated only in a period when a reset signal is at a first logic level. Therefore, it is possible to minimize the blind zone by minimizing a period in which the reset signal is at such logic level. A semiconductor device, semiconductor package, and/or smart card can be provided with such security device, as well as a method for determining a validity of a random signal using a semiconductor security device.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 12, 2022
    Inventors: Ihor Vasyltsov, Karpinskyy Bohdan, Kalesnikau Aliaksei, Yun-Hyeok Choi
  • Patent number: 11301323
    Abstract: Read parameter estimation techniques are provided that obtain information from multiple read operations to customize read parameters for data recovery. One method comprises performing the following steps, in response to a decoding failure of a page of a memory or a codeword of the memory: obtaining at least three read values of the page or codeword; and processing the at least three read values to determine read parameters comprising: (i) a log likelihood ratio, and/or (ii) a center read reference voltage, wherein the determination is based on a signal count of a number of bits falling in particular regions of multiple regions of the memory and wherein the determined read parameters are used for a decoding of the page or codeword following the decoding failure and/or a subsequent read operation following a successful decoding of the page or codeword.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 12, 2022
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wang, Ara Patapoutian, Bengt Anders Ulriksson
  • Patent number: 11303299
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 11303498
    Abstract: A data transmission method includes generating a physical layer data frame, where the physical layer data frame includes data on which probability non-uniform modulation is performed and indication information, where the indication information indicates demodulation parameters for performing probability non-uniform demodulation on the data, where the demodulation parameters include a modulation scheme for probability non-uniform modulation, a modulation order for probability non-uniform modulation, and at least one of a probability of each constellation symbol on which probability non-uniform modulation is performed, or a mapping relationship between each constellation symbol on which probability non-uniform modulation is performed and a bit stream, sending the physical layer data frame to a receive end, receiving the physical layer data frame, determining the demodulation parameters based on the indication information, and performing probability non-uniform demodulation on the data based on the demodulation
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 12, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei Huang, Ping Fang
  • Patent number: 11296729
    Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Christopher Joseph Bueb
  • Patent number: 11296722
    Abstract: Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Cheng Wei Song, Fabrice Jean Verplanken
  • Patent number: 11290130
    Abstract: Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 29, 2022
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Qingchao Liu, Xixian Chen, Yashar Nezami
  • Patent number: 11275358
    Abstract: A remote service system includes a first computer terminal configured to add a first signature to control information representing control content to be applied to a facility and transmit the control information and a second computer terminal configured to cause the control content represented by the control information to be applied to the facility, wherein the first computer terminal and the second computer terminal are connected by a first communication network and wherein the second computer terminal and the facility are connected by a second communication network.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 15, 2022
    Assignee: MITSUBISHI POWER, LTD.
    Inventors: Takayuki Kono, Kenji Takao, Daisuke Goto, Hiroyasu Ishigaki
  • Patent number: 11277153
    Abstract: Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: March 15, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Ivan Leonidovich Mazurenko, Aleksandr Aleksandrovich Petiushko, Chaolong Zhang
  • Patent number: 11271589
    Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11258460
    Abstract: This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 22, 2022
    Assignee: Codelucida, Inc.
    Inventors: David Declercq, Benedict J. Reynwar, Vamsi Krishna Yella
  • Patent number: 11251809
    Abstract: A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: February 15, 2022
    Assignee: Technische Universiteit Eindhoven
    Inventors: Alex Enrique Alvarado Segovia, Yi Lei, Bin Chen, Gabriele Liga
  • Patent number: 11239863
    Abstract: The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 1, 2022
    Assignee: Saturn Licensing LLC
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
  • Patent number: 11239860
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 1, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 11239864
    Abstract: A system and method for erasure coding. The method includes distributing a plurality of data chunks according to a mirroring scheme, wherein the plurality of data chunks is distributed as a plurality of rows among a plurality of non-volatile memory (NVM) nodes, wherein the mirroring scheme defines a plurality of groups, each group including a subset of the plurality of data chunks, wherein each data chunk in a group has a role corresponding to a relative position of the data chunk within the group, wherein data chunks included in the plurality of groups having the same relative positions within their respective groups have the same role, wherein each row of the plurality of rows includes at least one summation data chunk that is a function of at least one data chunk included in the row and of at least one extra data chunk included in at least one other row.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 1, 2022
    Assignee: Vast Data Ltd.
    Inventors: Renen Hallak, Shachar Fienblit, Yogev Vaknin, Eli Malul, Lior Klipper
  • Patent number: 11239944
    Abstract: Methods and devices for performing rate adaptive forward error correction using a flexible irregular error-correcting code, such as a staircase code. Each codeword of the ECC uses one of two or more different encodings, each encoding having a different number of parity bits. By adjusting the proportions of codewords of each encoding included in a data block, the FEC overhead can be finely adjusted, achieving flexible levels of FEC overhead in response to increased or decreased noise or perturbations in a communication channel. Three types of flexible irregular zipper codes are described: general zipper codes, staircase codes, and oFEC codes.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 1, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Chunpo Pan
  • Patent number: 11233530
    Abstract: Wireless communication devices are adapted to facilitate information sequences included in frozen sub-channels of polar coded transmissions. According to one example, an apparatus can generate a mask sequence based on a plurality of parameters, including at least one of a transmitting-device-specific sequence or a receiving-device-specific sequence. In some examples, the frozen bits may be masked with the mask sequence, and an information block may be encoded utilizing polar coding. In other examples, the mask sequence may be compared to the frozen bits of a received information block, and the received information block may be determined as intended for the apparatus when the mask sequence matches to the frozen bits. Other aspects, embodiments, and features are also included.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 25, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Gaojin Wu, Chao Wei, Jing Jiang
  • Patent number: 11233531
    Abstract: Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 25, 2022
    Assignee: ZTE CORPORATION
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11233643
    Abstract: A method for execution by a processing module of a distributed storage includes transmitting a request to retrieve a set of encoded data slices (EDSs) to a plurality of storage nodes followed by receiving a threshold number of EDSs from one or more of the plurality of storage nodes, and decoding the EDSs to produce a transposed encrypted data segment. The method continues with the processing module partitioning the encrypted data segment into an encoded encryption key and encrypted data, performing a hash function on the encrypted data to produce a digest resultant and combining the digest resultant with the encoded encryption key to generate combined key data. The method then continues with decoding the combined key data to recover an encryption key and decrypting the encrypted data using the encryption key to recover a data segment.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 25, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Wesley B. Leggette, Jason K. Resch
  • Patent number: 11228390
    Abstract: Provided in an embodiment of the invention are a method for transmitting data, a receiving-end device, and a transmitting-end device. The method comprises: a receiving-end device receiving, on a time unit, a first part and at least one second part of data, wherein first modulation and coding processing is performed on the first part, and second modulation and coding processing is performed on the at least one second part; and the receiving-end device performing demodulation on the first part and the at least one second part. The method for transmitting data, the receiving-end device, and the transmitting-end device provided in the embodiment of the invention achieve a higher frequency spectrum efficiency, thereby realizing fast demodulation.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 18, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: YaNan Lin
  • Patent number: 11223743
    Abstract: An image processing system comprises a first image processing apparatus and a second image processing apparatus. The first image processing apparatus obtains image data and transmits, to the second image processing apparatus, the obtained image data and information relating to the image data. The second image processing apparatus receives the image data and sets a condition for determining whether the image data is the image data to be processed, and determines whether or not the received image data is the image data to be processed, based on the set condition and the information. The second image processing apparatus executes, when it is determined that the received image data is the image data to be processed, image processing on the image data, based on the information and stores a result of the execution of the image processing.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 11, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Ken Achiwa
  • Patent number: 11218170
    Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 4, 2022
    Assignee: Saturn Licensing LLC
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11218167
    Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to data transmission using an LDPC code.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 4, 2022
    Assignee: SONY CORPORATION
    Inventors: Makiko Yamamoto, Yuji Shinohara
  • Patent number: 11218172
    Abstract: Disclosed are: a communication technique for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system therefor. The present disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety related services, and the like) on the basis of 5G communication technology and IoT-related technology.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 4, 2022
    Assignees: Samsung Electronics Co., Ltd., Industry Foundation of Chonnam National University
    Inventors: Min Jang, Hosung Park, Jaeyoel Kim, Seokki Ahn, Hongsil Jeong
  • Patent number: 11212703
    Abstract: A method, an apparatus and an equipment for determining a transport block size are provided. The method for determining a transport block size includes: determining an initial transport block size; comparing the initial transport block size with a threshold to obtain a comparison result; quantizing the initial transport block size based on the comparison result to obtain a quantized initial transport block size; and determining a final transport block size based on the quantized initial transport block size.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 28, 2021
    Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO., LTD.
    Inventors: Yanping Xing, Jiaqing Wang, Xuejuan Gao
  • Patent number: 11206045
    Abstract: An apparatus for determining a bit index for a parity bit of a polar codeword is disclosed. Each index of a polar codeword may have an associated weight and an associated reliability value. The apparatus may compare the weights and reliability values of a group of bit indices in parallel to determine a bit index of the group associated with the lowest weight and highest reliability value. Additional groups may be processed until all of the bit indices of the polar codeword have been examined and the bit index with the lowest weight and highest reliability value is identified.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: December 21, 2021
    Assignee: Xilinx, Inc.
    Inventor: Zahid Khan
  • Patent number: 11201628
    Abstract: A transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 14, 2021
    Assignee: SONY CORPORATION
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11196598
    Abstract: Aspects of the present application provide methods and devices for using a combined QAM and APSK modulation scheme in a hybrid modulation form in order to benefit from advantages of each respective modulation scheme. The proposed hybrid modulation scheme is less sensitive to phase noise and has lower PAPR than QAM and has very similar performance as QAM with respect to AWGN.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 7, 2021
    Assignee: HUAWEI TECHNOLOGIES CANADA CO., LTD.
    Inventors: Assem Shoukry Mohamed Hussein, Vincent Charles Gaudet, Patrick Mitran, Ming Jian
  • Patent number: 11196445
    Abstract: A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: December 7, 2021
    Assignees: Nokia Technologies Oy, Alcatel Lucent
    Inventors: Keeth Saliya Jayasinghe, Yu Chen, Dongyang Du, Jie Chen
  • Patent number: 11190220
    Abstract: A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Chol Su Chae
  • Patent number: 11184033
    Abstract: A data storage device includes a nonvolatile memory device configured to read and output a plurality of data chunks; and a data processing block configured to perform decoding on the data chunks, the data processing block comprising a sequencer configured to generate a decoding information on the data chunks; and a core circuit configured to perform normal decoding on a first data chunk among the data chunks based on the decoding information, and perform fast decoding on a second data chunk among the data chunks depending on whether a result of the normal decoding satisfies a fast decoding condition, wherein the fast decoding requires a shorter execution time than the normal decoding.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyoung Lae Cho
  • Patent number: 11177835
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Patent number: 11177831
    Abstract: A method of soft decoding received signals. The method comprising defining quantisation intervals for a signal value range, determining a number of bits in each quantisation interval that are connected to unsatisfied constraints, providing, the number of bits in each quantisation interval that are connected to unsatisfied constraints, as an input to a trained model, wherein the trained model has been trained to cover an operational range of a device for soft decoding of signals, determining, using the trained model, a log likelihood ratio for each quantisation interval, and performing soft decoding using the log likelihood ratios.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 16, 2021
    Assignees: Kabushiki Kaisha Toshiba, Kioxia Corporation
    Inventors: Magnus Stig Torsten Sandell, Amr Ismail
  • Patent number: 11177906
    Abstract: An LDPC (Low-Density Parity Check) code based on a control matrix represented by a Tanner bipartite graph includes 128 variable nodes of the graph and 64 constraint nodes of the graph, the code being wherein each of the constraint nodes of the graph is connected to 7 variable nodes of the graph; each of the cycles of the graph has a length greater than or equal to 6; the minimum distance of the code is equal to or greater than a predefined threshold for minimum distance.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 16, 2021
    Assignees: SUEZ GROUPE, GRDF
    Inventor: Jean-Louis Dornstetter
  • Patent number: 11171667
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system, such as long-term evolution (LTE). The disclosure provides decoding of a low-density parity-check (LDPC) code in a wireless communication system, and a decoding method of the LDPC code may include receiving a codeword, performing decoding iterations on the codeword a predefined maximum number of times using a parity check matrix, performing partial decoding using a partial area of the parity check matrix, and determining decoding success or failure of the codeword based a result of the partial decoding.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Jang, Hyuntack Lim, Hongsil Jeong, Hayoung Yang, Joohyun Lee
  • Patent number: 11159179
    Abstract: According to some embodiments, a method of operation of a transmit node in a wireless communication system comprises performing polar encoding of a set of K information bits to thereby generate a set of polar-encoded information bits. The K information bits are mapped to the first K bit locations in an information sequence SN. The information sequence SN is a ranked sequence of N information bit locations among a plurality of input bits for the polar encoding where N is equivalent to a code length. A size of the information sequence SN is greater than or equal to K. The information sequence SN is optimized for the specific value of the code length (N). The method may further comprise transmitting the set of polar-encoded information bits.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 26, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Yufei Blankenship
  • Patent number: 11159181
    Abstract: The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: October 26, 2021
    Assignee: Sony Corporation
    Inventors: Yuji Shinohara, Makiko Yamamoto
  • Patent number: 11152956
    Abstract: A method for iteratively decoding read bits in a solid state storage device, wherein the read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises: determining a binary Tanner graph of the Q-ary LDPC code based on a binary coset representation of the Galois field GF(2r) the binary Tanner graph comprising (2r?1) binary variable nodes, (2r?1?r) binary parity-check nodes each one connected to one or more binary variable nodes according to the binary coset representation and (2r?1) binary check nodes each one connected to a respective binary variable node mapping the read bits into N symbols providing each symbol of the N symbols to a respective Q-ary variable node; providing each bit of the symbol to a respective binary variable node of the respective Q-ary variable node and iteratively decoding each symbol.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 19, 2021
    Inventor: Margherita Maffeis
  • Patent number: 11150805
    Abstract: A system and method for using free space to improve erasure code locality. The method includes logically segmenting an erasure coding data set into a stripe based on an erasure coding scheme, wherein the erasure coding data set includes a plurality of chunks, wherein the plurality of chunks includes a plurality of chunks of systematic data and a plurality of chunks of parity data, wherein the stripe includes free user data; and distributing the stripe across a plurality of non-volatile memory nodes based on the erasure coding scheme, wherein the free user data is stored in at least one memory location among the plurality of non-volatile memory nodes, wherein each non-volatile node is a unit of non-volatile memory.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 19, 2021
    Assignee: VAST DATA LTD.
    Inventor: Yogev Vaknin
  • Patent number: 11153037
    Abstract: Disclosed is a method and apparatus for encoding an erasure code for storing data. The disclosed method for encoding an erasure code comprises the steps of: (a) generating a first local parity group including two or more local parity nodes for data nodes; (b) generating at least one global parity node for the data nodes; (c) generating at least one second local parity group including two or more local parity nodes for the data nodes; and (d) storing the data nodes, the first local parity group, the second local parity group, and the global parity node. According to the disclosed method, it is possible to store and recover data safely and efficiently.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 19, 2021
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Dong-Joon Shin, Ji Ho Kim, Jin Soo Lim
  • Patent number: 11152957
    Abstract: Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: October 19, 2021
    Assignee: Cohere Technologies, Inc.
    Inventors: Vamadevan Namboodiri, Ronny Hadani, Stuart Abrams
  • Patent number: 11146291
    Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative LDPC correction process, wherein at least one iteration after a first iteration in the LDPC correction process uses a criterion based at least partially on a previous iteration or partial iteration.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Eyal En Gad, Zhengang Chen, Sivagnanam Parthasarathy, Yoav Weinberg
  • Patent number: 11146289
    Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Aman Bhatia, Zion S. Kwok, Justin Kang, Poovaiah M. Palangappa, Santhosh K. Vanaparthy