Abstract: An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m<n-k.

Abstract: A method includes identifying ACF information by: obtaining channel information including multiple channels of expected operation scenarios; and based on the channel information for each of the channels, determining MMSE channel estimation (CE) weights expressed in a form of ACFs and an SNR, and covariance matrices. The method includes clustering the MMSE CE weights into K clusters. A center ACF weight of each of the K clusters represents a codeword. The method includes determining a distance metric based on a cluster distance after a re-clustering. The method includes, in response to a determination that cluster distances before and after the clustering differ from each other by a non-negligibly, iteratively re-clustering the ACF information thereby updating the center ACF weights and cluster distances. The method includes generating the codebook to include an index k of each of the K clusters and the center ACF weight of each of the K clusters.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time.

Abstract: Systems and methods for processing queries are described herein. As an example, a query may comprise an expression. Based on the expression, one or more indexlets may be determined. Using the one or more indexlets, a result of the expression may be determined.

Abstract: After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Abstract: A storage network operates by: encoding a data segment into a set of encoded data slices, wherein a read threshold of encoded data slices of the set of encoded data slices is required to decode the data segment, wherein the read threshold has a value greater than one, and wherein the data segment has an associated security level; selecting a subset of the plurality of storage units based on the security level, wherein the subset includes at least the read threshold of storage units of the plurality of storage units, wherein each of the subset of the plurality of storage units has a connection security approach that corresponds to the security level; and communicating the set of encoded data slices to the subset of the plurality of storage units in accordance with the connection security approach associated with each of the subset of the plurality of storage units.

Abstract: Error correction is proposed, wherein, on the basis of a data word, a syndrome calculation is carried out with a matrix M on the basis of a matrix H of a code, and, if the result of the syndrome calculation reveals that the data word is erroneous, the result of the syndrome calculation is transformed by means of a linear mapping. Next, an error vector is determined on the basis of the result of the linear mapping by means of an efficient error correction algorithm and the erroneous data word is corrected on the basis of the error vector.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: Methods, systems, and devices for wireless communications are described. A transmitting device may allocate a set of information bits into multiple subsets of bits corresponding to channel instances of a channel. The transmitting device may encode a first subset of bits according to a first channel coding scheme for a first channel instance and a second subset of bits according to a second channel coding scheme for a second channel instance. The transmitting device may input encoded subsets of bits to a polarizing transform, which may output a set of encoded polarized bits that are transmitted to a receiving device. Upon reception of the encoded polarized bits, the receiving device may apply a depolarizing transform to obtain multiple subsets of bits corresponding to channel instances of the channel, and may decode each subset of bits according to a respective channel coding scheme.

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

Abstract: An optical module includes: a laser device; a wavelength detector; a modulator; a modulator driver; a coherent mixer; a photoelectric element; a transimpedance amplifier; and a casing. Further, the laser device is arranged such that the laser device outputs a laser light beam in a direction opposite to a side on which the optical output unit is arranged in the casing.

Abstract: A method of detecting an error includes, in part, defining a bit pattern using a first multitude of bits, a second multitude of bits, the bits of an error correction code (ECC), and at least one user selected bit. The method further includes, in part, receiving a first value represented by the first multitude of bits and the at least one user selected bit; receiving a second value represented by the second multitude of bits; receiving a third value represented by the ECC bits. The method further includes, in part, generating a syndrome value from the first, second and third values; and using a subset of the syndrome value bits to detect the error in the first, second or third values. The third value is determined in accordance with the first and second values.

Abstract: An error correction code circuit includes a first error correction code circuit configured to generate correction data and a first correction check bit according to received source data and a source check bit corresponding to the received source data, a second error correction code circuit connected to the first error correction code circuit, and configured to, according to the correction data and at least one of the first correction check bit or the source check bit, determine whether the correction data is wrong and generate a second correction check bit, and a comparison circuit connected between the first error correction code circuit and the second error correction code circuit, and configured to compare the first correction check bit with the second correction check bit and determine whether the first correction check bit is wrong.

Abstract: Provided are systems, methods, and computer program products for protecting AV communications including a sender component and a receiver component from components of an AV system communicating via a shared memory buffer, the sender component configured to send one or more serialized communications to the receiver component, by controlling at least one processor to access a data block storing message data; obtain a first instruction for serializing a communication; obtain a second instruction for computing a CRC checksum; and interleave the CRC checksum with serialized message data to generate a communication within a communication channel, by computing a serialized communication of the message data in the data block based on the first instruction, while concurrently computing the CRC checksum for the message data based on the second instruction.

Abstract: Disclosed are example embodiments of systems and methods for hybrid automatic repeat request (HARQ). An example method includes performing a first HARQ compression to reduce a number of HARQ bits, the HARQ compression comprising one of a unified HARQ compression and a block-wise HARQ compression. Optionally, the example method further includes performing a second HARQ compression to further reduce the number of HARQ bits to a compressed number of HARQ bits. One of the first HARQ compression and the second HARQ compression include the unified HARQ compression and another of the first HARQ compression and the second HARQ compression comprising the block-wise HARQ compression. The example method also includes saving the compressed HARQ data to a DDR storage.

Abstract: A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords from the memory block, identify failed codewords from the decoded codewords, estimate raw bit errors RBERs of the failed codewords, sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and perform a super chip kill SCK operation on one of the failed codewords in the first set to produce a recovered codeword.

Abstract: Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.

Abstract: Provided are a decoding system including a receiving device and a transmitting device. The receiving device comprises a demapper configured to convert received data into a log likelihood ratio (LLR) signal and output the LLR signal, a deparser configured to rearrange the LLR signal by deparsing the LLR signal into orthogonal frequency division multiplex (OFDM) symbols, a codeword loader configured to output the rearranged LLR signal in units of codewords, a decoder controller configured to control a maximum iteration number and the number of decoders to be enabled according to a state of the received data and a low-density parity check (LDPC) decoder configured to repeatedly decode the LLR signal in units of codewords, according to the controlled number of decoders, as many times as the controlled maximum iteration number, wherein the received data comprises real data and a packet extension corresponding to a pre-FEC (forward error correction) padding factor.

Abstract: A base station may perform interleaving of parts of a plurality of transport blocks for a broadcast or multicast transmission across a plurality of time intervals. A size of a transport block of the plurality of transport blocks may be scaled by a scaling factor. The base station may transmit the interleaved parts in the plurality of time intervals.

Abstract: The present disclosure pertains to a radio node, methods and devices for a Radio Access Network. The radio node is adapted for communicating in the Radio Access Network based on a scheduled slot aggregation comprising a plurality of slots, wherein a slot format of at least one slot of the slot aggregation is adapted based on a structure of the slot aggregation.

Abstract: Provided are a method of low-complexity decoding based on soft decision and a computing device for performing the method. The method of low-complexity decoding based on soft decision, performed by a computing device, includes receiving a vector, in which a codeword is modulated, through a channel, determining a decoding result by sequentially applying the received vector to one or more decoding algorithms, and decoding the codeword based on an analysis on the decoding result of a detector corresponding to each of the one or more decoding algorithms.

Abstract: In implementations of systems for estimating terminal event likelihood, a computing device implements a termination system to receive observed data describing values of a treatment metric and indications of a terminal event. Values of the treatment metric are grouped into groups using a mixture model that represents the treatment metric as a mixture of distributions. Parameters of a distribution are estimated for each of the groups and mixing proportions are also estimated for each of the groups. In response to receiving a user input requesting an estimate of a likelihood of the terminal event for a particular value of the treatment metric, the termination system generates an indication of the estimate of the likelihood of the terminal event for the particular value based on a distribution density at the particular value for each of the groups and a probability of including the particular value in each of the groups.

Abstract: Systems and methods include receiving (51) blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding (52) the blocks of data; processing (53) checksum data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining (54) a location of any errors in the payload data based on the processed checksum data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO structure, a ZR structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Abstract: A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

Abstract: A system and method for determining congestion of a communication link transmitting a media stream over the communication link from a sender device to a receiving device.

Abstract: A method for accelerating bit error correction in a receiver in a radio communication network, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method includes receiving a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are non-overlapping: combining the two or more rows in a row group for parallel updating, updating, in parallel, the parity checks of the row group for the received message, and forming a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed.

Abstract: The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data.

Abstract: The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.

Abstract: The disclosure relates to bit-interleaved coded modulation with iterative decoding. In some implementations, a receiver comprises: a first memory including multiple first sub-memories; a decoder configured to perform first operations comprising: calculating, first extrinsic information of multiple code bits associated with multiple received symbols; and a demapper configured to perform second operations comprising: calculating soft decision information of the code bits; calculating, based on the soft decision information and the first extrinsic information, second extrinsic information of the code bits; and writing the second extrinsic information of the code bits into the first memory such that, for each received symbol, each sub-memory of the first sub-memories respectively stores the second extrinsic information associated with a respective one of the code bits corresponding to the received symbol.

Abstract: Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums to enhance the functionality of directional repeaters (wireless devices that relay directional wireless signals). For example, by adding even limited capability to buffer digital samples, repeater functionality may be enhanced to provide better coverage and make more efficient use of time, frequency, and spatial resources.

Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

Abstract: A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

Abstract: A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.

Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure discloses a method for effective retransmission when HARQ is applied to data encoded with a low density parity check (LDCP) code. A data transmission method of the transmitter may include: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgement (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting, in response to the NACK, LDPC-encoded data based on the retransmission related information.

Abstract: Data communications and storage systems require error control techniques and digital modulation schemes to be transferred efficiently and successfully. Constellation shaping based on probabilistic amplitude shaping (PAS) offers an energy-efficient transmission in particular for long shaping blocks. However, longer shaping blocks can cause burst errors and enhancement of bit error rates besides longer latency to complete distribution matcher and dematcher operations. Methods and systems are disclosed that provide a way to resolve the issues by introducing a dual concatenation of pre-shaping and post-shaping error correction codes to mitigate burst errors of shaping. This enables low-complexity, high-performance and parallel architecture with a balanced overhead of dual-concatenation codes for shaping systems.

Abstract: Forward Error Correction decoding is executed by acquiring a stream of real data symbols from a communication medium, the stream of real data symbols being arranged in a real matrix. Virtual data symbols are generated and arranged in a virtual matrix by applying an interleaver map onto the real matrix. Codewords formed by a main matrix formed by the real matrix and the virtual matrix are iteratively decoded, an iteration of the decoding comprising identifying a set of consecutive received rows of the main matrix, accessing a set of pre-determined reference codewords and in response to determining that a given codeword of the set of consecutive received rows does not match any pre-determined reference codewords, executing a GRAND algorithm on the given codeword, the GRAND algorithm generating a substitute codeword for the given codeword. A system comprising a processor and a memory executes the Forward Error Correction decoding.

Abstract: A wireless communication method and apparatus are provided. One example method includes: receiving first PEI by a first terminal device, where the first PEI corresponds to at least one PO, and the first PEI is associated with first information, where the first information is used to indicate that a paging message in the at least one PO is a RAN-initiated paging message or a CN-initiated paging message.

Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: A safety-directed control system comprises at least one safety sensor unit and at least one safety actuator unit, which are connected to one another via a fieldbus, and a programming device. Sensor connections for connecting safety sensors to the fieldbus are provided by the at least one safety sensor unit, the sensor connections being associated with safety lines. The programming device displays the available safety lines to a user via an output interface and receives a user input via an input interface, with the user input associating a selected safety response, which is executable by the safety actuator unit, with at least one selected safety line. The programming device further stores the association between the selected safety line and the selected safety response in the safety actuator unit as a safety configuration.

Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a network device. The network device includes a plurality of ports to facilitate communication over a plurality of planes in a multiplane network. The network device also includes a first interface that presents the plurality of ports as a single plane agnostic port to software, and a second interface that presents each port in the plurality of ports as a separate port to the software.

Abstract: The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

Abstract: Various communication systems may benefit from suitable coding schemes. For example, certain wireless communication systems may benefit from using low density parity check and other reliability mechanisms. A method can include communicating at least one transport block for ultra-reliable low-latency communications between a sending device and a receiving device. The transport block can be coded using a base graph according to one of the following three options: using only low density parity check base graph #2; using only low density parity check base graph #2 and truncated low density parity check base graph #1; or using low density parity check base graph #2, truncated low density parity check base graph #1, and low density parity check base graph #3.