Abstract: Embodiments of the present disclosure provide, among other implementations, sequence determining methods. One example method provides a sequence group, and one sequence group number is corresponding to at least two sequences, where one sequence is used for mapping to consecutive subcarriers, and at least one other sequence is used for mapping to equally-spaced subcarriers. In some embodiments of the present disclosure, as high as possible cross-correlation between a sending signal obtained after equally-spaced mapping is performed on a sequence in a sequence group can be determined, and a sending signal obtained after continuous mapping is performed on another sequence in the group.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: Provided are a file sending method, a file receiving method, and a file transceiving apparatus. The file sending method includes: creating a data sending process; acquiring a file to be sent, corresponding to the data sending process, from a data cache region in a user space; constructing metadata for the data sending process, and recording the metadata in a data reading and sending region in the user space; and sending the file to be sent and the metadata to a network adapter by means of a user-mode network device driver, and sending the file to be sent and the metadata by means of the network adapter.

Abstract: This disclosure relates to a 5G or pre-5G communication system for supporting a higher data transfer rate than a 4G communication system such as LTE. The present invention relates to a method for encoding and decoding a channel in a communication or broadcasting system, comprising the steps of: determining an input bit size (CBS); determining a code rate (R); determining a size (Z) of a block; comparing the determined CBS and code rate with predetermined reference values; determining an LDPC sequence to perform LDPC encoding according to the comparison result; and performing LDPC encoding and decoding on the basis of the LDPC sequence and the block size. Further, the present invention comprises the steps of: determining a code rate (R) indicated by a modulation and coding scheme (MCS) index; determining a transport block size; and determining either a first basic matrix or a second basic matrix as a basic matrix on the basis of the transport block size and the code rate.

Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

Abstract: An embodiment of a semiconductor package apparatus may include technology to process one or more vectors with a sum of squares operation with a layer of a multi-layer neural network, and determine a fixed-point approximation for the sum of squares operation. Other embodiments are disclosed and claimed.

Abstract: Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.

Abstract: According to some embodiments, a method of operation of a transmit node in a wireless communication system comprises performing polar encoding of a set of K information bits to thereby generate a set of polar-encoded information bits. The K information bits are mapped to the first K bit locations in an information sequence SN. The information sequence SN is a ranked sequence of N information bit locations among a plurality of input bits for the polar encoding where N is equivalent to a code length. A size of the information sequence SN is greater than or equal to K. The information sequence SN is optimized for the specific value of the code length (N). The method may further comprise transmitting the set of polar-encoded information bits.

Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

Abstract: Provided is a design method and apparatus for quasi-cyclic low-density parity-check (LDPC) encoding. The method includes: performing LDPC encoding on a K-bit information sequence to be encoded according to a parity check matrix of a quasi-cyclic LDPC code to obtain an N-bit LDPC encoded sequence, where the parity check matrix is determined according to a basic matrix and a lifting size Z, and the basic matrix is determined according to the lifting size Z and a coefficient matrix, where K is a positive integer, N is an integer greater than K, and Z is a positive integer.

Abstract: There is provided a method and device for forwarding a digital signal arranged into portions that each contain a timestamp and an error detection code. Duplicates of the digital signal are received on a first optical path and a second, separate optical path. Corresponding timestamps are identified in the signals and used to synchronize corresponding portions of the signals. The error detection codes in the synchronized portions are used to allow one and only one of the corresponding portions to be selected for forwarding. The selected portions are then forwarded.

Abstract: A network monitoring platform may obtain a measurement of a particular value of a key performance indicator (KPI) and one or more parameters of the particular value of the KPI. The network monitoring platform may determine a prediction of the particular value of the KPI. The network monitoring platform may determine an amount of error in the prediction of the particular value of the KPI, wherein the amount of error in the prediction of the particular value of the KPI is based on a difference between the prediction of the particular value of the KPI and the measurement of the particular value of the KPI. The network monitoring platform may perform, based on the amount of error in the prediction of the particular value of the KPI, one or more actions.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may allocate data associated with a user equipment (UE), of two or more UEs, into at least one of a first part, a second part, or a combination thereof; multiplex the first part of the data associated with the UE with a first part of data associated with one or more other UEs, of the two or more UEs, to form multiplexed data; map the multiplexed data to a first set of layers; and map the second part of the data associated with the UE and a second part of the data associated with the one or more other UEs to a second set of layers. Numerous other aspects are provided.

Abstract: Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

Abstract: Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.

Abstract: Proposed is a method for a terminal to decode a signal. In particular, the method for a terminal to decode a signal comprises: a step for demodulating a first low density parity check (LDPC)-coded signal; and a step for decoding a second signal obtained from the first demodulated signal through a trained neural network. The second signal is obtained by using: an output sequence generated on the basis of the trained neural network; and a log likelihood ratio (LLR) sequence of the first signal.

Abstract: A method for compressing pre-compressed data used in a reconfigurable processor, where the pre-compressed data includes a number of data blocks, obtains a current data block, calculates a current checking code of the current data block, and compares the current checking code with an immediately-previous checking code. A tag of the current data block is marked as a first tag if the current checking code and the immediately-previous checking code are different, and is marked as a second tag if the current checking code and the immediately-previous checking code are the same. Only data blocks whose tags are the first tags are saved. A related device for compressing data, and a method and a device for decompressing data are also provided.

Abstract: A communication device includes a radio transceiver and a collision detection device. The radio transceiver is configured to receive a wireless signal which includes an acknowledgment packet from a wireless communication channel. The acknowledgment packet includes acknowledgment information which corresponds to a plurality of transmitted packets. The collision detection device is coupled to the radio transceiver and configured to receive the acknowledgment packet, determine whether collision has occurred in the wireless communication channel according to the acknowledgment information corresponding to the transmitted packets and accordingly generate a detection result. The collision detection device determines whether collision has occurred according to a distribution of the acknowledgment information having a predetermined acknowledgment status.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Abstract: The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Abstract: Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Abstract: The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

Abstract: Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values.

Abstract: A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Abstract: A method may include receiving, at a wireless station, device capability information associated with a number of user equipment (UE) devices and determining, by the wireless station, uplink and downlink configurations for a number of carriers associated with the wireless station. The method may also include configuring uplink and downlink time slots for each of the carriers based on the determined uplink and downlink configurations and modifying the uplink and downlink configurations for at least some of the carriers over time based on data usage or congestion associated with the at least some of the plurality of carriers.

Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

Abstract: Instructions stored on a computer-readable medium include, in response to receiving a new message for transmission, generating a candidate message by attempting recovery of a previous message from the new message and recovery bits of the previous message. The instructions include, in response to an indicator indicating that the attempted recovery was successful, computing a delta between the new message and the candidate message and generating a delivery message based on the computed delta. The instructions include, in response to the indicator indicating that the attempted recovery was unsuccessful, generating the delivery message based on the new message exclusive of the computed delta. The instructions include calculating new recovery bits from the new message. The instructions include storing the new recovery bits as the recovery bits of the previous message. The instructions include transmitting the delivery message to a destination over a communications channel.

Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.

Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Abstract: A method for securing a blockchain and incentivizing the storage of blockchain data using a publicly verifiable proof of retrievability (PoR) includes receiving a PoR transaction having a PoR proof, determining whether the PoR proof is a verified PoR proof, and based upon determining that the PoR proof is a verified PoR proof, incorporating, by a block creator node, the PoR transaction into a new block of the blockchain.

Abstract: Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.

Abstract: The present disclosure discloses a new coding scheme, which is constructed by superimposing together a pair of basic codes in a twisted manner. A SCL decoding algorithm is proposed for the TPST codes, which may be early terminated by a preset threshold on the empirical divergence functions (EDF) to trade off performance with decoding complexity. The SCL decoding of TPST is based on the efficient list decoding of the basic codes, where the correct candidate codeword in the decoding list is distinguished by employing a typicality-based statistical learning aided decoding algorithm. Lower bounds for the two layers of TPST are derived, which may be used to predict the decoding performance and to show the near-ML performance of the proposed SCL decoding algorithm. The construction of TPST codes may be generalised by allowing different basic codes for the two layers.

Abstract: Methods, systems, and devices are described for low latency communications within a wireless communications system. An eNB and/or a UE may be configured to operate within the wireless communications system and may send triggers to initiate communications using a dedicated resource in a wireless communications network that supports transmissions having a first subframe type and a second subframe type, the first subframe type comprising symbols of a first duration and the second subframe type comprising symbols of a second duration that is shorter than the first duration. Communications may be initiated by transmitting a trigger from the UE or eNB using the dedicated resource, and initiating communications following the trigger. The duration of time between the trigger and initiating communications can be significantly shorter than the time to initiate communications using legacy LTE communications.

Abstract: Disclosed in an embodiment of the present invention are a polar code encoding method and device, the method comprising: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead.

Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

Abstract: A system determines an event location of an event within an indoor environment based on an event sound generated by the event. The system employs time-reversal techniques based on a received event sound to identify the event location as being in the vicinity of one of a plurality of locator devices at locator locations in the environment. The system includes a base array located within the environment that receives an indication that an event has been detected. Upon receiving the event sound, the system generates a time-reversed event sound for each transceiver and transmits via each transceiver the time-reversed event sound for that transceiver. When a locator device receives a time-reversed event sound, the locator device determines whether the event is in the vicinity of that locator location of the locator device and, if so, outputs an indication that the event occurred at that locator location.

Abstract: Described herein is a system and method for coded streaming data to facilitate recovery from failed or slow processor(s). A batch of processing stream data can be partitioned into a plurality of data chunks. Parity chunk(s) for the plurality of data chunks. The plurality of data chunks and the parity chunk(s) can be provided to processors for processing. Processed data of at least some (e.g., one or more) of the plurality of data chunks, and, processed data of parity chunk(s) are received. When it is determined that processed data for a pre-defined quantity of data chunks has not been received by a pre-defined period of time, the processed data for particular data chunk(s) of particular processor(s) from which processed data has not been received are determined based, at least in part, upon the received processed parity chunk(s) and the received processed data chunk(s).

Abstract: A current frame in a sequence is encoded at a first bitrate to generate one or more encoded source frames. One or more previous frames in the sequence are encoded at a second bitrate that is lower than the first bitrate to generate one or more encoded FEC frames. The one or more encoded source frames and the one or more encoded FEC frames are packetized into one or more data packets.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.

Abstract: This application discloses an information processing method and apparatus, a communications device, and a communications system. The method includes: encoding an input sequence by using a low-density parity-check (LDPC) matrix, to obtain a bit sequence D, where a base matrix of the LDPC matrix is represented as a matrix of m rows and n columns, each column corresponds to a group of Z consecutive bits in the bit sequence D, and n and Z are both integers greater than 0; and obtaining an output bit sequence based on a bit sequence V, where the bit sequence V is obtained by permuting two groups of bits corresponding to at least two parity check columns in the bit sequence D.

Abstract: Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller.

Abstract: Methods for data storage on polymers are provided. In various embodiments, an erasure error correcting code is selected. Input data is read from an input file. The erasure error correcting code is applied to the input data to generate a code word. The code word is encoded according to a chemical alphabet. A number of cycles required for synthesis is determined for the code word. The encoded code word is screened according to the number of cycles. The code word is retained where passing the screening.

Abstract: Described herein is a method for improving the reception of a satellite navigation message divided in several pages and transmitted by one or several satellites. A satellite navigation message M of k pages is encoded inn pages, and any k retrieved pages from any satellite enables decoding of the original satellite navigation message M. An implementation of the method uses parallel block encoding for a binary erasure channel with high parity and zero overhead, where symbols at a fixed position of all pages are encoded in parallel into shorter codes. This method achieves full page interchangeability in the message transmission, optimizes message reception and reduces decoding cost.

Abstract: Disclosed is a method for transmitting a broadcast signal. The method comprises formatting input streams with multiple data transmission channels, and the formatting step comprises adding a header indicating a format of a payload of the BBF.