Abstract: A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords in the memory block; determine failed codewords based on one or more parity checks including a chipkill parity; and turbo-decode the failed codewords using at least two decoders in a feedback loop with adders prior to each decoder for scaling soft decode information prior to subsequent decoding of the failed codewords.

Abstract: A data transmission method and apparatus, a terminal, a storage medium, and a system. The data transmission method includes: obtaining audio data and transmission status information, determining a compression factor and a redundancy factor based on the transmission status information, performing time domain data compression processing on the audio data according to the compression factor to obtain compressed data, performing channel coding on the compressed data according to the redundancy factor to obtain a data transmission packet, and transmitting the data transmission packet.

Abstract: A data transmission method implemented by a first item of telecommunication equipment transmitting to a second item of telecommunication equipment. The method includes: encoding input data by using an encoder; puncturing data after encoding; modulating with mapping of the data, after puncturing, on one symbol among M symbols of a constellation having order M, where M=2q,?2, each symbol of the constellation comprising at least two bits having different weights; and transmitting the data, after mapping, to the second item of equipment. The method is such that, for at least one of the M symbols, the puncturing of the data differs according to the weight of the bits in the symbol on which these data are mapped.

Abstract: A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.

Abstract: The disclosure relates to an LDPC decoding method which involves performing iterations until a stop criterion is satisfied. Each iteration involves computing variable messages (?n,m), computing parity check messages (?m,n), and computing a posteriori estimation variables. Computing a parity check message (?m,n) for a parity check node (CNm) involves determining the two smallest values (Mini1, Min2) among the absolute values of the variable messages associated with the parity check node (CNm), comparing a difference between said values with a threshold, determining a correction value according to the result of the comparison, and computing the parity check message according to the correction value.

Abstract: An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the fault.

Abstract: Methods, systems and devices for wireless communication are described. One method includes obtaining a two-dimensional delay-Doppler representation of a received wireless signal that is received over a wireless channel, determining an estimated channel response of the wireless channel from a portion of the delay-Doppler grid corresponding to a channel estimation portion, performing, using the estimated channel response, channel equalization in the delay-Doppler domain, generating, based on the channel equalization, a posteriori probability estimates of data symbols in the received wireless signal, wherein the a posteriori probability estimates are generated based on a priori feedback that is generated using an iterative process and further processing the a posteriori probability estimates of data symbols to recover information bits from the received wireless signal.

Abstract: A low density parity check (LDPC) channel encoding method for use in a wireless communications system includes a communication device encoding an input bit sequence by using a LDPC matrix to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The encoding method can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A decoding device includes a memory and a processor configured to execute inputting a code word encoded by a polar code from an original message; decoding the original message from the code word based on a conditional probability expressed by a symmetric parameterization and having observation information as a condition; and outputting the decoded original message.

Abstract: A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a reference signal for estimation of at least one parameter associated with generation of an adapted low density parity check (LDPC) graph. The UE may transmit an indication of an adapted LDPC graph that is based on at least one adaptation metric associated with the at least one parameter. The UE may receive, based on the adapted LDPC graph, a downlink shared channel communication. Numerous other aspects are described.

Abstract: A memory includes a first check matrix calculation circuit configured to generate a first parity based on a group indicator portion of a check matrix and write data; a memory core including cell regions configured to store therein the write data and the first parity, neighboring ones of the cell regions sharing one or more sub-word line drivers; a first syndrome calculation circuit configured to generate a first syndrome based on the first parity read from the memory core and a first result of calculating the group indicator portion and data read from the memory core; and a failure determination circuit configured to detect, for each row of the memory core, a defective one of the sub-word line drivers based on the first syndrome.

Abstract: Methods and devices are disclosed for transmitting data, including segmenting a group of information bits into a set of information blocks that each include a respective plurality of the information bits; encoding, using low density parity check (LDPC) encoding, each of the information blocks to generate corresponding codewords; transmitting the codewords to a destination station; receiving a feedback message indicating that at least one of the codewords has not been successfully decoded by the destination station; interleaving the information bits of the information block that corresponds to the at least one of the codewords; encoding, using low density parity check (LDPC) encoding, the interleaved information bits to generate an interleaved codeword; and transmitting the interleaved codeword to the destination station.

Abstract: For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.

Abstract: There are provided a channel coding method, a processing device, a communication method and a device. The channel coding method includes: using a generating matrix or a check matrix of QC-LDPC codes to channel-encode or channel-decode a code stream, wherein a code rate of the generating matrix or the check matrix is 1/6, 1/4 or 1/3. The method can be used in a transmission environment with a low signal-noise ratio and a long distance.

Abstract: An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m<n-k.

Abstract: A method includes identifying ACF information by: obtaining channel information including multiple channels of expected operation scenarios; and based on the channel information for each of the channels, determining MMSE channel estimation (CE) weights expressed in a form of ACFs and an SNR, and covariance matrices. The method includes clustering the MMSE CE weights into K clusters. A center ACF weight of each of the K clusters represents a codeword. The method includes determining a distance metric based on a cluster distance after a re-clustering. The method includes, in response to a determination that cluster distances before and after the clustering differ from each other by a non-negligibly, iteratively re-clustering the ACF information thereby updating the center ACF weights and cluster distances. The method includes generating the codebook to include an index k of each of the K clusters and the center ACF weight of each of the K clusters.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to store data according to a second memory storage process instead of a first memory storage process based on an underfill threshold.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time.

Abstract: Systems and methods for processing queries are described herein. As an example, a query may comprise an expression. Based on the expression, one or more indexlets may be determined. Using the one or more indexlets, a result of the expression may be determined.

Abstract: After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Abstract: A storage network operates by: encoding a data segment into a set of encoded data slices, wherein a read threshold of encoded data slices of the set of encoded data slices is required to decode the data segment, wherein the read threshold has a value greater than one, and wherein the data segment has an associated security level; selecting a subset of the plurality of storage units based on the security level, wherein the subset includes at least the read threshold of storage units of the plurality of storage units, wherein each of the subset of the plurality of storage units has a connection security approach that corresponds to the security level; and communicating the set of encoded data slices to the subset of the plurality of storage units in accordance with the connection security approach associated with each of the subset of the plurality of storage units.

Abstract: Error correction is proposed, wherein, on the basis of a data word, a syndrome calculation is carried out with a matrix M on the basis of a matrix H of a code, and, if the result of the syndrome calculation reveals that the data word is erroneous, the result of the syndrome calculation is transformed by means of a linear mapping. Next, an error vector is determined on the basis of the result of the linear mapping by means of an efficient error correction algorithm and the erroneous data word is corrected on the basis of the error vector.

Abstract: Methods, systems, and devices for wireless communications are described. A transmitting device may allocate a set of information bits into multiple subsets of bits corresponding to channel instances of a channel. The transmitting device may encode a first subset of bits according to a first channel coding scheme for a first channel instance and a second subset of bits according to a second channel coding scheme for a second channel instance. The transmitting device may input encoded subsets of bits to a polarizing transform, which may output a set of encoded polarized bits that are transmitted to a receiving device. Upon reception of the encoded polarized bits, the receiving device may apply a depolarizing transform to obtain multiple subsets of bits corresponding to channel instances of the channel, and may decode each subset of bits according to a respective channel coding scheme.

Abstract: This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z?K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Abstract: An optical module includes: a laser device; a wavelength detector; a modulator; a modulator driver; a coherent mixer; a photoelectric element; a transimpedance amplifier; and a casing. Further, the laser device is arranged such that the laser device outputs a laser light beam in a direction opposite to a side on which the optical output unit is arranged in the casing.

Abstract: There is provided a decoding apparatus for decoding a low density parity check (LDPC) code, wherein the decoding apparatus includes a memory a memory configured to store a scheduling table indicating a desired processing order of a plurality of rows included in a parity check matrix and a plurality of columns included in each of the rows of the parity check matrix, and processing circuitry configured to decode the LDPC code based on the scheduling table, the decoding including performing processing on at least one column included in a second scheduled row of the parity check matrix before processing of all columns included in a first scheduled row of the parity check matrix has been completed.

Abstract: An error correction code circuit includes a first error correction code circuit configured to generate correction data and a first correction check bit according to received source data and a source check bit corresponding to the received source data, a second error correction code circuit connected to the first error correction code circuit, and configured to, according to the correction data and at least one of the first correction check bit or the source check bit, determine whether the correction data is wrong and generate a second correction check bit, and a comparison circuit connected between the first error correction code circuit and the second error correction code circuit, and configured to compare the first correction check bit with the second correction check bit and determine whether the first correction check bit is wrong.

Abstract: A method of detecting an error includes, in part, defining a bit pattern using a first multitude of bits, a second multitude of bits, the bits of an error correction code (ECC), and at least one user selected bit. The method further includes, in part, receiving a first value represented by the first multitude of bits and the at least one user selected bit; receiving a second value represented by the second multitude of bits; receiving a third value represented by the ECC bits. The method further includes, in part, generating a syndrome value from the first, second and third values; and using a subset of the syndrome value bits to detect the error in the first, second or third values. The third value is determined in accordance with the first and second values.

Abstract: Provided are systems, methods, and computer program products for protecting AV communications including a sender component and a receiver component from components of an AV system communicating via a shared memory buffer, the sender component configured to send one or more serialized communications to the receiver component, by controlling at least one processor to access a data block storing message data; obtain a first instruction for serializing a communication; obtain a second instruction for computing a CRC checksum; and interleave the CRC checksum with serialized message data to generate a communication within a communication channel, by computing a serialized communication of the message data in the data block based on the first instruction, while concurrently computing the CRC checksum for the message data based on the second instruction.

Abstract: Disclosed are example embodiments of systems and methods for hybrid automatic repeat request (HARQ). An example method includes performing a first HARQ compression to reduce a number of HARQ bits, the HARQ compression comprising one of a unified HARQ compression and a block-wise HARQ compression. Optionally, the example method further includes performing a second HARQ compression to further reduce the number of HARQ bits to a compressed number of HARQ bits. One of the first HARQ compression and the second HARQ compression include the unified HARQ compression and another of the first HARQ compression and the second HARQ compression comprising the block-wise HARQ compression. The example method also includes saving the compressed HARQ data to a DDR storage.

Abstract: A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords from the memory block, identify failed codewords from the decoded codewords, estimate raw bit errors RBERs of the failed codewords, sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and perform a super chip kill SCK operation on one of the failed codewords in the first set to produce a recovered codeword.

Abstract: Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.

Abstract: Provided are a decoding system including a receiving device and a transmitting device. The receiving device comprises a demapper configured to convert received data into a log likelihood ratio (LLR) signal and output the LLR signal, a deparser configured to rearrange the LLR signal by deparsing the LLR signal into orthogonal frequency division multiplex (OFDM) symbols, a codeword loader configured to output the rearranged LLR signal in units of codewords, a decoder controller configured to control a maximum iteration number and the number of decoders to be enabled according to a state of the received data and a low-density parity check (LDPC) decoder configured to repeatedly decode the LLR signal in units of codewords, according to the controlled number of decoders, as many times as the controlled maximum iteration number, wherein the received data comprises real data and a packet extension corresponding to a pre-FEC (forward error correction) padding factor.

Abstract: In implementations of systems for estimating terminal event likelihood, a computing device implements a termination system to receive observed data describing values of a treatment metric and indications of a terminal event. Values of the treatment metric are grouped into groups using a mixture model that represents the treatment metric as a mixture of distributions. Parameters of a distribution are estimated for each of the groups and mixing proportions are also estimated for each of the groups. In response to receiving a user input requesting an estimate of a likelihood of the terminal event for a particular value of the treatment metric, the termination system generates an indication of the estimate of the likelihood of the terminal event for the particular value based on a distribution density at the particular value for each of the groups and a probability of including the particular value in each of the groups.

Abstract: Provided are a method of low-complexity decoding based on soft decision and a computing device for performing the method. The method of low-complexity decoding based on soft decision, performed by a computing device, includes receiving a vector, in which a codeword is modulated, through a channel, determining a decoding result by sequentially applying the received vector to one or more decoding algorithms, and decoding the codeword based on an analysis on the decoding result of a detector corresponding to each of the one or more decoding algorithms.

Abstract: A base station may perform interleaving of parts of a plurality of transport blocks for a broadcast or multicast transmission across a plurality of time intervals. A size of a transport block of the plurality of transport blocks may be scaled by a scaling factor. The base station may transmit the interleaved parts in the plurality of time intervals.

Abstract: The present disclosure pertains to a radio node, methods and devices for a Radio Access Network. The radio node is adapted for communicating in the Radio Access Network based on a scheduled slot aggregation comprising a plurality of slots, wherein a slot format of at least one slot of the slot aggregation is adapted based on a structure of the slot aggregation.

Abstract: Systems and methods include receiving (51) blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding (52) the blocks of data; processing (53) checksum data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining (54) a location of any errors in the payload data based on the processed checksum data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO structure, a ZR structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

Abstract: A system and method for determining congestion of a communication link transmitting a media stream over the communication link from a sender device to a receiving device.

Abstract: A method for accelerating bit error correction in a receiver in a radio communication network, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method includes receiving a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are non-overlapping: combining the two or more rows in a row group for parallel updating, updating, in parallel, the parity checks of the row group for the received message, and forming a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed.

Abstract: The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data.

Abstract: The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.

Abstract: The disclosure relates to bit-interleaved coded modulation with iterative decoding. In some implementations, a receiver comprises: a first memory including multiple first sub-memories; a decoder configured to perform first operations comprising: calculating, first extrinsic information of multiple code bits associated with multiple received symbols; and a demapper configured to perform second operations comprising: calculating soft decision information of the code bits; calculating, based on the soft decision information and the first extrinsic information, second extrinsic information of the code bits; and writing the second extrinsic information of the code bits into the first memory such that, for each received symbol, each sub-memory of the first sub-memories respectively stores the second extrinsic information associated with a respective one of the code bits corresponding to the received symbol.

Abstract: Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

Abstract: Aspects of the present disclosure provide apparatus, methods, processing systems, and computer readable mediums to enhance the functionality of directional repeaters (wireless devices that relay directional wireless signals). For example, by adding even limited capability to buffer digital samples, repeater functionality may be enhanced to provide better coverage and make more efficient use of time, frequency, and spatial resources.