Forward Correction By Block Code Patents (Class 714/752)
  • Patent number: 12035278
    Abstract: A wireless communication method and apparatus are provided. One example method includes: receiving first PEI by a first terminal device, where the first PEI corresponds to at least one PO, and the first PEI is associated with first information, where the first information is used to indicate that a paging message in the at least one PO is a RAN-initiated paging message or a CN-initiated paging message.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: July 9, 2024
    Assignee: Quectel Wireless Solutions Co., Ltd.
    Inventors: Zheng Zhao, Ling Lyu, Zhongzhi Yang
  • Patent number: 12021618
    Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: June 25, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Kyungjoong Kim, Seokki Ahn, Hongsil Jeong, Min Jang
  • Patent number: 12007737
    Abstract: A safety-directed control system comprises at least one safety sensor unit and at least one safety actuator unit, which are connected to one another via a fieldbus, and a programming device. Sensor connections for connecting safety sensors to the fieldbus are provided by the at least one safety sensor unit, the sensor connections being associated with safety lines. The programming device displays the available safety lines to a user via an output interface and receives a user input via an input interface, with the user input associating a selected safety response, which is executable by the safety actuator unit, with at least one selected safety line. The programming device further stores the association between the selected safety line and the selected safety response in the safety actuator unit as a safety configuration.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 11, 2024
    Assignee: Schneider Electric Industries SAS
    Inventors: Jens Bunsendal, Maximilian Lankl, Maximilian Eugen Stahl
  • Patent number: 11996860
    Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eyal En Gad, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Yoav Weinberg
  • Patent number: 11991073
    Abstract: A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a network device. The network device includes a plurality of ports to facilitate communication over a plurality of planes in a multiplane network. The network device also includes a first interface that presents the plurality of ports as a single plane agnostic port to software, and a second interface that presents each port in the plurality of ports as a separate port to the software.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: May 21, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Haggai Eran, Inbal Gal, Guy Rozenberg Kunievsky, Jason Gunthorpe, Liran Liss, Vladimir Koushnir
  • Patent number: 11984910
    Abstract: The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: May 14, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Di Fan, Nedeljko Varnica, Xuanxuan Lu
  • Patent number: 11973593
    Abstract: Various communication systems may benefit from suitable coding schemes. For example, certain wireless communication systems may benefit from using low density parity check and other reliability mechanisms. A method can include communicating at least one transport block for ultra-reliable low-latency communications between a sending device and a receiving device. The transport block can be coded using a base graph according to one of the following three options: using only low density parity check base graph #2; using only low density parity check base graph #2 and truncated low density parity check base graph #1; or using low density parity check base graph #2, truncated low density parity check base graph #1, and low density parity check base graph #3.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 30, 2024
    Assignee: Nokia Technologies Oy
    Inventor: Keeth Saliya Jayasinghe Laddu
  • Patent number: 11966285
    Abstract: A method includes determining, by a computing device of a storage network, a storage inconsistency exists for a set of encoded data slices based on an indicator of a difference list, where the difference list is regarding storage of the set of encoded data slices within a set of storage units of the storage network and where a data segment is error encoded into the set of encoded data slices. The method further includes determining a storage resolution of a plurality of storage resolutions for the storage inconsistency based on the one or more indicators. The method further includes facilitating the storage resolution to resolve the storage inconsistency for the set of encoded data slices.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Andrew D. Baptist, Ravi V. Khadiwala, Jason K. Resch
  • Patent number: 11960355
    Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 16, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Masayoshi Sato, Kenichiro Suzuki
  • Patent number: 11962328
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Patent number: 11954418
    Abstract: Methods and apparatuses for designing quantum circuits include generating a Pauli graph from Pauli strings in a qubit Hamiltonian. Nodes are merged in the Pauli graph, responsive to a determination that some Pauli strings are observables that are jointly measurable by entangled measurement. A quantum circuit based is generated on a merged Pauli graph that results from merging the nodes.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: April 9, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ikko Hamamura, Takashi Imamichi
  • Patent number: 11955988
    Abstract: The embodiments herein provide a system and method for generating a catalog of graphs that acts as a source for creating error correcting codes. A D3 chord index notation is used to describe the graphs. A list of (3, g) Hamiltonian graphs for even girth g is created to satisfy the condition 6?g?16. Each of the lists is infinite and is used for creating LDPC codes of high quality.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 9, 2024
    Inventor: Vivek Sathyanarayana Nittoor
  • Patent number: 11949463
    Abstract: Various embodiments of the present disclosure are directed to accessing a quantum communication channel undetected and/or characterizing this communication channel based upon attempted access. An example method includes accessing a quantum communication channel transmitting one or more qubits. The method includes the introduction of a noise signal to the quantum communication channel and then applying in its absence one or more weak or variable-strength measurements to the quantum communication channel. A strength of at least one measurement of the one or more measurements is based at least in part upon the current noise signal. The method further includes obtaining information associated with the one or more qubits based on the one or more measurements.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: April 2, 2024
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Tali Septon, Elad Mentovich, Moshe B Oron, Yonatan Piasetzky, Yuval Idan, Eliahu Cohen, Avshalom C Elitzur, Taylor Lee Patti
  • Patent number: 11942730
    Abstract: Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: March 26, 2024
    Assignee: Credo Technology Group Limited
    Inventors: Baohua Chen, Haoli Qian, Sheng Huang, Donald Barnetson
  • Patent number: 11936401
    Abstract: A Polar code decoding method and apparatus, a storage medium, and a terminal are provided. The method includes: dividing a Polar code having a length of N into S groups of Polar codes, each group of the S groups of Polar codes being data extracted from the Polar code having the length of N according to a preset rule, and S being an integer power of 2; and performing joint decoding on calculation results of the S groups of Polar codes after performing a logarithm likelihood ratio (LLR) calculation on each group of the S groups of Polar codes.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 19, 2024
    Assignee: SANECHIPS TECHNOLOGY CO., LTD.
    Inventor: Guangming Shi
  • Patent number: 11937210
    Abstract: A wireless communication method and apparatus are provided. One example method includes: receiving first PEI by a first terminal device, where the first PEI corresponds to at least one PO, and the first PEI is associated with first information, where the first information is used to indicate that a paging message in the at least one PO is a RAN-initiated paging message or a CN-initiated paging message.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: March 19, 2024
    Assignee: Quectel Wireless Solutions Co., Ltd.
    Inventors: Zheng Zhao, Ling Lyu, Zhongzhi Yang
  • Patent number: 11929764
    Abstract: For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 12, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Duen-Yih Teng
  • Patent number: 11916667
    Abstract: Examples of check codes, methods of creating check codes, and communication systems utilizing check codes, such as low-density parity-check codes (LDPC codes) are described herein. In some examples, check codes described herein utilize a larger number of check operations than check bits.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: February 27, 2024
    Assignee: Tarana Wireless, Inc.
    Inventor: Kelly Davidson Hawkes
  • Patent number: 11914725
    Abstract: An information handling system includes a virtual interface configured to provide communication between an agent and an embedded controller, wherein the virtual interface is located below a kernel space of the information handling system. The agent may be configured to transmit telemetry data published by the embedded controller to a data repository, wherein the agent is located at a user space of the information handling system. The embedded controller publishes telemetry data to the data repository via the virtual interface through the agent.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Anantha K. Boyapalle, Mario Limonciello, Abeye Teshome
  • Patent number: 11909416
    Abstract: A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: February 20, 2024
    Assignee: AIRBUS DEFENCE AND SPACE SAS
    Inventors: Benjamin Gadat, Lyonel Barthe
  • Patent number: 11909523
    Abstract: An upstream (US) optical line terminal (OLT) for a passive optical network having at least one downstream (DS) optical network unit (ONU). The OLT generates a trigger signal indicating a need to receive at least one US burst having a shortened codeword for a first forward error-correction (FEC) code. Based on the trigger signal, the OLT transmits a DS message instructing the ONU to transmit an US burst having a shortened codeword. The OLT receives and decodes the US burst having the shortened codeword using the first FEC code. During periods of high bit-error rate, the shortened codewords increase the ability of the OLT to decode the US bursts and keep communications from the ONU alive. The OLT can use the decoded US bursts to measure BER and, if appropriate, instruct the ONU to use a different FEC code.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Yannick Lefevre, Amitkumar Mahadevan, Werner Van Hoof
  • Patent number: 11902200
    Abstract: Embodiments of the present disclosure provide, among other implementations, sequence determining methods. One example method provides a sequence group, and one sequence group number is corresponding to at least two sequences, where one sequence is used for mapping to consecutive subcarriers, and at least one other sequence is used for mapping to equally-spaced subcarriers. In some embodiments of the present disclosure, as high as possible cross-correlation between a sending signal obtained after equally-spaced mapping is performed on a sequence in a sequence group can be determined, and a sending signal obtained after continuous mapping is performed on another sequence in the group.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: February 13, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingxin Gong, Hao Sun, Bingyu Qu
  • Patent number: 11902021
    Abstract: A method may include: dividing, by a sending device into k code blocks CBs, a TB into which a cyclic redundancy check bit is loaded, then separately performing channel coding on the k CBs, to obtain a bit sequence Sj, where j=1, 2, . . . , and k, and a set S={S1, S2, . . . , Sk}, and mapping, by the sending device, some or all bit sequences in all elements in S to transmission resources in N basic transmission time units, where some or all bit sequences in the Sj are mapped to transmission resources in Mj basic transmission time units, and a last bit in the Sj mapped to an mth basic transmission time unit in the Mj basic transmission time units and a first bit in the Sj mapped to an (m+1)th basic transmission time unit are contiguous in the Sj.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: February 13, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ruixiang Ma, Yongxia Lyu
  • Patent number: 11882479
    Abstract: A wireless LAN communication device generates an MPDU by attaching a MAC header to transmission data, generates an A-MPDU subframe by attaching an MPDU delimiter to the MPDU, generates an A-MPDU by aggregating a plurality of A-MPDU subframes, and transmits the A-MPDU. The wireless LAN communication device includes: an MPDU duplicating means for determining whether or not transmission data is a redundancy target according to a required quality of the transmission data, determining that an MPDU generated from the transmission data determined to be a redundancy target is a redundant MPDU, and generating a duplicate MPDU by duplicating the redundant MPDU; and an A-MPDU generating means for generating an A-MPDU that includes the redundant MPDU and the duplicate MPDU.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 23, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kenichi Kawamura, Yasushi Takatori, Hiroshi Nakamoto, Tomoyuki Yamada, Keisuke Wakao, Shota Nakayama
  • Patent number: 11876623
    Abstract: The present disclosure discloses an example communication method and apparatus. One example communication method includes receiving, by a first node, decoding information and coded data from a second node, where the coded data is obtained after data of a node group in which the first node is located is encoded, the data of the node group includes data expected to be received by at least two nodes in the node group, and the at least two nodes include the first node. Data expected to be received by the first node is obtained by the first node based on the decoding information and the coded data.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: January 16, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Rongkuan Liu, Pengpeng Dong, Yuanjie Li, Shengyue Dou, Huiying Zhu, Zijie Xu
  • Patent number: 11876534
    Abstract: A method may include, and/or a device may be configured for: receiving, from a transmitting device, a signal corresponding to input bits; performing demodulation based on the signal to determine values corresponding to the input bits; identifying a number of the input bits based on the signal; identifying a base matrix and a lifting size based on the number of the input bits; identifying a parity check matrix based on the base matrix; determining a number of layers based on the lifting size and a number of the values; determining an order of layers for low density parity check (LDPC) decoding based on the number of layers; and performing the LDPC decoding to determine the input bits based on the values, the parity check matrix, and the order of layers.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Min Jang, Yangsoo Kwon, Jeongho Yeo, Hongsil Jeong
  • Patent number: 11868740
    Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: Postech Research and Business Development Foundation
    Inventors: Seokhyeong Kang, Sunmean Kim, Sunghye Park, SungYun Lee
  • Patent number: 11863486
    Abstract: Embodiments of the present disclosure provide, among other implementations, sequence determining methods. One example method provides a sequence group, and one sequence group number is corresponding to at least two sequences, where one sequence is used for mapping to consecutive subcarriers, and at least one other sequence is used for mapping to equally-spaced subcarriers. In some embodiments of the present disclosure, as high as possible cross-correlation between a sending signal obtained after equally-spaced mapping is performed on a sequence in a sequence group can be determined, and a sending signal obtained after continuous mapping is performed on another sequence in the group.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: January 2, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingxin Gong, Hao Sun, Bingyu Qu
  • Patent number: 11855655
    Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 26, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robin Osa Hoel, Anand Kumar G, Dhivya Ravichandran, Aniruddha Periyapatna Nagendra
  • Patent number: 11855778
    Abstract: A network interface for a storage controller includes a processor and a memory that stores an instruction code to be executed by the processor. The processor executes protocol processing for transmitting and receiving packets via a network. The processor reproduces a first packet not received from the network, from a plurality of other received packets included in an error correction packet group same as that of the first packet.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 26, 2023
    Assignee: HITACHI, LTD.
    Inventors: Nobuhiro Yokoi, Hiroka Ihara, Akira Deguchi
  • Patent number: 11855657
    Abstract: The present disclosure relates to a method and an apparatus for decoding data packets in communication network. The method comprises receiving one or more data packets related to each of one or more data types; and decoding the one or more data packets using a parity check matrix associated with the corresponding data type, wherein the parity check matrix comprises a plurality of layers, arranged according to a combination of layers which is determined using a reinforcement model.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tirthankar Mittra, Seungil Yoon, Satya Kumar Vankayala
  • Patent number: 11855776
    Abstract: Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size and allocation of the information bits is based on a base sequence of a given length. During decoding, a decoder assigns different bit types to channels instances by dividing a codeword into a plurality of groups and assigning bit types to channel instances of the plurality of groups using the base sequence.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Shrinivas Kudekar, Joseph Binamira Soriaga, Hari Sankar, Changlong Xu, Chao Wei
  • Patent number: 11856188
    Abstract: Systems and methods relating to presenting media content are disclosed. According to an example method, media data comprising a first media content segment is received. The first media content segment comprises first audio data received via the first user device and first video data received via the first user device, and is encoded according to a first set of encoding parameters. A fault is detected in the first media content segment. Detecting the fault comprises determining a quality value of the first media content segment, and determining whether the quality value exceeds a threshold. A second media content segment is received. The second media content segment comprises second audio data and second video data, and is encoded according to a second set of encoding parameters. The first media content segment is replaced with the second media content segment in the media data.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: December 26, 2023
    Inventors: Roie Cohen, Gideon Keyson, Nadav Keyson, Sebastian Greco
  • Patent number: 11848684
    Abstract: The present disclosure relates to a method, system, and non-transitory computer-readable storage medium for constructing a base matrix of a PBRL LDPC code, comprising: determining at least one candidate sub-matrix of a PBRL LDPC code based on a base matrix of a QR-QC-LDPC code; obtaining at least one count of cycles with at least one preset length for each of the at least one candidate sub-matrix; and determining a first sub-matrix of the base matrix of the PBRL LDPC code based on the at least one count of cycles.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: December 19, 2023
    Assignee: CHONGQING UNIVERSITY
    Inventors: Yong Li, Hao Yan
  • Patent number: 11838125
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure relates to encoding and decoding by using a polar code in a wireless communication system, and an operation method of a transmission-end apparatus includes determining segmentation and the number of segments, based on parameters associated with encoding of information bits, encoding the information bits according to the number of check bits, and transmitting the encoded information bits to a reception-end apparatus.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongsil Jeong, Min Jang
  • Patent number: 11831423
    Abstract: Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a method for wireless communications involves, in a punctured transmission, encoding, bits in a non-legacy preamble portion of a packet to include bandwidth information and resource allocation information, and signaling, in the packet, the bandwidth information and resource allocation information for at least one of a single-user-multiple-input multiple-output (SU-MIMO) technique, a multiple-user-multiple-input multiple-output (MU-MIMO) technique, and an orthogonal frequency-division multiple access (OFDMA) technique.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 28, 2023
    Assignee: NXP USA, Inc.
    Inventors: Rui Cao, Hongyuan Zhang, Liwen Chu
  • Patent number: 11831329
    Abstract: An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: November 28, 2023
    Assignee: Entropic Communications, LLC
    Inventors: Shaw Yuan, Zong Liang Wu, David Barr, Shachar Kons
  • Patent number: 11823760
    Abstract: A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refre
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 21, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Frank Sai-keung Lee
  • Patent number: 11817879
    Abstract: Disclosed are systems, methods, and software for generating spatially-coupled low-density parity-check (SC-LDPC) codes. A method for generating SC-LDPC codes includes generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, and also includes assigning at least one of the generated one or more QC-LDPC codes as one or more template codes. The method further includes copying at least a portion of the one or more template codes to introduce irregularity. The method also includes shifting one or more template codes on a sub-block basis to generate at least one SC-LDPC code. As compared to known LDPC code generation modalities, the disclosed invention provides a simplified technique for implementation in streamlined hardware which has more general applicability across both present, and anticipated, communication systems, including those adapted for use with optical communications, wireless communications, and 5G as well as future 6G.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 14, 2023
    Assignee: Arizona Board of Regents on Behalf of the University of Arizona
    Inventors: Ivan B. Djordjevic, Xiaole Sun
  • Patent number: 11816342
    Abstract: A method includes sending, from an application layer, a chunk size setting to an erasure coding layer. The method further includes receiving, at the application layer, user data. The method further includes aligning, at the application layer, the user data based on the chunk size setting. The method further includes sending the aligned user data to the erasure coding layer. The method further includes partitioning, at the erasure coding layer, the aligned user data into a first data chunk and a second data chunk. The method further includes generating, at the erasure coding layer, a parity chunk based on the first data chunk and the second data chunk. The method further includes sending, from the erasure coding layer, the first data chunk, the second data chunk, and the parity chunk to a storage system.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rekha Pitchumani, Yang Seok Ki
  • Patent number: 11803319
    Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes a serial-to-parallel conversion circuit, a data buffer, a DBI decoder, and a precharge module. The serial-to-parallel conversion circuit performs serial-to-parallel conversion on first DBI data of a DBI port to generate second DBI data for transmission via a DBI signal line and generates input data of the data buffer according to the second DBI data and input data of a DQ port. The data buffer determines, according to the input data of the data buffer, whether to invert the global bus. The DBI decoder receives the second DBI data, decodes the global bus data and writes the decoded global bus data into the memory bank, where the decoding comprises determining whether to invert the global bus data. The precharge module sets an initial state of the global bus to Low.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 31, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11791842
    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat, in the LDPC codeword, at least some bits of the LDPC codeword in the LDPC codeword so that the repeated bits are to be transmitted in the current frame; a puncturer configured to puncture some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits, and generate additional parity bits to be transmitted in a previous frame of the current frame.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung
  • Patent number: 11791839
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11784668
    Abstract: A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 10, 2023
    Assignee: Marvell Asia Pte, Ltd
    Inventors: Damian Alfonso Morero, Mario Alejandro Castrillion, Matias German Schnidrig, Mario R. Hueda
  • Patent number: 11777668
    Abstract: The subject application is related to a method and apparatus for Device-to-Device communication. A method for Device-to-Device communication includes transmitting a signal toward a group of user equipments (UEs); detecting a HARQ feedback signal accumulated by signal (s) from one or more UEs within the group of UEs; and transmitting a signal toward the group of UEs, wherein the UE and the group of UEs are configured to perform groupcast transmission.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 3, 2023
    Assignee: Lenovo (Beijing) Limited
    Inventors: Zhennian Sun, Xiaodong Yu, Haipeng Lei, Lianhai Wu, Jing Han
  • Patent number: 11777524
    Abstract: A method for supporting a rate-compatible non-binary LDPC code, performed by a wireless device, according to the present embodiment, comprises the steps of: acquiring a kernel part comprising a plurality of first check nodes and a plurality of first variable nodes, the kernel part having a predetermined first code rate applied thereto, and the level of each of the plurality of first variable nodes included in the kernel part being set to 2; and generating, on the basis of the kernel part, a protograph having a second code rate, when a change from the first code rate to the second code rate is required.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 3, 2023
    Assignee: LG Electronics Inc.
    Inventors: Kijun Jeon, Sangrim Lee
  • Patent number: 11757471
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: September 12, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-Joong Kim, Hong-sil Jeong, Daniel Ansorregui Lobete, Belkacem Mouhouce
  • Patent number: 11748227
    Abstract: Disclosed herein is a computer implemented method and system for analyzing load responsive behavior of infrastructure components in an electronic environment for proactive management of the infrastructure components. Transaction data on multiple application transactions is collected. Load patterns are identified from the collected transaction data for generating load profiles. Data on infrastructure behavior in response to the application transactions is collected. Infrastructure behavior patterns are identified from the infrastructure behavior data for generating behavior profiles. The generated load profiles and the generated behavior profiles are correlated to create a load responsive behavior model. The created load responsive behavior model predicts behavior of the infrastructure components for different load patterns. A live data stream from current application transactions is analyzed using the load responsive behavior model to determine current load responsive behavior.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: September 5, 2023
    Inventor: Padmanabhan Desikachari
  • Patent number: 11740970
    Abstract: A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Patent number: 11742879
    Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ariel Doubchak, Dikla Shapiro, Evgeny Blaichman, Lital Cohen, Amit Berman