Digital Data Error Correction Patents (Class 714/746)
- Double error correcting with single error correcting code (Class 714/753)
- Error correction during refresh cycle (Class 714/754)
- Double encoding codes (e.g., product, concatenated) (Class 714/755)
- Parallel generation of check bits (Class 714/757)
- Error correcting code with additional error detection code (e.g., cyclic redundancy character, parity) (Class 714/758)
- Look-up table encoding or decoding (Class 714/759)
- Threshold decoding (e.g., majority logic) (Class 714/760)
- Random and burst error correction (Class 714/761)
- Burst error correction (Class 714/762)
- Memory access (Class 714/763)
- Adaptive error-correcting capability (Class 714/774)
- Synchronization (Class 714/775)
- For packet or frame multiplexed data (Class 714/776)
- Hamming code (Class 714/777)
- Nonbinary data (e.g., ternary) (Class 714/778)
- Variable length data (Class 714/779)
- Using symbol reliability information (e.g., soft decision) (Class 714/780)
- Code based on generator polynomial (Class 714/781)
- Random and burst errors (Class 714/787)
- Burst error (Class 714/788)
- Synchronization (Class 714/789)
- Puncturing (Class 714/790)
- Sequential decoder (e.g., Fano or stack algorithm) (Class 714/791)
- Trellis code (Class 714/792)
- Syndrome decodable (e.g., self orthogonal) (Class 714/793)
- Maximum likelihood (Class 714/794)
- Viterbi decoding (Class 714/795)
- Branch metric calculation (Class 714/796)