Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a plurality of storage regions, each including a plurality of memory cells; and a controller configured to provide a plurality of read retry sets, determine an applying order of the plurality of read retry sets based on characteristics of a read error occurred in a first storage region among the plurality of storage regions, and apply at least one of the read retry sets, based on the applying order, for a read retry operation performed on the first storage region.

Abstract: In one embodiment, a method includes configuring a first application probe class and a second application probe class. The first application probe class may be associated with a first Differentiated Services Code Point (DSCP), and the second application probe class may be associated with a second DSCP. The method also includes determining an adaptive Forward Error Correction (FEC) data policy for the first application probe class and the second application probe class, calculating a first loss value associated with the first application probe class for a link between a first network node and a second network node, and comparing the first loss value to a first loss threshold. The method further includes determining whether to activate FEC processing for the first application probe class in response to comparing the first loss value to the first loss threshold.

Abstract: Systems and methods for measuring quantum states of qubits with more than two levels are provided. A method can include, for a plurality of shuffling sequences, applying, by a quantum computer, one or more quantum gates to the one or more qubits to execute a quantum algorithm; applying, by the quantum computer, a shuffling sequence to the one or more qubits; and measuring, using a readout apparatus, the state of the one or more qubits to determine a readout state. The method can further include determining, by a classical computer or the quantum computer, an average occupation for one or more of the quantum states of the one or more qubits using the readout states for each of the shuffling sequences. The readout states can correspond to a state in a subset of the quantum states of the one or more qubits.

Abstract: A temperature-sensing RFID device includes an RFID chip and an antenna electrically coupled thereto. The RFID chip includes a temperature sensor, while the antenna is adapted to receive energy from an RF field and produce a signal. A shielding structure and/or a thermally conductive or absorbent structure may be associated with the RFID chip. The shielding structure is oriented so as to be positioned between at least a portion of the RFID chip and an outside environment and configured to shield the temperature sensor from at least one environmental factor capable of affecting a temperature sensed by the temperature sensor of an article to which the RFID device is secured. The thermally conductive or absorbent structure is oriented so as to be positioned between at least a portion of the RFID chip and the article and configured to enhance thermal coupling between the temperature sensor and the article.

Abstract: This disclosure describes systems, methods, and devices related to enhanced constellation shaping. A device may generate payload bits associated with a frame to be sent to a first station device. The device may generate a first output bits having a first length based on the application of a first mask of one or more masks to the payload bits. The device may generate a second output bits having a second length based on the application of a second mask of the one or more masks. The device may compare the first length of the first output bits to the second length of the second output bits. The device may select the first mask or the second mask based on the comparison. The device may convert the payload bits using the selected mask before passing through a shaping encoder to generate shaped bits. The device may cause to send the frame bits and an indication of the selected mask to the first station device.

Abstract: Provided is a wireless communication terminal that communicates wirelessly. The terminal includes: a transceiver; and a processor. The processor is configured to receive a trigger frame for triggering that a frame for setting a link with a wireless communication terminal, which is an AP, is transmitted through UpLink Multi User (UL MU) transmission through the transmission/reception unit. The processor transmits the frame for setting the link through UL MU transmission based on the trigger frame.

Abstract: Aspects of the disclosure are directed to apparatuses, systems and methods for radar processing. As may be implemented in accordance with one or more aspects herein, an apparatus may include receiver circuitry to receive and sample radar signals reflected from a target, and processing circuitry to carry out the following. Representations of the reflections are transformed into the time-frequency domain where they are oversampled. The oversampled representations of the reflections are inversely transformed to provide resampled reflections. Positional characteristics of the target may then be ascertained by constructing a range response characterizing the target based on the resampled reflections.

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

Abstract: Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a base station may receive, from a repeater having a first interface and a second interface, information associated with one or more capabilities of the repeater, the second interface being different from the first interface. The base station may determine an operation mode for the repeater based at least in part on the information associated with the one or more capabilities of the repeater, and may communicate with the repeater via the first interface or the second interface. In some aspects, a repeater may transmit, to a base station via a first interface, information associated with one or more capabilities of the repeater, and may communicate via the first interface or via a second interface in accordance with an indicated operation mode, the second interface being different from the first interface. Numerous other aspects are provided.

Abstract: A transmission device includes a frame processing unit, a redundant channel processing unit, a transmission and reception unit, and a channel selection unit. The frame processing unit generates division frames, adds error detection signals to the division frames, and outputs the division frames to which the error detection signals are added to a plurality of data channels. The redundant channel processing unit generates, from the division frames, one or more redundant frames including restoration information that enables restoration of the division frames, and outputs the generated redundant frames to a data channel. The transmission and reception unit outputs the division frames and the redundant frames to a transmission line. The channel selection unit allocates the division frames and the redundant frames to allocable transmission and reception units.

Abstract: System and methods are disclosed that comprise receiving at least one signal via a receiver. The at least one signal is extracted for data via a processor coupled to the receiver, wherein the data includes at least one message and a set of parameters related to the message. A signal output is generated using the at least one message and the set of parameters such that the signal output includes a first portion and a second portion. At least one error is identified in the signal output and corrected using the first portion and the second portion. An output is generated that is used to perform at least one task related to the at least one signal.

Abstract: A method and apparatus for code block division are provided. The method may include the following acts. A reference information block length of a code block is determined according to an obtained division related parameter. A maximum information block length is determined according to the reference information block length and a hardware parameter. A Transport Block (TB) having a length greater than the maximum information block length may be divided into two or more code blocks according to the obtained division related parameter, the hardware parameter and the determined maximum information block length. An information length after code block division is less than the determined maximum information block length.

Abstract: The present disclosure provides a method for optimizing a protograph-based LDPC code over an underwater acoustic (UAW) channel. The traditional protograph-based LDPC code over an UAW channel does not consider performance in an error floor region. The method first determines parameters such as a protograph-based LDPC code length, a basic protograph, a target decoding threshold, a threshold adjustment factor, and an ACE check parameter. The protograph is optimized, and the method constructs a parity check matrix by using a UAW channel-based PEG/ACE hybrid algorithm, performs ACE check on the parity check matrix, and calculates a decoding threshold for the matrix passing the check. If the decoding threshold is within a range of an iterative decoding threshold, the parity check matrix is a final optimized matrix. Otherwise, the method continues to optimize the protograph until a parity check matrix passing the check is obtained.

Abstract: Methods, systems, and devices related to wireless communication are described. A method of wireless communication includes determining respective starting points of data, in accordance with Polar encoding, that are associated with each Redundancy Version (RV) of a plurality of RVs and selecting data for transmission in accordance with at least one of the plurality of RVs.

Abstract: Systems and methods for resonance aware performance management of processing devices. In one aspect, a method includes iteratively testing a performance operation for the processing device, wherein each iteration is performed at an iteration voltage level for a power delivery network. The performance operation is applied at different application periods and at the iteration voltage level for the iteration. If no failure condition is met, the iteration voltage is reduced and another iteration is done. Upon a failure occurring at a particular application period, an operational voltage level for the power delivery network that is based on the iteration voltage level for the iteration in which a failure condition was induced is selected, and application of the performance operation at the particular application period is precluded.

Abstract: This application provides a data processing method and a communications device. The data processing method includes: determining, by a first communications device, NCB, based on a size of the circular buffer of the communications device and an information processing capability of a second communications device; and obtaining, by the first communications device, a second encoded bit segment from a first encoded bit segment having a length of NCB. According to the data processing method and the communications device provided in this application, decoding complexity of the communications device can be reduced and communication reliability can be improved.

Abstract: Methods and systems for communicating according to an automatic repeat request, ARQ, scheme, and/or hybrid ARQ, HARQ, scheme are provided. A method may include: performing a first data transmission on a dedicated resource on a first channel; simultaneously to the first data transmission or in a subsequent resource, performing at least one redundancy transmission.

Abstract: A system includes a memory array including a plurality of memory cells; and a processing device coupled to the memory array, the processing device configured to iteratively adjust an active processing level used to process data, wherein, for each iteration, the processing device is configured to: determine a first error rate corresponding to the active processing level, determine a second error rate based on using an offset processing level different than the active processing level, and incrementally adjust the active processing level based on a comparison of the first error rate and the second error rate.

Abstract: Read error mitigation in solid-state memory devices. A solid-state drive (SSD) includes a read error mitigation module that monitors one or more memory regions. In response to detecting uncorrectable read errors, memory regions of the memory device may be identified and preemptively retired. Example approaches include identifying a memory region as being suspect such that upon repeated read failures within the memory region, the memory region is retired. Moreover, memory regions may be compared to peer memory regions to determine when to retire a memory region. The read error mitigation module may trigger a test procedure on a memory region to detect the susceptibility of a memory region to read error failures. By detecting read error failures and retirement of a memory regions, data loss and/or data recovery processes may be limited to improve drive performance and reliability.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A method for encoding a packet in a broadcasting system supporting an Internet Protocol (IP)-based multimedia service is provided. The method includes dividing a data stream into data payloads, generating a Motion Picture Expert Group (MPEG) Media Transport (MMT) packet by adding a first header to each of the data payloads, and generating a source packet by adding an MMT packet header to the MMT packet and performing Forward Error Correction (FEC) encoding on the header-added MMT packet. The MMT packet header includes type information of the MMT packet.

Abstract: A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

Abstract: Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Apparatus and methods for performing a hybrid automatic repeat request, HARQ, process are disclosed. In one embodiment, a method in a wireless device for transmission of redundancy versions in a HARQ process includes determining, by the wireless device, a redundancy version, RV, for transmission by the wireless device, the RV being based at least on a coding rate and performing a transmission according to the determined RV. In one embodiment, a method in a network node is provided including receiving, from a wireless device, a transmission corresponding to a redundancy version, RV, the RV being based at least on a coding rate.

Abstract: Innovations in hash table construction and hash-based block matching for image encoding or video encoding are described. For example, an encoder determines hash values for base-size candidate blocks in a reference picture. The encoder stores, in a hash table, the hash values for the base-size candidate blocks. The encoder encodes a trial-size current block in a current picture. In some cases, the trial-size current block has a block size larger than the base block size. As part of the encoding, the encoder uses hash-based block matching, between base-size current blocks of the trial-size current block and the base-size candidate blocks, to identify a trial-size matching block, if any, in the reference picture. The encoder stores hash values only for the base-size candidate blocks. This can significantly reduce the computational cost and memory cost for hash table construction during encoding, without hurting compression efficiency or the overall speed of encoding.

Abstract: An application apparatus includes a removal controller, a selection controller, and a recovery controller. The removal controller performs, in a case where a removal event occurs, control for storing an operation state of an active application as an original operation state and removing the application from an operation target. The selection controller performs, before causing the removed application to be recovered as the operation target, control for allowing a user to select a specific recovery method from among plural recovery methods including a method for reproducing the original operation state. The recovery controller performs, in accordance with the selected specific recovery method, control for causing an operation of the removed application to be recovered.

Abstract: A gas chromatograph includes a display unit, indicators, and a display control unit. The gas chromatograph is provided with a plurality of units having the same function, and the indicators are each associated with any of the plurality of units. When the error has occurred in any of the plurality of units in the gas chromatograph, processing of the display control unit displays an error notification screen on a display screen of a display unit, and in addition, operates an indicator associated with the unit in which the error has occurred. Therefore, a user can recognize in which of the plurality of units the error has occurred.

Abstract: A control method for a memory device uses an inverting data to label that a data stored in a memory block is in an inverting state or a non-inverting state. According to the inverting data, the number of bits whose data states is changed is lower than a half of total bits in the memory block in writing operation. Therefore, an energy consumption of the memory device can reduce. The control method of the present invention also can utilize the inverting data to label a memory block with a defective bit and to select a spare block to repair the memory block with a defective bit.

Abstract: Methods and apparatus are provided that permit estimation of eigenphase or eigenvalue gaps in which random or pseudo-random unitaries are applied to a selected initial quantum state to produce a random quantum state. A target unitary is then applied to the random quantum state one or more times, or an evolution time is allowed to elapse after application of the target unitary. An inverse of the pseudo-random unitary used to produce the random quantum state is applied, and the resultant state is measured with respect to the initial quantum state. Measured values are used to produce Bayesian updates, and eigenvalue/eigenvector gaps are estimated. In some examples, the disclosed methods are used in amplitude estimate and control map determinations. Eigenvalue gaps for time-dependent Hamiltonians can be evaluated by adiabatic evolution of the Hamiltonian from an initial Hamiltonian to a final Hamiltonian.

Abstract: A vehicle and a method for controlling a vehicle including a current collector transmitting electric power from a current conductor located in a predetermined position in the surface of a road a distance from one side of the road; a first detecting means generating a signal indicative of the position of the current collector relative to a current conductor reference point; where the current collector is displaceable to track the current conductor in response to the signal; and a second detecting means detecting the position of the current collector are provided.

Abstract: A system and method of creating frames comprised of blocks, where each block comprises data symbols corresponding to a higher order quadrature modulation format and support symbols corresponding to a lower order modulation format. One or more of the blocks can further comprise markers comprising distinct symbol patterns. The markers can mark the start of each frame and/or another location in the frame. The support symbols can be in a common location in each block.

Abstract: A gas chromatograph includes a display unit, indicators, and a display control unit. The gas chromatograph is provided with a plurality of units having the same function, and the indicators are each associated with any of the plurality of units. When the error has occurred in any of the plurality of units in the gas chromatograph, processing of the display control unit displays an error notification screen on a display screen of a display unit, and in addition, operates an indicator associated with the unit in which the error has occurred. Therefore, a user can recognize in which of the plurality of units the error has occurred.

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

Abstract: A variable reference based sensing scheme is described. In one example, performance of a memory command to access a crosspoint memory device such as a memory read or memory write command involves a sensing operation. In one example, a memory read operation involves applying a voltage across the memory cell and sensing current through the cell. The current through the memory cell is compared with one of multiple reference currents to determine the state of the memory cell. The reference current is selected based on the voltage applied across the memory for the sensing operation. Different reference currents may be used for different types of operations. For example, different reference currents may be selected for a write sensing operation than for a read sensing operation.

Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

Abstract: A gas chromatograph includes a display unit, indicators, and a display control unit. The gas chromatograph is provided with a plurality of units having the same function, and the indicators are each associated with any of the plurality of units. When the error has occurred in any of the plurality of units in the gas chromatograph, processing of the display control unit displays an error notification screen on a display screen of a display unit, and in addition, operates an indicator associated with the unit in which the error has occurred. Therefore, a user can recognize in which of the plurality of units the error has occurred.

Abstract: Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

Abstract: A method for functionally secure connection identification for data exchange via a telegram between a source data service and a sink data service, wherein whether the time stamp of an incoming telegram is older than the time stamp of a predecessor telegram is determined, upon receipt of the predecessor telegram a monitoring counter being started and whether the currently incoming telegram has arrived within a monitoring time is additionally determined, where a local time stamp of a local time basis is compared with the associated time stamp of the incoming telegram and whether a comparison difference does not exceed a period of time is determined, a telegram arriving only being accepted as valid if the time stamp of the arriving telegram is greater than the time stamp of the telegram most recently accepted as valid, and data is valid if the checks are positive, otherwise a fail-safe reaction is triggered.

Abstract: An operation method of a first communication node comprises: receiving a first frame from a second communication node; obtaining a destination address of the first frame; and transmitting a second frame including an indicator for indicating an occurrence of an error in the first frame to a communication node corresponding to a source address of the first frame, when a port corresponding to the destination address does not exist in a routing table.

Abstract: Disclosed herein are example embodiments of protocols to distill magic states for T-gates. Particular examples have low space overhead and use an asymptotically optimal number of input magic states to achieve a given target error. The space overhead, defined as the ratio between the physical qubits to the number of output magic states, is asymptotically constant, while both the number of input magic states used per output state and the T-gate depth of the circuit scale linearly in the logarithm of the target error. Unlike other distillation protocols, examples of the disclosed protocol achieve this performance without concatenation and the input magic states are injected at various steps in the circuit rather than all at the start of the circuit. Embodiments of the protocol can be modified to distill magic states for other gates at the third level of the Clifford hierarchy, with the same asymptotic performance.

Abstract: To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version.

Abstract: A method of producing a set of coded bits from a set of information bits for transmission between a first node (110, 115) and a second node (110, 115) in a wireless communications system (100), the method comprises generating (904) a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing (908) circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.

Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.

Abstract: Provided herein is a memory controller and a method of operating the same. The memory controller may include a program erase counter configured to count a number of program and erase operations performed on the memory device and then generate a current program/erase count value, an error correction counter configured to count a number of error corrections for correcting error in an operation performed on the memory device and then generate a current error correction count value and a power consumption predictor configured to, predict a future program/erase count value based on the current program/erase count value, predict future power consumption of a storage device including the memory device and the memory controller, the future power consumption corresponding to the predicted program/erase count value and output information about the predicted power consumption to a host.

Abstract: Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Abstract: A memory apparatus of an embodiment includes a nonvolatile semiconductor memory device, an error correction circuit, a memory circuit, a data distribution circuit, and a processing circuit. The error correction circuit performs error detection in data read from the nonvolatile semiconductor memory device on a processing unit size basis and performs error correction on the data in response to its necessity. The memory circuit stores data on the processing unit size basis. The data distribution circuit transfers the data read from the nonvolatile semiconductor memory device to the error detection circuit and the memory circuit on the processing unit size basis. The processing circuit reads the data from the memory circuit and processes the data in response to the error correction circuit detecting an uncorrectable error in the data.