Digital Data Error Correction Patents (Class 714/746)
  • Patent number: 11170302
    Abstract: Methods and apparatus are provided that permit estimation of eigenphase or eigenvalue gaps in which random or pseudo-random unitaries are applied to a selected initial quantum state to produce a random quantum state. A target unitary is then applied to the random quantum state one or more times, or an evolution time is allowed to elapse after application of the target unitary. An inverse of the pseudo-random unitary used to produce the random quantum state is applied, and the resultant state is measured with respect to the initial quantum state. Measured values are used to produce Bayesian updates, and eigenvalue/eigenvector gaps are estimated. In some examples, the disclosed methods are used in amplitude estimate and control map determinations. Eigenvalue gaps for time-dependent Hamiltonians can be evaluated by adiabatic evolution of the Hamiltonian from an initial Hamiltonian to a final Hamiltonian.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 9, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nathan Wiebe, Ilia Zintchenko
  • Patent number: 11169894
    Abstract: A control method for a memory device uses an inverting data to label that a data stored in a memory block is in an inverting state or a non-inverting state. According to the inverting data, the number of bits whose data states is changed is lower than a half of total bits in the memory block in writing operation. Therefore, an energy consumption of the memory device can reduce. The control method of the present invention also can utilize the inverting data to label a memory block with a defective bit and to select a spare block to repair the memory block with a defective bit.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 9, 2021
    Assignee: NS Poles Technology Corp.
    Inventors: Yu Chou Ke, Shih Hong Jheng, Chun Chia Chen
  • Patent number: 11163313
    Abstract: A vehicle and a method for controlling a vehicle including a current collector transmitting electric power from a current conductor located in a predetermined position in the surface of a road a distance from one side of the road; a first detecting means generating a signal indicative of the position of the current collector relative to a current conductor reference point; where the current collector is displaceable to track the current conductor in response to the signal; and a second detecting means detecting the position of the current collector are provided.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 2, 2021
    Assignee: VOLVO TRUCK CORPORATION
    Inventor: Mikaela Öhman
  • Patent number: 11159243
    Abstract: A system and method of creating frames comprised of blocks, where each block comprises data symbols corresponding to a higher order quadrature modulation format and support symbols corresponding to a lower order modulation format. One or more of the blocks can further comprise markers comprising distinct symbol patterns. The markers can mark the start of each frame and/or another location in the frame. The support symbols can be in a common location in each block.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: October 26, 2021
    Assignee: VIASAT, INC.
    Inventors: Murat Arabaci, Fan Mo, Sameep Dave, William H. Miller
  • Patent number: 11150226
    Abstract: A gas chromatograph includes a display unit, indicators, and a display control unit. The gas chromatograph is provided with a plurality of units having the same function, and the indicators are each associated with any of the plurality of units. When the error has occurred in any of the plurality of units in the gas chromatograph, processing of the display control unit displays an error notification screen on a display screen of a display unit, and in addition, operates an indicator associated with the unit in which the error has occurred. Therefore, a user can recognize in which of the plurality of units the error has occurred.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 19, 2021
    Assignee: Shimadzu Corporation
    Inventor: Masashi Yamane
  • Patent number: 11144393
    Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongho Lee, Youngsik Kim, Seungyou Baek, Eunchu Oh, Youngkwang Yoo, Younggeun Lee
  • Patent number: 11139026
    Abstract: A variable reference based sensing scheme is described. In one example, performance of a memory command to access a crosspoint memory device such as a memory read or memory write command involves a sensing operation. In one example, a memory read operation involves applying a voltage across the memory cell and sensing current through the cell. The current through the memory cell is compared with one of multiple reference currents to determine the state of the memory cell. The reference current is selected based on the voltage applied across the memory for the sensing operation. Different reference currents may be used for different types of operations. For example, different reference currents may be selected for a write sensing operation than for a read sensing operation.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventor: Ashraf B. Islam
  • Patent number: 11126498
    Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11119077
    Abstract: A gas chromatograph includes a display unit, indicators, and a display control unit. The gas chromatograph is provided with a plurality of units having the same function, and the indicators are each associated with any of the plurality of units. When the error has occurred in any of the plurality of units in the gas chromatograph, processing of the display control unit displays an error notification screen on a display screen of a display unit, and in addition, operates an indicator associated with the unit in which the error has occurred. Therefore, a user can recognize in which of the plurality of units the error has occurred.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Shimadzu Corporation
    Inventor: Masashi Yamane
  • Patent number: 11073554
    Abstract: Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Asad Azam, Dhinesh A/L Sasidaran, R Selvakumar Raja Gopal
  • Patent number: 11068186
    Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Patent number: 11063868
    Abstract: An operation method of a first communication node comprises: receiving a first frame from a second communication node; obtaining a destination address of the first frame; and transmitting a second frame including an indicator for indicating an occurrence of an error in the first frame to a communication node corresponding to a source address of the first frame, when a port corresponding to the destination address does not exist in a routing table.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 13, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Kang Woon Seo, Dong Ok Kim, Jin Hwa Yun
  • Patent number: 11063680
    Abstract: A method for functionally secure connection identification for data exchange via a telegram between a source data service and a sink data service, wherein whether the time stamp of an incoming telegram is older than the time stamp of a predecessor telegram is determined, upon receipt of the predecessor telegram a monitoring counter being started and whether the currently incoming telegram has arrived within a monitoring time is additionally determined, where a local time stamp of a local time basis is compared with the associated time stamp of the incoming telegram and whether a comparison difference does not exceed a period of time is determined, a telegram arriving only being accepted as valid if the time stamp of the arriving telegram is greater than the time stamp of the telegram most recently accepted as valid, and data is valid if the checks are positive, otherwise a fail-safe reaction is triggered.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventors: Johannes Hubert, Thomas Markus Meyer, Herbert Barthel, Maximilian Walter
  • Patent number: 11038537
    Abstract: Disclosed herein are example embodiments of protocols to distill magic states for T-gates. Particular examples have low space overhead and use an asymptotically optimal number of input magic states to achieve a given target error. The space overhead, defined as the ratio between the physical qubits to the number of output magic states, is asymptotically constant, while both the number of input magic states used per output state and the T-gate depth of the circuit scale linearly in the logarithm of the target error. Unlike other distillation protocols, examples of the disclosed protocol achieve this performance without concatenation and the input magic states are injected at various steps in the circuit rather than all at the start of the circuit. Embodiments of the protocol can be modified to distill magic states for other gates at the third level of the Clifford hierarchy, with the same asymptotic performance.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: June 15, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jeongwan Haah, David Wecker, Matthew Hastings, David Poulin
  • Patent number: 11038625
    Abstract: To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 15, 2021
    Assignees: SHARP KABUSHIKI KAISHA, FG Innovation Company Limited
    Inventors: Ryota Yamada, Tomoki Yoshimura, Hiroki Takahashi
  • Patent number: 11031960
    Abstract: A method of producing a set of coded bits from a set of information bits for transmission between a first node (110, 115) and a second node (110, 115) in a wireless communications system (100), the method comprises generating (904) a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing (908) circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 8, 2021
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Mattias Andersson, Yufei Blankenship, Sara Sandberg
  • Patent number: 11016703
    Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 25, 2021
    Assignee: SONY CORPORATION
    Inventor: Kenichi Nakanishi
  • Patent number: 11010226
    Abstract: Provided herein is a memory controller and a method of operating the same. The memory controller may include a program erase counter configured to count a number of program and erase operations performed on the memory device and then generate a current program/erase count value, an error correction counter configured to count a number of error corrections for correcting error in an operation performed on the memory device and then generate a current error correction count value and a power consumption predictor configured to, predict a future program/erase count value based on the current program/erase count value, predict future power consumption of a storage device including the memory device and the memory controller, the future power consumption corresponding to the predicted program/erase count value and output information about the predicted power consumption to a host.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 18, 2021
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Han
  • Patent number: 10997044
    Abstract: Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 4, 2021
    Assignee: Google LLC
    Inventor: Julian Shaw Kelly
  • Patent number: 10991443
    Abstract: A memory apparatus of an embodiment includes a nonvolatile semiconductor memory device, an error correction circuit, a memory circuit, a data distribution circuit, and a processing circuit. The error correction circuit performs error detection in data read from the nonvolatile semiconductor memory device on a processing unit size basis and performs error correction on the data in response to its necessity. The memory circuit stores data on the processing unit size basis. The data distribution circuit transfers the data read from the nonvolatile semiconductor memory device to the error detection circuit and the memory circuit on the processing unit size basis. The processing circuit reads the data from the memory circuit and processes the data in response to the error correction circuit detecting an uncorrectable error in the data.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiko Iwai, Shinji Maeda, Takaaki Ikeda
  • Patent number: 10956338
    Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 23, 2021
    Assignee: ATI Technologies ULC
    Inventors: Leon King Nok Lai, Qian Ma, Jimshed B. Mirza
  • Patent number: 10951455
    Abstract: Methods (C) for converting a data signal (U). The methods may comprise (i) providing an input symbol stream (IB) of input symbols (Bj), the input symbol stream (IB) being representative for the data signal (U) to be converted and (ii) applying to consecutive disjunct partial input symbol sequences (IBp) of a number of p consecutive input symbols (IBj) covering said input symbol stream (IB), a distribution matching process (DM) to generate and output a final output symbol stream (OB) or a preform thereof, wherein the distribution matching process (DM) may be formed by a preceding shell mapping process (SM) and a succeeding amplitude mapping process (AM), wherein said shell mapping process (SM) may be configured to form and output to said amplitude mapping process (AM) for each of said consecutive partial input symbol sequences (IBp) a sequence (sq) of a number of q shell indices (s), and wherein said amplitude mapping process (AM) may be configured to assign to each shell index (s) a tuple of amplitude values.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: March 16, 2021
    Assignee: Technische Universität München
    Inventors: Georg Böcherer, Patrick Schulte, Fabian Steiner
  • Patent number: 10944992
    Abstract: A method for encoding a packet in a broadcasting system supporting an Internet Protocol (IP)-based multimedia service is provided. The method includes dividing a data stream into data payloads, generating a Motion Picture Expert Group (MPEG) Media Transport (MMT) packet by adding a first header to each of the data payloads, and generating a source packet by adding an MMT packet header to the MMT packet and performing Forward Error Correction (FEC) encoding on the header-added MMT packet. The MMT packet header includes type information of the MMT packet.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hee Hwang, Kyung-Mo Park, Hyun-Koo Yang
  • Patent number: 10923192
    Abstract: A memory system may include: a memory device including a plurality of memory blocks each having a plurality of pages; and a controller suitable for controlling the memory device to perform program operations in the pages, the memory device may check program voltage distributions of the programmed pages, and may check fail bits in the programmed pages, and the controller may confirm a partial program success in the program operations, and may perform a copy operation for first data corresponding to the partial program success, in the memory blocks.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Kyung-Bum Kim
  • Patent number: 10917275
    Abstract: An information transmission method for reducing Peak to Average Power Ratio (PAPR), a transmitting terminal and a receiving terminal are provided, to solve the technical problem that it is difficult for a transmitting terminal to reliably transmit side information to a receiving terminal by using conventional methods for reducing PAPR. The method includes: scrambling an initial data block according to a predetermined scrambling mode to obtain a scrambled target data block; determining a scrambling mode index corresponding to the predetermined scrambling mode according to a predetermined relation between scrambling mode indexes and scrambling modes; generating side information carrying the determined scrambling mode index based on the scrambling mode index; and transmitting the side information and the target data block to a receiving terminal.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 9, 2021
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventor: Xiaodong Shen
  • Patent number: 10917769
    Abstract: One embodiment provides a technique of adjusting a gate voltage to be applied to at least one MOS capacitor and an amount of electric charge to be stored in the MOS capacitor so as to determine sensitivity of a change in the amount of electric charge stored in the MOS capacitor, and exposing the MOS capacitor to an electric field for a predetermined amount of time and then reading an electron inflow or outflow result due to the electric field so as to interpret the intensity and the direction of the electric field, thereby measuring the intensity and the direction of the electric field.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 9, 2021
    Assignee: LG Electronics Inc.
    Inventors: Bonghoe Kim, Yunjung Yi
  • Patent number: 10908995
    Abstract: In general, data is susceptible to errors caused by faults in hardware (i.e. permanent faults), such as faults in the functioning of memory and/or communication channels. To detect errors in data caused by hardware faults, the error correcting code (ECC) was introduced, which essentially provides a sort of redundancy to the data that can be used to validate that the data is free from errors caused by hardware faults. In some cases, the ECC can also be used to correct errors in the data caused by hardware faults. However, the ECC itself is also susceptible to errors, including specifically errors caused by faults in the ECC logic. A method, computer readable medium, and system are thus provided for securing against errors in an ECC.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventor: Nirmal R. Saxena
  • Patent number: 10890600
    Abstract: Fault detection for real-time visual-inertial odometry motion tracking. A fault detection system allows immediate detection of error when the motion of a device cannot be accurately determined. The system includes subdetectors that operate independently and in parallel to a main system on a device to determine if a condition exists which results in a main system error. Each subdetector covers a phase of a six-degrees of freedom (6DOF) estimation. If any of the subdetectors detect an error, a fault is output to the main system to indicate a motion tracking failure.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: January 12, 2021
    Assignee: Google LLC
    Inventors: Mingyang Li, Joel Hesch, Zachary Moratto
  • Patent number: 10893349
    Abstract: One embodiment provides a wireless microphone comprising a microphone body a plurality of antennas positioned at different locations of the microphone body. Each of the plurality of antennas is configured to wirelessly transmit data. The wireless microphone further comprises a sensor configured to detect an object within proximity of an antenna of the plurality of antennas that obstructs the antenna, and a controller configured to switch antenna operation of the wireless microphone from the antenna to another antenna of the plurality of antennas in response to the object detected.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 12, 2021
    Assignee: Audio-Technica U.S., Inc.
    Inventors: Robert T. Green, III, Brian K. Fair, Jacquelynn A. Green
  • Patent number: 10885343
    Abstract: Repairing missing frames in a video includes obtaining video data from an image capture system, applying a first neural network model to the video data to detect that one or more frames are missing, where the first neural network model has been trained to detect missing frames based on training data in which an artificial gap has been introduced. In response to detecting that the one or more frames are missing, a second model is applied to the video data to generate one or more replacement frames. The one or more replacement frames are based on at least a first frame prior to the detected dropped one or more frames, and a second frame after the detected dropped one or more frames. Modified video data is generated using the plurality of frames and the replacement frames.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Kevin Harkness
  • Patent number: 10872021
    Abstract: In a general aspect, quantum computing system performance is tested. Systems and methods for testing hardware in a quantum computing system are described. The methods may include certification/decertification of data produced by the quantum computing system, detection of faults, correction of errors and/or recalibration/replacement of the quantum computing system or a quantum computing subsystem.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 22, 2020
    Assignee: Rigetti & Co, Inc.
    Inventors: Nikolas Anton Tezak, Matthew J. Reagor, Christopher Butler Osborn, Alexa Nitzan Staley
  • Patent number: 10817196
    Abstract: A method for generating a data directory can include allocating a first page for storing a first segment of a log recording changes applied to data subsequent to a checkpoint. When the first page reaches maximum capacity, a second page can be allocated for storing a second segment of the log. A third page can be allocated for storing a first page list that includes a first page reference to the second data page. A fourth page serving as a restart page can be updated. The fourth page can store a second page list of data pages storing the data directory. The fourth page can be updated to add, to the second page list, a second page reference to the data page. Crash recovery at the computing node can be performed based on the data directory. Related systems and articles of manufacture are also provided.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 27, 2020
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10804952
    Abstract: Systems and methods for improving isolation between a cosite transmitter-receiver system. The transmitter may send a first plurality of transmit signals from multiple transmit ports. The first plurality of transmit signals may be related to one another by a first set of complex weights. The receiver may detect channel-impaired versions of the first plurality of transmit signals at one or more receive ports. The receiver may analyze channel-impaired versions of the first plurality of transmit signals to estimate channel state information. The transmitter may use the channel state information to determine a second set of complex weights which will reduce the power received at one or more ports of the receiver when applied to a second plurality of transmit signals. The second set of complex weights may vary with frequency.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: October 13, 2020
    Assignee: UNIVERSITY OF NOTRE DAME DU LAC
    Inventors: Thomas G. Pratt, Robert Daniel Kossler
  • Patent number: 10795785
    Abstract: A failover method, apparatus and system to implement fast failover between a primary processor and a secondary processor, where the method includes receiving, by a first device, transaction content of a transaction and transaction status data of the transaction, the transaction status data being used to resume the transaction when the transaction is interrupted by a failure of a second device, and continuing to process, by the first device, the transaction according to the transaction content and the transaction status data when detecting that the second device fails.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 6, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Junjie Wang, Ruiling Wang, Yan Ye
  • Patent number: 10790885
    Abstract: When a base station has reason to increase the extent of MU-MIMO service that it can provide or in other contexts, the base station could select at least one of the base station's served UEs to have its MIMO rank reduced, with the selecting being based at least on a determination that the selected UE has had a threshold high rate of data retransmissions such as a threshold high rate of HARQ retransmissions for instance.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Sprint Spectrum L.P.
    Inventors: Sathyanarayanan Raghunathan, Muthukumaraswamy Sekar, Maheswaran Vijayakumar, Suresh Majjara
  • Patent number: 10790858
    Abstract: Provided is a method of transmitting and receiving data by a user equipment (UE), the method including receiving, by the UE, a first data stream including at least one of transmission data and a first error correction code regarding the transmission data, obtaining a second error correction code based on the transmission data obtained from the received first data stream, and transmitting a second data stream including at least one of recovered transmission data and the obtained second error correction code.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mun-hwan Choi, Hyeon-mok Ko, Kill-yeon Kim
  • Patent number: 10790854
    Abstract: A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2r).
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 29, 2020
    Assignee: NandEXT S.R.L.
    Inventors: Emanuele Viterbo, Viduranga Wijekoon
  • Patent number: 10771202
    Abstract: A terminal apparatus includes a coding unit configured to divide a transport block into one or more code blocks and generate coded bit(s) by coding the one or more code blocks; and a transmitter configured to transmit the coded bit(s) by using a channel, wherein multiplex bit(s) are given based on at least coupling of the coded bit(s) generated by coding of the one or more code blocks, the coding unit maps the multiplex bit(s) to a matrix in a first-axis prioritized manner and reads the multiplex bit(s) from the matrix in the first-axis prioritized manner or in a second-axis prioritized manner, and whether the first axis or the second axis is prioritized in a case that the multiplex bit(s) are read from the matrix is given based on at least whether a signal waveform applied to a prescribed channel is an OFDM.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: September 8, 2020
    Assignees: Sharp Kabushiki Kaisha, FG Innovation Company Limited
    Inventors: Tomoki Yoshimura, Shoichi Suzuki, Tatsushi Aiba, Liqing Liu, Wataru Ouchi, Takashi Hayashi, Kimihiko Imamura
  • Patent number: 10771196
    Abstract: Techniques are described for wireless communication. One method includes receiving, at a user equipment (UE), a transport block (TB) that includes a plurality of code block groups (CBGs); determining CBG failure information identifying a set of one or more CBGs in the TB that failed to decode at the UE; determining a compressed representation of the CBG failure information; and transmitting, in response to receiving the TB, hybrid automatic repeat request (HARQ) information including the compressed representation of the CBG failure information. The compressed representation of the CBG failure information includes fewer bits of information than the CBG failure information.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Jiang, Seyedkianoush Hosseini, Jing Sun
  • Patent number: 10741250
    Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chi-Yuan Chin
  • Patent number: 10740506
    Abstract: This application discloses a computing system configured to identify a channel in an electronic device is configured to transmit signals encoding data with more than two value levels in response to a correlated test input. The computing system can determine probabilities of value level changes in the transmitted signals based on an encoding for the correlated test input, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the determined probabilities of value level changes in the transmitted signals, which can predict a signal integrity of the channel configured to transmit the signals based, at least in part, on the determined probabilities of value level changes in the transmitted signals.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 11, 2020
    Assignee: Mentor Graphics Corporation
    Inventor: Vladimir B. Dmitriev-Zdorov
  • Patent number: 10733347
    Abstract: This application discloses a computing system configured to identify that a test input for a channel in an electronic device conforms to protocol having a correlated bit pattern. The computing system can determine transition probabilities for bits in the test input based on the protocol having the correlated bit pattern, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the transition probabilities for bits in the test input, which can predict a signal integrity of the channel. The computing system can generate an eye diagram or a develop a bit error rate corresponding to the signal integrity of the channel.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 4, 2020
    Assignee: Mentor Graphics Corporation
    Inventor: Vladimir B. Dmitriev-Zdorov
  • Patent number: 10735566
    Abstract: Certain aspects of the present disclosure relate to jumbo MSDU delivery. Certain aspects of the present disclosure provide an apparatus for wireless communications. The apparatus includes at least one processing system configured to split a first media access control (MAC) service data unit (MSDU) into a first plurality of MAC protocol data units (MPDUs), each having a unique MPDU sequence number and a separate MSDU sequence number associated with the first MSDU, and a first interface configured to output the first plurality of MPDUs for transmission to a recipient.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Solomon Trainin, Alecsander Petru Eitan
  • Patent number: 10698776
    Abstract: Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Timothy Mowry Hollis
  • Patent number: 10698065
    Abstract: An exemplary system, method and computer-accessible medium for removing noise and Gibbs ringing from a magnetic resonance (“MR”) image(s), can be provided, which can include, for example, receiving information related to the MR image(s), receiving information related to the MR image(s), and removing the Gibbs ringing from the information by extrapolating data in a k-space from the MR image(s) beyond an edge(s) of a measured portion of the k-space. The data can be extrapolated by formatting the data as a regularized minimization problem(s). A first weighted term of the regularized minimization problem(s) can preserve a fidelity of the extrapolated data, and a second weighted term of the regularized minimization problem(s) can be a penalty term that can be based a norm(s) of the MR image(s), which can be presumed to be sparse.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: June 30, 2020
    Assignees: New York University, University of Antwerp
    Inventors: Dmitry Novikov, Jelle Veraart, Els Fieremans
  • Patent number: 10693676
    Abstract: A relay device may include a plurality of communication circuits and a state control portion. The relay device may relay the data among a plurality of buses, each of which connecting one or more nodes. The plurality of communication circuits may perform transmission and reception of the data, and transition among a plurality of states including a transmission enabled state and a transmission disabled state. The plurality of communication circuits may be connected to the plurality of buses in one to one manner. The state control portion may cause a specific communication circuit to transition from the transmission enabled state to the transmission disabled state when a relay transition time has elapsed from an occurrence of predetermined event. The specific communication circuit may represent at least one of the plurality of communication circuits to which at least one of the plurality of buses connecting the specific node is connected.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 23, 2020
    Assignee: DENSO CORPORATION
    Inventors: Hiroto Tanaka, Mitsutoshi Kato, Katsuhiko Furuta
  • Patent number: 10673464
    Abstract: An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: Xilinx, Inc.
    Inventors: Kumar Rahul, Santosh Yachareni
  • Patent number: 10664338
    Abstract: Methods, systems and computer program products for root cause analysis using provenance data are provided herein. A computer-implemented method comprises computing a plurality of provenance paths for at least one of a plurality of data elements in a curation flow and a plurality of groups of data elements in the curation flow, analyzing the computed provenance paths to determine one or more errors in the curation flow, and outputting the one or more errors in the curation flow to at least one user. The analyzing comprises at least one of identifying which of the computed provenance paths are partial provenance paths, and identifying one or more output records associated with the curation flow, wherein the one or more output records comprise incorrectly curated data, and identifying the computed provenance paths that respectively correspond to the one or more output records comprising the incorrectly curated data.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hima P. Karanan, Manish Kesarwani, Salil Joshi, Mohit Jain, Sameep Mehta
  • Patent number: 10652190
    Abstract: A method of determining locations for social media postings may include: retrieving, by communicating with at least one application programming interface (API) of a social media system over one or more first communication networks, at least one social media posting; determining at least one location mention in the at least one social media posting; determining at least one location based on the at least one location mention; determining a primary location from the at least one location; storing, in at least one database on a non-transitory machine-readable storage medium, at least one set of geo-coordinates for the primary location in at least one posting object for the at least one social media posting; and outputting, by communicating with a user system over one or more second communication networks, the at least one social media posting with the stored at least one set of geo-coordinates for display on the user system.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 12, 2020
    Assignee: THOMSON REUTERS ENTERPRISE CENTRE GMBH
    Inventors: Armineh Nourbakhsh, Sameena Shah
  • Patent number: 10623020
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 14, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur