Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Abstract: There is provided a recording apparatus, a recording method, a reproduction apparatus, a reproduction method, a recording medium, an encoding apparatus, and a decoding apparatus which enable recording or reproduction to be easily implemented at high line density. User data is encoded into a multilevel edge code, and a multilevel code whose value changes in accordance with the multilevel edge code is recorded.

Abstract: Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable

Abstract: Embodiments of the present invention provide an information sending method and apparatus and an information receiving method and apparatus. The sending method includes: determining a length of a cyclic redundancy check CRC code based on a length of first information, where the first information is control information, and if the length of the first information is less than or equal to a first threshold, and greater than a second threshold, it is determined that the length of the CRC code is a first length; generating the CRC code based on a generator polynomial corresponding to the length of the CRC code and the first information; generating second information; and sending the second information. The present invention improves reliability of information transmission.

Abstract: Provided is a method of scheduling a parity check matrix, the method performed by a low-density parity-check (LDPC) decoder, the method including checking at least one non-zero elemental variable node in the parity check matrix, identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node, extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement, and identifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node.

Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.

Abstract: A wireless communication transmitter (200) configured to segment a transport block into C segments, encode each segment into a set of encoded bits, determine, for ? encoded segments, a subset of size M0? of encoded bits for each encoded segment and for C?? encoded segments, a subset of size M1? of encoded bits for each encoded segment, wherein the subset sizes M0? and M1? differ at most by P bits, where P is a product of a modulation order and a number of transmission layers over which the transport block is transmitted. The selected subsets of encoded bits are concatenated and grouped to form modulation symbols of the modulation order.

Abstract: According to one embodiment, a data decoding control apparatus includes a reading controller and a decoding controller. The reading controller reads the encoded data of a symbol unit bit by bit from a storage medium. The decoding controller computes a log-likelihood ratio (LLR) value of the symbol unit for estimate decoding calculation relative to the encoded data based on the number of bit inversion in a symbol of the encoded data and a correction factor.

Abstract: An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute dc output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.

Abstract: The invention relates to a device and a method for storing binary data in a storage device, in which the binary data is transformed to and stored as ternary data. The storage device uses memory cells capable of storing three states. The device and method furthermore are configured to identify and correct falsified ternary data when reading and outputting the data from storage device.

Abstract: A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.

Abstract: Systems and methods are provided for decoding a vector from a communications channel using a non-binary decoder. The communications channel may correspond to a wired or wireless channel. A message passing process computes R messages corresponding to a variable node of the non-binary decoder. Decoder extrinsic information is formed for the variable node by combining the R messages. The decoder extrinsic information is provided to a soft-detector.

Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse.

Abstract: Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts. A determiner determines indicia associated with the communicated data. And, responsive thereto, the data is decoded, selectably utilizing fewer than all of the data bursts that form the encoded data block.

Abstract: A method and apparatus providing improved set membership determination and group membership identification of candidate data elements using a single Bloom filter programmed to provide a plurality of non-zero f-bit binary vectors, where each of the f-bit binary vectors is associated with a respective group. The Bloom filter is programmed using one or more (but not all) of a plurality of hash filter sets.

Abstract: A method and apparatus for processing symbols of a block code is presented. A sequence of symbols is received, e.g., from an inter-symbol interference (ISI) channel. A soft value is determined for each symbol using a binary trellis.

Abstract: A technique for iterative decoding between turbo and Reed Solomon (RS) decoders for improving bit error rate (BER) and packet error rate (PER) in a receiver in a wireless communication system comprises receiving data samples comprising turbo encoded packets and RS code words at the receiver; decoding turbo encoded packets of the received data samples using a turbo decoder; decoding RS code words of the received data samples using a RS decoder; feeding the RS decoded data to turbo decoder to perform a plurality of iterations; and correcting data errors present in the received data samples.

Abstract: A system and method for channel equalization using a Viterbi algorithm. Information from an output of a matched filter and channel parameters from a channel estimation circuit are correlated and passed on to a reconfigurable data path. The reconfigurable data path includes a reconfigurable branch metric calculation block. The reconfigurable data path also includes a reconfigurable add-compare-select and path metric calculation block. The reconfigurable data path is controlled using a programmable finite state machine. The programmable finite state machine executes a plurality of context-related instructions associated with the Viterbi algorithm. The system and method for channel equalization supports multiple standards using Viterbi algorithms.

Abstract: A method of and apparatus to data encode and decode for improving the reliability of data that is compatible with a conventional error correction code (ECC) block format, a storage medium, a system to drive the storage medium, and a method of generating an extra parity ECC block, the data encoding method including generating N number of ECC blocks with respect to user data and generating at least one extra parity ECC block for the generated N number of ECC blocks.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells.

Abstract: A method and apparatus for processing a received digital signal that has been corrupted by a channel is disclosed. The method includes storing the received digital signal and receiving a partially corrected sequence of symbols that includes an output of a preliminary denoising system operating on the received digital signal. Information specifying a signal degradation function that measures the signal degradation that occurs if a symbol having the value I is replaced by a symbol having the value J is utilized to generate a processed digital signal by replacing each symbol having a value I in a context of that symbol in the received digital signal with a symbol having a value J if replacement reduces a measure of overall signal degradation in the processed digital signal relative to the received digital signal as measured by the degradation function and the partially corrected sequence of symbols.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: The invention relates to error-correcting coding and correct restart of decoding after errors of sequences that are coded by convolutional coders or LFSR based descramblers. The signals can be binary or multi-valued signals. Methods and apparatus to convolutional encode and decode sequences of binary and n-valued symbols are disclosed. The invention further discloses methods and apparatus to identify symbols in error in sequences coded according to methods of the invention. Methods and apparatus to correct these errors are provided. Methods and apparatus to repair errors in a Trellis of received sequences are also provided. Methods and apparatus for n-valued Recursive Systematic Convolutional coders and decoders are disclosed.

Abstract: Iterative decoding channel architectures employing coded modulation are provided. The coded modulation is realized via set partitioning for Partial Response (PR) channels along with multi-level coding. Associated error correction encoding and decoding methods, with additional compatibility considerations for channel constrained coding, are also provided.

Abstract: A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n?2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space.

Abstract: An order-ensemble searching unit classifies a distribution of reception signals at each bit position of a modulation symbol, and searches an order ensemble of a parity check matrix that minimizes an SNR threshold value. A code generating unit generates a parity check matrix and a generation matrix, based on the order ensemble obtained as a search result.

Abstract: A virtual display driver that can be dynamically loaded and unloaded for remote control of a host computing system. The host computing system includes an original display driver that updates an output display of the computing system based on display commands. A remote control executive executes in kernel-mode within an operating environment provided by the computing system and dynamically loads and unloads the virtual display driver as requested by a user. The remote control executive inserts hooks within the functions provided by the original display driver to trap the display commands received by the original display driver and direct the commands to the virtual display driver for communication to a remote client computer.

Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.

Abstract: A symbol sequence in a received DS-CDMA signal is decoded in an efficient manner in order to reduce the processing needs in a receiver when, e.g., processing acquisition indicators (AI) in a UMTS system. The decoding comprises iterative calculation of a hard-decision vector, using a decision threshold having a value based on the probability of each ternary alphabet element of each symbol in the hard-decision vector.

Abstract: A method and apparatus can detect errors within an incorrect media access control address and can prevent an Ethernet device from using the incorrect media access control address while it is fully operating. The method and apparatus can also correct some types of errors within the media access control address so that the Ethernet device may operate using a correct media access control address.

Abstract: Disclosed is an apparatus for encoding k consecutive inputs indicating a TFCI (Transport Format Combination Indicator) of each of successively transmitted frames into a sequence of m symbols in an NB-TDD (Narrowband-Time Division Duplex) mobile communication system. An encoder encodes the k input bits into a sequence of at least 2n symbols where 2n>m, using an extended Reed-Muller code from a Kasami sequence. A puncturer performs puncturing on the sequence of 2n symbols from the encoder so as to output a sequence of m symbols.

Abstract: A low-density parity-check (LDPC) decoder (304) has a memory (308), and a processor (306). The processor is programmed to initialize (202) the LDPC decoder, calculate (204) a probability for each check node, calculate (206) a probability for each bit node, calculate soft decisions, update the bit nodes according to the calculated soft decisions, calculate (208) values from the calculated soft decisions, perform (210) a parity check on the calculated values, update (218) log-likelihood ratios (LLRs) if a bit error is detected in the calculated values, update the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps.

Abstract: Information signals such as grayscale images or audio signals are represented as a sequence of PCM signal samples. To embed auxiliary data in the least significant bits of the signal, the samples are slightly distorted. There is a so-termed “rate-distortion function” (20) which gives the largest embedding rate R given a certain distortion level D. It appears that the efficiency of prior art embedding schemes such as LSB replacement (21,22) can be improved. The invention discloses such embedding schemes (23,24). According to the invention, the signal is divided into groups of L (L>1) signal samples (x). For each group of signal samples, a vector of least significant portions (x mod n) of the signal samples is created. For n=2, the vector comprises the least significant bit of each signal sample. The syndrome of said vector (as defined in the field of error detection and correction) represents the embedded data.

Abstract: A method of coded modulation of digital data is described, the digital data being divided into parallel signal streams, and the useful bits then being channel coded at different code rates according to their error susceptibility. The useful bits channel coded differently in this way are then scrambled separately in time. The different code rates used and the respective number per transmission frame of the useful bits channel coded at different code rates are signaled to the receivers, so that the receiver is able to perform the descrambling and channel decoding.

Abstract: A method and apparatus for processing symbols of a block code is presented. A sequence of symbols is received, e.g., from an inter-symbol interference (ISI) channel. A soft value is determined for each symbol using a binary trellis.

Abstract: Disclosed is an apparatus for encoding k consecutive inputs indicating a TFCI (Transport Format Combination Indicator) of each of successively transmitted frames into a sequence of m symbols in an NB-TDD (Narrowband-Time Division Duplex) mobile communication system. An encoder encodes the k input bits into a sequence of at least 2n symbols where 2n>m, using an extended Reed-Muller code from a Kasami sequence. A puncturer performs puncturing on the sequence of 2n symbols from the encoder so as to output a sequence of m symbols.

Abstract: A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

Abstract: A hashing system produces hash values by manipulating n-bit sequences in accordance with a selected distance d error correction code (“ECC”) over an associated Galois Field. The current system produces a hash value for a given n-bit sequence by treating the sequence as either a corrupted n-bit ECC codeword or as “n” information bits of an (n+r)-bit ECC codeword. The hashing system may decode the n bits as a corrupted codeword of an (n, k, d) perfect ECC to produce an n-bit error-free codeword, and then use as the hash value the information bits of the error-free codeword. Alternatively, the hashing system may treat the n-bit sequence as a corrupted code word of a cyclic distance d ECC, and map the codeword to an (n?k)-bit “error pattern” that the system then uses as the hash value. The hashing system may instead treat the n-bit sequence as n “information” bits and encode the bits in accordance with an (n+r, n, d) ECC, to produce an r-bit hash value that consists of the associated redundancy bits.

Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.

Abstract: A method of encoding data includes representing the data as number(s) in a first base. The method further includes converting the number(s) into a number(s) in a second base. The resultant number in the second base can be viewed as data suitable for encoding using an ECC algorithm. After being ECC encoded, the data may be further modulation encoded. Modulation encoding may include transforming each symbol to a value that constrains run lengths of a binary value (e.g., zero). A decoding method and system checks a received data block for erroneous symbols, maps each received, encoded symbol to an associated ECC-encoded transform pair. The ECC encoded data may be decoded and corrected using the ECC and the locations of identified erroneous symbols. Finally, the corrected data sequence is converted from the second base back to the first base, from which the original data is retrieved.

Abstract: A method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion.

Abstract: The information transfer method uses: an alphabet Z2t={0, 1, 2, . . . 2t−1}, t≧3, in which additions and multiplications are carried out modulo 2t, and a lifted Hamming code whose generator polynomial is in Z2t. It includes: coding (302) of the information by a sequence of words of the said code, labelling (303), each letter of the alphabet Z2t labelling a letter of an alphabet A, for two adjacent symbols of A, one of the labels is the residue modulo 2t of the other incremented by 1, for each word of the said code, transmission (305) of signals, a physical quantity of which is proportional to the elements of A labelled by each of the symbols of the words of the said code.

Abstract: The invention concerns a method and devices for the detection of errors, in particular transmission errors, in data streams and/or data packets. In order to better detect systematic errors in particular, the error detection function according to the invention is variable. The detection function is varied on the basis of the time and/or the data themselves, for example by assigning an individual variation value to each index (packet index), effectively varying the data themselves. The invention is particularly suitable for application to compressed data streams.

Abstract: A communication device employs a method and apparatus for transmitting and receiving information packets using multiple layers of error detection. A sending communication device constructs an information packet to include user information divided into multiple data blocks, a primary error detection code for each data block, and at least a portion of a secondary protection code. The secondary protection code provides error protection for the entire information packet. The secondary protection code is selected such that it can be incrementally determined by a receiving device as data blocks are received and accepted by the receiving device, regardless of order of reception of the data blocks. Since the secondary protection code is incrementally determined, processor utilization is better regulated and delays associated with sending acknowledgments are minimized.

Abstract: The method for selecting CRC polynomials (or CRC generators) for linear coded systems. In the exemplary embodiment, a communication system utilizes a concatenated code comprising a CRC code and a convolutional code. The CRC generators are selected based on the distance spectrums which have been computed for all possible CRC generators of a given length L. The distance spectrum comprises a listing of the number of paths (or code words) at various weights (or Hamming distance). These paths represent error information sequences I(x) which have diverged from an all-zero transmitted sequence (or the zero state) and have merged back into the zero state. The paths are checked by the CRC generators. If the CRC check passes, indicating that the error information sequence is undetected by the CRC check, the weight of this path is calculated and the distance spectrum for this CRC generator is updated. Otherwise, if the CRC does not check, the path is ignored. The CRC generator with the maximum minimum distance d.sub.