Abstract: An image processing apparatus obtains a degree of degradation for blocks in an encoded image obtained by encoding an input image, decodes the encoded image; and executes image recovery processing on a block in a decoded image obtained by the decoding. The image processing apparatus, switches, depending on the degree of degradation of the blocks in the encoded image, whether or not the image recovery processing using a first neural network is executed on each block in the decoded image.

Abstract: Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

Abstract: The invention relates to concealing information within error correction codes of adaptive rate wireless communication systems. In some embodiments, the invention includes selecting a modulation and coding scheme with a more robust error correction capacity than needed by current channel conditions; encoding a hidden message with a pre-shared key that is known by a covert transmitter and a covert receiver, and after a standard message is encoded by a transmitting station of the wireless communication systems, replacing codeword parity bits of codewords in the encoded standard message with the encoded hidden message at designated locations. Before a receiving station of the wireless communication systems decodes the encoded standard message, a covert receiver extracts the embedded hidden message from the encoded standard message, replaces bit values of the embedded hidden message with zero at the designated locations, and decodes the extracted hidden message with the pre-shared key.

Abstract: The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Abstract: A method and user equipment are provided for generating a channel state information feedback report, which has multiple layers, from channel state information associated with each of the multiple layers including at least one parameter, which is commonly present in the channel state information associated with each of the multiple layers. Each commonly present parameter in each of the multiple layers has a respective value. A set of reference signals transmitted from a network entity are received and observed channel characteristics are organized, based on the received set of reference signals, into the multiple layers of channel state information. From the at least one parameter, which is commonly present in each of the multiple layers, selecting one or more parameters from which a respective index value can be derived for each of the multiple layers.

Abstract: The present technology relates to an error correction circuit. According to the present technology, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device.

Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

Abstract: A method is provided for channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes grouping information bits into a plurality of groups, determining an order of the plurality of groups to be shortened, according to a code rate, determining a length of information bits to be obtained by shortening the plurality of groups, shortening the plurality of groups on a group basis in the determined order, based on the determined length of the information bits, and LDPC-encoding shortened information bits.

Abstract: An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

Abstract: Low latency wireless communication applications require highly dynamic allocation of resources. Providing allocation information on a highly dynamic basis increases the overhead of control signaling for allocation. A technique known as blind PDCCH decoding is used to reduce the control signaling overhead for allocation information. However, blind decoding occasionally may lead to invalid detection of allocation messages which in turn may lead to a number of problems such as wasted bandwidth, more power consumption, reduced throughput, etc. A method and apparatus are disclosed that may detect the invalid allocation messages and discard them which in turn may lead to detection of valid allocation messages for increased data throughput and reduced power consumption and improve the overall performance.

Abstract: Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. Also, the information bits are encoded according to a block coding scheme, where m copies of each bit are included in the information bits, and one or more bits in the m copies of each bit are flipped. The information bits are mapped to a plurality of constellation symbols, and a plurality of orthogonal frequency division multiplexing (OFDM) symbols are generated to include the plurality of constellation symbols. The PHY data unit is generated to include the plurality of OFDM symbols.

Abstract: Access terminals are configured to decrease awake state durations (and conversely increase standby state durations) utilizing a preamble skip operation. According to one example, an access terminal may assign a finger of a receiver to receive a control channel transmission at a time after a beginning of a preamble of the control channel transmission, and before an initial boundary of a slot after a first slot of the control channel transmission, the preamble of the control channel transmission including information corresponding to a data rate of the control channel transmission. The access terminal may further be configured to decode the control channel transmission in accordance with a predicted data rate. Other aspects, embodiments, and features are also included.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. Also, the information bits are encoded according to a block coding scheme, where m copies of each bit are included in the information bits, and one or more bits in the m copies of each bit are flipped. The information bits are mapped to a plurality of constellation symbols, and a plurality of orthogonal frequency division multiplexing (OFDM) symbols are generated to include the plurality of constellation symbols. The PHY data unit is generated to include the plurality of OFDM symbols.

Abstract: The embodiments of the present invention provide a decoding method and a decoding device for a polar code cascaded with CRC. The decoding method includes: performing SC-List decoding on a Polar code according to the number of survival paths L to obtain L survival paths, where L is a positive integer; performing cyclic redundancy check on the L survival paths respectively; and increasing the number of survival paths when all the L survival paths fail to pass the cyclic redundancy check, and acquiring a decoding result of the Polar code according to the increased number of survival paths. In the embodiments of the present invention, the path number of survival paths is adjusted according to a result of the cyclic redundancy check, so as to output paths as much as possible, where the output paths can pass the cyclic redundancy check, thereby improving decoding performance.

Abstract: A transmitting apparatus and method transmits different modulated signals from a plurality of antennas, and employs a configuration that includes a modulation section that obtains a modulated signal by performing signal point mapping of transmit bits using a signal point arrangement that is divided into a plurality of signal point sets on the IQ plane, whereby the minimum distance between signal points within a signal point set is smaller than the minimum signal point distance between signal point sets; and an antenna that transmits a modulated signal obtained by the modulation section. A signal point generating apparatus generates a first and second symbols to be transmitted by first and second antennas, respectively.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are encoded using a forward error correction (FEC) encoder. The information bits are mapped to a constellation symbols. Additionally, either the information bits are encoded according to a block coding scheme, or the constellation symbols are encoded according to the block coding scheme. Orthogonal frequency division multiplexing (OFDM) symbols are generated to include the constellation symbols and the PHY data unit is generated to include the OFDM symbols.

Abstract: Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: A method begins by a processing module identifying a set of encoded data slices that have been created in accordance with a dispersed storage error encoding function having a decode threshold equal to or less than half of a number encoded data slices in the set of encoded data slices. The method continues with the processing module identifying a first sub-set of encoded data slices having a non-current revision level and identifying a second sub-set of encoded data slices having a more-current revision level. When a number of encoded data slices of the second sub-set of encoded data slices is greater than or equal to the decode threshold and when a number of encoded data slices of the first sub-set of encoded data slices is less than the decode threshold, the method continues with the processing module facilitating rebuilding of the first sub-set of encoded data slices.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: Devices and/or methods for managing a buffer containing failed data may utilize side information related to the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors and/or a local host requested status for buffered or unbuffered failed data.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. In some cases, embodiments include a variable length data decoder circuit that is operable to apply a decode algorithm to the encoded input based upon a first selected H-Matrix to yield a first decoded output and apply the decode algorithm to the encoded input based upon a second selected H-Matrix to yield a second decoded output.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein an adaptive check node approximation is performed at the check node processor utilizing the smallest magnitude log-likelihood ratio (LLR) and the second smallest magnitude log-likelihood ratio (LLR) to adapt to the current conditions at the check node.

Abstract: Provided is a wireless communication system employing network coding which can set transmission quality for each destination of packets and improve throughput. The wireless communication system is provided with a wireless relay station apparatus and wireless terminal station apparatuses. The wireless relay station apparatus selects coding rates to be used for a first packet and a second packet in accordance with communication quality required for the first packet and the second packet, generates error correction encoded packets having the same data length from the first packet and the second packet using the selected coding rates, performs network encoding on the error correction encoded first and second packets to generate a network encoded packet, and transmits the generated network encoded packet.

Abstract: Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data.

Abstract: An error detection method of a variable-length coding (VLC) code stream includes at least the following steps: decoding a data frame of the VLC code stream; and determining whether the data frame is erroneous according to length information of the data frame and a bit number of decoded data of the data frame. According to the method, the present invention realizes the objective of performing error detection upon data frames during the decoding process.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: According to one embodiment, a decoder includes a control unit and a decoding unit. The control unit determines a window size applied to a first target frame to be a first value and determines a window size applied to a second target frame different from the first target frame to be a second value different from the first value. The decoding unit carries out windowed decoding of a spatially coupled code on the first target frame with the window size set to the first value and carries out windowed decoding of a spatially coupled code on the second target frame with the window size set to the second value.

Abstract: A data input method of a NAND flash memory includes: determining whether a size of a writing-requested data is less than a reference value; calculating an error correction code (ECC) for the data using a software ECC method when the data size is less than the reference value; and writing the data and the ECC to a data region of the NAND flash memory. A data output method of the NAND flash memory includes: determining whether a size of a reading-requested data is less than a reference value; reading the data and an error correction code (ECC) from the NAND flash memory; calculating an ECC for the read data using a software ECC method when the data size is less than the reference value; and performing an error detection and correction by comparing the calculated ECC and the read ECC.

Abstract: The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 20 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 20-bit length corresponding to columns of the code generation matrix. If “A” is 10, individual basis sequences of the code generation matrix correspond to column-directional sequences of a specific matrix composed of 20 rows and 10 columns. The specific matrix is made from 20 rows of the (32,10) code matrix used for TFCI coding were selected.

Abstract: A method for processing data packets of a data stream, in which the received data packets are processed in real-time by a first unit and only data packets that are received error-free are processed by a second unit, include a data sink initially receiving only the data packets processed by a first unit. Once a second unit and the first unit are processing identical data packets nearly simultaneously, data packets processed by the second unit can be routed to the data sink. Embodiments of the invention can be used advantageously in video coding, for example with a video-on-demand service or image analysis within the framework of a surveillance system.

Abstract: A method for data transmission by telegram via a fieldbus of process automation technology, wherein information is transmitted via the fieldbus in the form of data in at least one telegram, and wherein the information, especially the same information, is transmitted in the at least one telegram in a first data format and in a second data format, wherein the first data format differs from the second data format.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of minimum Hamming distance.

Abstract: A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A?10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: A transmitting apparatus and a transmitting method wherein the systematic bit reception quality can be improved and the throughput performance can be improved. An IR parameter control part (101) controls, based on the number of retransmissions, the ratio of systematic bits to parity bits in mapping them to packets, and controls to map a parity bit to an initially transmitted packet, while mapping a systematic bit to a retransmitted packet. An encoding part (102) generates the systematic bits and parity bits and maps them to the packets in accordance with the IR parameters. A transmission power calculating part (105) calculates, based on reception quality information of the initially transmitted packet fed back from a receiving end, the transmission power of the transmitted packet to which the systematic bit is mapped.

Abstract: An objective of the present invention is to provide a decoder, a perpendicular magnetic recording and reproducing device, a receiving device, and a decoding method that are used for performing decoding resistant to burst errors such as a pole-erase phenomenon, where the burst errors do not have amplitude fluctuation, without the addition of a special code (redundant code) for detecting burst errors. The present invention is a decoder, a perpendicular magnetic recording and reproducing device, a receiving device, and a decoding method that perform a decoding process on an encoded data signal, wherein a parity check is performed on the encoded data signal that is encoded with a low density parity check code to output burst information.

Abstract: The disclosure provides a method that includes receiving a data sector of a plurality of data tiles, wherein each of the plurality of data tiles includes either nuisance data or user data, decoding the received data sector, using an error correction code, to generate a decoded data sector, and determining an error in the decoded data sector. The method further includes identifying, in response to determining the error, at least one data tile from a first plurality of data tiles, such that each of the identified at least one data tiles potentially includes nuisance data, and generating a modified data sector from the received data sector, by correcting at least one of the at least one data tiles in the received data sector.

Abstract: Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data.

Abstract: A layered LDPC decoder sorts and selects a subset of message entries for processing based on entry size. MIN1 and MIN2 values for each message entry in the subset are truncated, and either the truncated values or non-truncated values are combined with a symbol vector based on whether the subset of message entries includes a variable node associated with the layer being processed.

Abstract: Apparatuses of wireless subscribers that manage storage of HARQ packets are disclosed. One embodiment of a wireless subscriber includes receiver circuitry for wirelessly receiving HARQ packets. CRC processing circuitry checks an error status of the received HARQ packets. A HARQ memory controller divides the HARQ packets into HARQ sub-packets for storage in HARQ memory. The HARQ memory controller records storage locations and a storage order of each of the HARQ sub-packets.

Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Abstract: The embodiments of the present invention provide a decoding method and a decoding device for a polar code cascaded with CRC. The decoding method includes: performing SC-List decoding on a Polar code according to the number of survival paths L to obtain L survival paths, where L is a positive integer; performing cyclic redundancy check on the L survival paths respectively; and increasing the number of survival paths when all the L survival paths fail to pass the cyclic redundancy check, and acquiring a decoding result of the Polar code according to the increased number of survival paths. In the embodiments of the present invention, the path number of survival paths is adjusted according to a result of the cyclic redundancy check, so as to output paths as much as possible, where the output paths can pass the cyclic redundancy check, thereby improving decoding performance.