Abstract: Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

Abstract: Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.

Abstract: The disclosure provides a look-up table (LUT) compression method and a LUT reading method for computation equipment and its host and device. In a LUT compression phase, the host retrieves an original data from an original LUT by using an original table address, checks the original data according to a reconstruction condition to obtain a check result (bitmap), converts the original data into a reconstructed data according to the check result, writes the reconstructed data to a compressed LUT by using a compressed table address, writes a relationship among the original table address, the compressed table address, and the check result (bitmap) to a mapping table, and stores the compressed LUT to the device.

Abstract: A split decoder apparatus in a communication system provides reliable transfer of a transmitted message from a source to a destination. A channel encoder encodes the transmitted message into a transmitted codeword from a channel code and transmits the transmitted codeword over a channel. The channel produces a channel output in response to the transmitted codeword. In the split decoder apparatus, a decode client receives the channel output and generates a compressed error information, and a decode server receives the compressed error information and generates a compressed error estimate. The decode client receives the compressed error estimate and generates a message estimate. Communication complexity between the decode client and the decode server is reduced. The split decoder apparatus optionally generates a no-errors signal from the channel output, where the decode server is not activated if the no-errors signal indicates that the hard decisions correspond to a valid transmitted codeword.

Abstract: One example includes a non-transitory storage medium storing a set of instructions, which upon being implemented by a processing element cause the processing element to initiate a burst update communication session from a master microcontroller device on a bus and provide a burst address in the burst update communication session from the master microcontroller device to slave microcontroller devices on the bus. The slave microcontroller devices on the bus can have a burst address to concurrently activate the slave microcontroller devices to read data. The instructions can also cause the processing element to provide burst data corresponding to a burst update from the master microcontroller device to the slave microcontroller devices on the bus based on the burst address, and conclude the burst update communication session from the master microcontroller device to the slave microcontroller devices on the bus.

Abstract: The technology described in this document can be embodied in a computer-implemented method that includes receiving, at one or more servers from a first computing device, (i) first identification information identifying the first computing device or an application executing on the first computing device, and (ii) second identification information identifying a second computing device. The second identification information is obtained by the first computing device by detecting changes to one or more parameters of a magnetic field generated by the second computing device. The method also includes determining, by the server based on the first information, identity information of a user associated with the first computing device, and transmitting, from the one or more servers to the second computing device, the identity information, such that the identity information is usable by the second computing device to verify an access attempt by the user.

Abstract: Embodiments of the present invention disclose a method for transmitting control information, a user equipment and a base station. The method includes: obtaining a resource occupied by first UCI, and obtaining a resource occupied by second UCI; performing channel encoding on the first UCI according to the resource occupied by the first UCI to obtain an encoded bit sequence of the first UCI, and performing channel encoding on the second UCI according to the resource occupied by the second UCI to obtain an encoded bit sequence of the second UCI; mapping the encoded bit sequence of the first UCI and the encoded bit sequence of the second UCI to a physical uplink channel, so as to transmit to a base station.

Abstract: A decoder includes a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.

Abstract: The present disclosure discloses a rate dematching method, device and receiving-side apparatus-. The method includes: acquiring new data to be processed, executing bit recovery/bit separation based on the new data to be processed, and writing data obtained after bit recovery/bit separation into a code block data memory; conducting sub-block deinterleaving processing on data stored in the code block data memory; and conducting hybrid automatic repeat request (HARQ) combination processing on output data after sub-block deinterleaving processing and acquired history data to be processed, and outputting HARQ combination results.

Abstract: A method for transmitting an input stream of data across a serial link including a serial channel. The method includes segmenting the stream of data into blocks of bits to form input blocks, and for each input block, calculating a measure of burst error probability, forming an output block and a modification signaling bit from the input block, transmitting the output block, and transmitting the modification signaling bit. The forming of the output block and the modification signaling bit from the input block includes, when the measure of burst error probability exceeds a set threshold: modifying the input block to form the output block, and asserting the modification signaling bit.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface, an encoder configured to generate eight code words, and a writing control unit. The writing control unit causes the memory interface to perform a first writing and a second writing, and repeat the first writing and the second writing. The first writing writes a first symbol included in a first code word to a second page in a first word line. The second writing writes a second symbol included in a first code word to a first page in a third word line adjacent to a second word line adjacent to a first word line. Thus, the code words to be written are changed. The repeat of the first writing and the second writing is performed by shifting a word line at a write destination one by one.

Abstract: An arrangement of interleavers allocates bits from an input symbol across sub-symbols transmitted via sub-carriers of multiple orthogonal frequency division multiplex (OFDM) carriers. The input bits are allocated in a fashion to provide separation across subcarriers, and rotation of sub-symbols across the OFDM carriers provides additional robustness in the present of signal path impairments.

Abstract: A wireless bit-interleaved coded OFDM (BI-COFDM) multiple-in-multiple-out (MIMO) system that improves the diversity seen by a convolutional decoder. The bit stream is interleaved first, then bits are mapped into symbols and then symbols are parsed into Nt separate streams, where t is the number of transmitters. A deinterleaver then performs the inverse permutation before sending the symbols to a Viturbi decoder. In another embodiment, a transmitting side bit-interleaver transforms an encoded and punctured bit stream using a first permutation, groups the transformed bit stream according to a desired constellation on one of Nt antennae, splits the transformed bit stream into separate streams accordingly and bit-interleaves/symbol-maps using a plurality of bit-interleavers/symbol-mappers to permute each stream using a second permutation. A receiving side performs the inverse operations of the transmitting side.

Abstract: A transmitting apparatus in a transport network, which performs forward error correcting encoding for each virtual lane set, which is a multiple of the number of transmission channels, in order to generate virtual frames including independent parity bytes for each of the virtual lanes. These generated virtual frames are transmitted through at least one transmission channel. A receiving apparatus for detecting the virtual frames for each virtual lane from a signal received through a transmission channel by using a frame assignment sequence, and performing forward error correcting decoding by using the parity bytes included in the virtual frames detected for each virtual lane.

Abstract: A memory system according to the embodiment comprises a p-adic number converter unit operative to convert ?-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.

Abstract: An arrangement of interleavers allocates bits from an input symbol across sub-symbols transmitted via sub-carriers of multiple orthogonal frequency division multiplex (OFDM) carriers. The input bits are allocated in a fashion to provide separation across subcarriers, and rotation of sub-symbols across the OFDM carriers provides additional robustness in the present of signal path impairments.

Abstract: In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.

Abstract: In an information processing device, error detection information is generated from additional information and a header is generated from error detection information. An encoded header is then generated by appending a header-error correction code to the header and encoded additional information is generated by appending an information-error correction code to the additional information. Finally, an information-appended image is generated by integratedly appending the encoded header and the encoded additional information to the target image.

Abstract: An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling.

Abstract: An arrangement of interleavers allocates bits from an input symbol across sub-symbols transmitted via sub-carriers of multiple orthogonal frequency division multiplex (OFDM) carriers. The input bits are allocated in a fashion to provide separation across subcarriers, and rotation of sub-symbols across the OFDM carriers provides additional robustness in the present of signal path impairments.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: An optical transport system (OTS) having a plurality of optical transponders (OTs) connected via one or more optical links and adapted to communicate with one another using respective rate-adaptive forward-error-correction (FEC) codes. In one embodiment, the OTS has a rate control unit (RCU) adapted to configure the OTs to dynamically adjust the rates of the FEC codes based on an estimated performance margin for each link between two respective communicating OTs to optimize the overall capacity of the OTS while maintaining an adequate, but not excessive, overall system margin.

Abstract: An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: An apparatus for encrypting and decrypting an original data stream is provided. The apparatus comprises: a key including a key-algorithm, an interleaver having at least one dynamically changeable interleaving parameter, and a de-interleaver adapted to communicate with a communication channel.

Abstract: A communication apparatus includes a transmitter and a receiver, wherein the transmitter further includes: an interleaver that rearranges positions of bits of an information frame; an FEC encoder that performs an error correction encoding to the information frame whose bit positions have been rearranged; and a selector that inserts FEC parity into predetermined positions of the information frame, to thereby generate a transmission signal, whereas the receiver includes: a selector that extracts an information frame part and an FEC parity part from a reception signal; an interleaver that rearranges positions of the bits of the information frame part using the same rule as that used at that transmitter side; an FEC decoder that corrects an error of bits rearranged based on the error correction parity part; and a de-interleaver that reproduces an information frame by returning positions of error-corrected bits to original bit positions.

Abstract: Disclosed herein is a method and system for interleaving and deinterleaving of data bits in wireless data communications. Interleaving is performed as a single stage parallel operation using a single standard memory block. The disclosed method and system is capable of implementing different interleaving techniques, individually, or as a combination thereof. The disclosed system comprises a plurality of multiplexers, a standard memory block, read and write buses, control block, and a lookup table. The contents of the lookup table are generated based on an interleaving function. The data bits from the input bus and bits from the read bus of the memory are inputted to the plurality of multiplexers. Based on the lookup table's contents the multiplexers are switched to parallelly permute the input data bits and read bits from the read bus. The permuted data bits are in an interleaved sequence.

Abstract: Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

Abstract: The invention relates to an encoding system and method for generating concatenated codes which utilize interleaving and data puncturing. The method includes selecting first and second puncture location sets defining desired puncture locations in non-interleaved and interleaved data sequences, respectively. A puncture-constrained interleaver is provided, which permutes the first puncture location set into the second puncture location set, so as to provide desired regular puncture patterns for all constituent codes. In a preferred embodiment, the puncture-constrained interleaving alters a symbol location relative to a puncture mask so as to satisfy a pre-defined spread or distance constraint.

Abstract: A method for encrypting and decrypting an original data stream comprising: (A) transmitting a copy of a key to an interleaver and to a de-interleaver, wherein the key includes a key-algorithm configured to describe an evolution in time of at least one interleaving parameter; (B) interleaving the original data stream by using the interleaver, wherein the interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter; and (C) recovering the original data stream from the interleaved data stream propagated through the communication channel by using the de-interleaver adapted to communicate with the communication channel, wherein the de-interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter.

Abstract: The present invention provides a method and apparatus for the efficient implementation of a totally general convolutional interleaver in a discrete multi-tone (DMT)-based digital subscriber line (xDSL) system, such as a modem or the like, that uses forward error correction (FEC) and convolutional interleaving to combat the effects of impulse noise and the like. More specifically, the present invention provides a method and apparatus for implementing a general convolutional interleaver, with no constraints, in an efficient manner, using (D?1)*(I?1)/2 memory locations for the interleaved data in all cases.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: Successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows are de-interleaved. The de-interleaving includes receiving each sequence of the interleaved data samples, and writing row by row the received sequences of interleaved data samples in a de-interleaving memory array having L rows and C columns, with L being greater or equal to L0 and C being greater or equal to C0. The data samples stored in the de-interleaving memory array are de-interleaved sub-array by sub-array. Each sub-array is a square cluster array having a number SQ of rows and columns. A cluster array is a row of the square cluster array comprising SQ data samples, with the number L of rows and the number C of columns of the de-interleaving memory array being multiples of the number SQ of rows and columns.

Abstract: An efficient bit interleaving scheme for a multi-band OFDM ultra-wideband (UWB) system. The encoded bits of the multi-band OFDM system are interleaved within each OFDM symbol and across OFDM symbols. The bit interleaving scheme minimizes performance degradation due to groups of contiguous OFDM tones experiencing a poor SNR caused by the frequency selective channel, exploits the frequency diversity across sub-bands, randomizes the effect of co-channel interference from simultaneously operating un-coordinated piconets, and randomizes the impact of generic narrow-band interferers present within the UWB spectrum.

Abstract: In the code word mapping operation of a radio communication system, mapping patterns are provided for different S/N ratios, the code word bits produced from a coder are not equally assigned to multi-level modulation bits, but weighted according to the resistance of multi-level modulation bits to error before being assigned, and the mapping patterns are switched in accordance with S/N. Since the code word mapping method is updated so that the error rate can be always minimized according to the situations of a propagation path and S/N ratio, communication can be made with high communication quality.

Abstract: A method of optimizing the size of blocks of coded data intended to be subjected to an iterative decoding process, a maximum error rate of the iterative decoding process being fixed in advance, in which there are sought, among a plurality of block sizes (N/k) which are submultiples of the normal block size by an integer factor (k) greater than or equal to 1 and a plurality of integers giving the maximum number of iterations that can be effected by the said iterative decoding on a block, (1) a submultiple size, and (2) a maximum number of iterations such that they are compatible with the maximum error rate, and such that the mean number of iterations that will be applied by the iterative decoding process on a block of submultiple size is minimized.

Abstract: A QCTC (Quasi-Complementary Turbo Code) generating apparatus having a turbo encoder for generating an information symbol sequence and a plurality of parity symbol sequences by encoding the information symbol sequence; a channel interleaver for individually interleaving the symbol sequences, generating new parity symbol sequences by multiplexing the symbols of parity symbol sequences with the same priority levels, and serially concatenating the information symbol sequence and the new parity symbol sequences; and a QCTC generator for generating a sub-code with a given code rate by recursively selecting a predetermined number of symbols from the concatenated symbol sequence at a given starting position.

Abstract: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and at least either columns or rows of the data to be transmitted randomly rearranged, facilitating the interleaving. The result is that biased distribution of data, which leads to degradation of the transmission quality, can be prevented relatively easily in a simple structure.

Abstract: An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N?B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)?(R?1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N?B).

Abstract: A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. Such memory-mapping in combination with data handling functions (e.g., multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).

Abstract: The present invention provides a system and method for explicitly transmitting a block attribute in the data of a block. In one embodiment, a current block of data is randomized in accordance with an ID value from the current block and from at least one temporally adjacent block of data. The ID of the current block is selected such that when combined with determined bits of the data results in the value of the block attribute. During a decoding process, the block attribute is retrieved by accessing the determined bits of the data. In one embodiment, the data is then decoded by generating possible candidate decodings and evaluating the candidate decodings based upon confidence metrics.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: The present invention provides for adaptive and multimode decoding, in a data packet-based communication system, to provide improved received signal quality in the presence of burst erasures or random bit errors, with particular suitability for real-time, delay sensitive applications, such as voice over Internet Protocol. In the presence of burst erasures, the adaptive multimode decoder of the present invention provides burst erasure correction decoding, preferably utilizes a maximally short (MS) burst erasure correcting code, which has a comparatively short decoding delay. Depending upon the level of such burst erasures, different rate MS codes may be utilized, or other codes may be utilized, such as hybrid or multidescriptive codes. When no burst erasures are detected, the adaptive multimode decoder of the present invention provides random bit error correction decoding, in lieu of or in addition to corresponding burst erasure correction coding.

Abstract: A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b?1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Ds is obtained. As a result, a burst error in the received information can be detected and corrected.