Abstract: A user equipment includes a wireless interface for communication with a cellular communication network. The user equipment is operative to receive, via the wireless interface, network assistance information for a media streaming session, and to transmit media streaming session related information to the cellular communication network.

Abstract: A wireless communication system can include an antenna and an equalization system. The antenna can be configured to wirelessly receive a data signal from a user equipment (UE). The equalization system can be configured to compensate for distortion incurred by the data signal during propagation. The equalization system can include a set of multiplier circuits. Each multiplier circuit can include a first input, a second input, a multiplier device, and a management circuit. The first input can receive a first input signal that corresponds to the data signal. The second input can receive a second input signal that corresponds to a weighting value assigned to a channel associated with the antenna. The multiplier device can be enabled or disabled. When enabled, the multiplier device can be configured to perform a multiplication operation on the first input signal and the second input signal. When disabled, the multiplier circuit may not perform the multiplication operation.

Abstract: This disclosure describes systems, methods, and devices related to extreme high throughput (EHT) data scrambler. A device may determine an extreme high throughput (EHT) data field of a frame to be scrambled using an EHT data scrambler. The device may determine to initialize the EHT data scrambler using an initialization seed, wherein the initialization seed has a size greater than seven bits. The device may generate scrambled data using the initialization seed. The device may cause to send the frame comprising the scrambled data to a first station device.

Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

Abstract: A transmitter for transmitting data to a receiver of a wireless communication network, the transmitter includes at least one antenna, a codebook, an encoder, and a transceiver coupled to the encoder and to the at least one antenna. The codebook includes a plurality of codewords, each codeword being a vector including a plurality of symbols, each symbol to be transmitted over resources of the wireless communication network. The encoder is configured to receive an information message to be transmitted to a receiver of the wireless communication network, to select from the codebook the codeword associated with the received information message, and to divide the selected codeword into a plurality of sub-codewords.

Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.

Abstract: A new radio (NR) bit prioritization procedure that may be executed by a UE and a base station is disclosed, resulting in transmission and reception of modulation symbols having prioritized bits. For example, a transmitter may encode a code block using low-density parity-check code to generate a stream of encoded bits. The transmitter may arrange the encoded bits in one or more modulation symbols according to a relative priority of the encoded bits. The highest priority bits may be located in the most significant bits of the modulation symbol, and therefore be less likely to experience errors. A receiver may receive the modulation symbols and reorder the encoded bits according to the coding scheme based on the relative priority prior to decoding the encoded bits. The prioritization of the bits within the modulation symbols may provide improved block error rates over sequential mapping of encoded bits to symbols.

Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

Abstract: Devices, systems and methods for improving the convergence of a bit-flipping decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, computing a plurality of flipping energies for each column of a first subset of columns from the plurality of columns of circulant matrices, computing, based on the plurality of flipping energies, one or more metrics, selecting, based on the one or more metrics, a second subset of columns from the first subset of columns in an order that is different from a sequential indexing order of the second subset of columns, determining, based on processing the second subset of columns using a vertically shuffled scheduling operation, a candidate version of the transmitted codeword.

Abstract: Transmitting, in a wireless local area network (WLAN), a second punctured coded bit sequence generated by puncturing coded data using a second puncturing pattern, wherein the coded data has previously been punctured using a first puncturing pattern to generate a first punctured coded bit sequence transmitted in the WLAN. The second puncturing pattern is different than the first puncturing pattern to cause at least some bits of the coded data that were omitted in the first punctured coded bit sequence to be included in the second punctured coded bit sequence.

Abstract: Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M?1)-th iteration, wherein M and N are positive integers, and wherein M?2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.

Abstract: A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

Abstract: A user equipment includes a wireless interface for communication with a cellular communication network. The user equipment is operative to receive, via the wireless interface, network assistance information for a media streaming session, and to transmit media streaming session related information to the cellular communication network.

Abstract: A method for sending communications with dynamic data correction to at least one receiving device includes dividing a message into one or more message blocks and determining corresponding redundancy blocks for the one or more message blocks, the redundancy blocks to be used by at least one of the receiving devices for message block detection or message block correction. The method further includes constructing a data packet including a header and a data payload including the one or more message blocks and the corresponding redundancy blocks. The construction of the data packet is such that it is processable by receiving devices that are configured to recognize and process the corresponding redundancy blocks and also processable by other receiving devices that cannot recognize the presence of the corresponding redundancy blocks. The method further includes sending the constructed data packet to the at least one receiving device.

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

Abstract: Methods, systems, and devices for wireless communication are described. Some wireless communications systems (e.g., New Radio (NR) systems) may support the dynamic configuration of time intervals (or slots) for communication in a specific link direction (e.g., uplink, downlink, sidelink, etc.). In such cases, a base station may dynamically allocate time intervals (or slots) for broadcast or multicast data (e.g., via a physical downlink control channel (PDCCH)) based on the dynamically determined configuration of certain time intervals (or slots). The dynamic allocation of resources for broadcast or multicast data may ensure that broadcast or multicast data is not scheduled to be transmitted during time intervals configured for uplink communication. In some cases, the broadcast or multicast data may be transmitted on a portion of a system bandwidth that is frequency division multiplexed with another portion of the system bandwidth allocated for mobile broadband (MBB) communications.

Abstract: A method and an apparatus for rate matching interleaving for polar codes are provided. The method includes: obtaining a first codeword bit sequence; dividing the first codeword bit sequence to obtain one or more segments; performing intra-segment and/or inter-segment interleaving on the one or more segments to generate an interleaved bit sequence.

Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.

Abstract: Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector LAPP; performing Cyclic Redundancy Check (CRC) on LAPP, and stopping if LAPP passes CRC; otherwise, determining magnitudes of LLRs in LAPP; identifying K LLRs in LAPP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting Lmax to maximum magnitude of LLRs in LAPP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}A(r(k))=LA(r(k))?Lmaxvksign[LAPP(r(k))], for k=1, 2, . . .

Abstract: A transmitter operating in a communication system is provided. The transmitter includes an encoding circuit and a modulation circuit. The transmitter is configured to generate multiple encoded bits according to an encoding relationship, in which the encoding relationship is corresponding to a code rate and a minimum distance, and the minimum distance is greater than a reciprocal of the code rate. The modulation circuit is configured to generate a transmission signal according to the encoded bits, such that the encoded bits are transmitted over multiple subcarriers, and each encoded bit is transmitted via a subcarrier. The encoding relationship is corresponding to multiple output codewords, and the minimum distance represents a minimum Hamming distance between two distinct output codewords. One of the output codewords includes the encoded bits.

Abstract: Methods, systems, and devices for object recognition are described. Generally, the described techniques provide for a compact and efficient convolutional neural network (CNN) model for facial recognition. The proposed techniques relate to a light model with a set of layers of convolution and one fully connected layer for feature representation. A new building block of for each convolution layer is proposed. A maximum feature map (MFM) operation may be employed to reduce channels (e.g., by combining two or more channels via maximum feature selection within the channels). Depth-wise separable convolution may be employed for computation reduction (e.g., reduction of convolution computation). Batch normalization may be applied to normalize the output of the convolution layers and the fully connected layer (e.g., to prevent overfitting). The described techniques provide a compact and efficient CNN model which can be used for efficient and effective face recognition.

Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

Abstract: An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.

Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.

Abstract: Systems, methods, and apparatus are provided for iteratively decoding a codeword. Once a codeword is received, the codeword is processed to generate an incremental hard decision value and a log likelihood ratio amplitude value. These values are generated by processing the codeword using a soft output Viterbi algorithm. A faulty symbol in the codeword is identified. A complete hard decision value is generated using the incremental hard decision value. The LLR amplitude value and complete hard decision value corresponding to the identified faulty symbol are selectively provided to a decoder and the decoder uses these values to decode the codeword.

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.

Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.

Abstract: Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A method of performing interleaving, which is performed by a communication apparatus using a low-density parity-check code (LDPC), includes outputting LDPC encoded bits to a block interleaver, and performing block interleaving on the LDPC encoded bits inputted to the block interleaver in a unit of a size of one time transport block based on the a position of redundancy version.

Abstract: Methods and apparatuses are provided for operating a list Viterbi decoder. A path metric difference (PMD) threshold is set based on an input signal level and a PMD limit value. Decoding is performed by using the PMD threshold. Performing the decoding includes determining a PMD of a best path, comparing the determined PMD and the PMD threshold, and declaring a decoding failure and ending performing of the decoding, if the PMD is greater than or equal to the PMD threshold.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

Abstract: A radio receiver comprises physical layer circuitry and processor circuitry. The physical layer circuitry receives quadrature amplitude modulation (QAM) symbols via a plurality of subcarriers included in a broadcast radio signal. Each received QAM symbol is a complex symbol comprising multiple bits of encoded source information. The processing circuitry demodulates the received data symbols, generates a constellation sample for each received QAM symbol, generates a soft metric for each bit of encoded information of the received QAM symbols using the constellation sample, and multiplies the soft metric by a channel state information (CSI) weight to produce a Log-likelihood Ratio (LLR) approximation for each bit of encoded information of the received QAM symbols.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.

Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.

Abstract: A method and system for decoding a signal are provided. The method includes receiving a signal, where the signal includes at least one symbol; decoding the signal in stages, where each at least one symbol is decoded into at least one bit per stage, wherein a Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining the magnitudes of the LLRs; identifying K bits of the signal with the smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with the largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords, and stopping after a first candidate codeword passes the CRC.

Abstract: It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

Abstract: Methods and apparatuses are provided for transmitting data. A codeword is generated by encoding an information word. Parity bits of the codeword are grouped into a plurality of groups. The parity bits are interleaved according to a predetermined order. One or more of the interleaved parity bits are punctured to generate a punctured codeword. A frame including a portion of the punctured codeword is transmitted.

Abstract: A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

Abstract: A communication system includes: a validation module configured to transmit a repeat request corresponding to a preceding data including a communication content; an inter-block processing module, coupled to the validation module, configured to determine a previous communication value based on the preceding data; a detection module, coupled to the inter-block processing module, configured to identify a repeat data corresponding to the repeat request from a receiver signal; an accumulator module, coupled to the detection module, configured to generate an accumulation output based on the preceding data and the repeat data; and a decoding module, coupled to the accumulator module, configured to determine the communication content using the previous communication value and the accumulation output across instances of transmission blocks for communicating with a device.

Abstract: A sensor information processing apparatus according to one embodiment of the present invention is a sensor information processing apparatus 251 for processing measured result from a plurality of sensors 202, and it includes a sensing information obtaining section 12 for obtaining sensing information including the measured results in the sensors 202 from radio signals received from the sensors 202, and a time synchronizing section 13 for temporally relate the measured results included in the sensing information obtained by the sensing information obtaining section 12 to each other.

Abstract: This disclosure describes methods, apparatus, and systems related to a modulation and coding scheme (MCS) system. The device may determine a wireless communications channel with a first device in accordance with a wireless communications standard. The device may generate a header in accordance with a communication standard, the header including, at least in part, a modulation and coding scheme (MCS) index value. The device may determine a code rate associated with the MCS index value based at least in part on the wireless communications channel. The device may cause to send the header to the first device over the wireless communications channel based at least in part on the MCS index value.

Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.

Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.

Abstract: Methods and systems for providing efficient communications between two mobile stations served by the same base station or relay station are provided. A base station maintains information identifying which mobile stations it is serving. When a connection is set up between two mobile stations, if they are both being served by the same base station, the base station forwards traffic directly between the two mobile stations without forwarding it on to higher level network entities.

Abstract: A transmitting system and a method for processing data are disclosed herein. The transmitting system includes a service multiplexer and at least one transmitter located in a remote position from the service multiplexer. Herein, the service multiplexer generates an RS frame having the size of N (row)×187 (column) bytes including at least one type of mobile service data, packetizes the RS frame into a plurality of mobile service data packets, and multiplexes the packetized mobile service data packets with a main service data packet at a predetermined data rate, thereby transmitting the multiplexed data packets. Herein, each mobile service data packet is configured of a TS header and a data region, and the data region is configured of at least one of a payload region and an adaptation field region.