Forward Error Correction By Tree Code (e.g., Convolutional) Patents (Class 714/786)
  • Patent number: 10706267
    Abstract: Methods, systems, and devices for object recognition are described. Generally, the described techniques provide for a compact and efficient convolutional neural network (CNN) model for facial recognition. The proposed techniques relate to a light model with a set of layers of convolution and one fully connected layer for feature representation. A new building block of for each convolution layer is proposed. A maximum feature map (MFM) operation may be employed to reduce channels (e.g., by combining two or more channels via maximum feature selection within the channels). Depth-wise separable convolution may be employed for computation reduction (e.g., reduction of convolution computation). Batch normalization may be applied to normalize the output of the convolution layers and the fully connected layer (e.g., to prevent overfitting). The described techniques provide a compact and efficient CNN model which can be used for efficient and effective face recognition.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lei Wang, Ning Bi, Yingyong Qi
  • Patent number: 10637501
    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 28, 2020
    Assignee: INPHI CORPORATION
    Inventors: Andre Szczepanek, Arash Farhoodfar, Sudeep Bhoja, Sean Batty, Shaun Lytollis
  • Patent number: 10606695
    Abstract: An error correction circuit includes a decoder including a plurality of check node units and variable node units corresponding to a parity check matrix of low density parity check (LDPC) scheme, and configured to generate decoded data by decoding a codeword; a syndrome check circuit configured to calculate a reference value for the codeword based on the parity check matrix, and generate a decoder operation control signal corresponding to the reference value; and a control circuit configured to control whether to operate each of the plurality of check node units and variable node units of the decoder in response to the decoder operation control signal, wherein the decoder decodes the codeword based on check node units and variable node units which operate according to the control of the control circuit among the plurality of check node units and variable node units.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Kwang Hyun Kim
  • Patent number: 10579560
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 3, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang
  • Patent number: 10547328
    Abstract: Systems, methods, and apparatus are provided for iteratively decoding a codeword. Once a codeword is received, the codeword is processed to generate an incremental hard decision value and a log likelihood ratio amplitude value. These values are generated by processing the codeword using a soft output Viterbi algorithm. A faulty symbol in the codeword is identified. A complete hard decision value is generated using the incremental hard decision value. The LLR amplitude value and complete hard decision value corresponding to the identified faulty symbol are selectively provided to a decoder and the decoder uses these values to decode the codeword.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 28, 2020
    Assignee: Marvell International Ltd.
    Inventors: Shu Li, Yifei Zhang, Wei Cao
  • Patent number: 10536156
    Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 14, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Ashish Senapati, Kevin Kilzer, Prashanth Pulipaka
  • Patent number: 10505678
    Abstract: In one embodiment an apparatus, method, and system is described, the embodiment an apparatus, method including receiving a stream of data frames at an input interface, the data frames one of including security frames, or being included in security frames, wherein the security frames include payload data, performing forward error correction on the data frames a forward error correction (FEC) decoder, buffering received data frames at a buffer and blanker engine and building a complete security frame of the received data frames, determining whether or not to suppress taking a consequent action based on a frequency of authentication errors at an authentication engine, wherein the consequent action to be taken or suppressed, when taken, is taken upon payload data of one or more security frames including a data frame upon which an authentication error occurred. Related apparatus, methods and systems are also described.
    Type: Grant
    Filed: March 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Stefan Langenbach, Gilberto Loprieno, Alessandro Cavaciuti
  • Patent number: 10498349
    Abstract: Disclosed is a bit error rate (BER) forecast circuit for successive approximation register analog-to-digital conversion. The BER forecast circuit includes an N bits successive approximation register analog-to-digital converter (N bits SAR ADC) and an estimation circuit. The N bits SAR ADC is configured to carry out a regular operation at least N times and an additional operation at least X time(s) in one cycle of conversion time, in which the N is an integer greater than 1 and the X is an integer not less than zero. The estimation circuit is configured to generate a test value according to total times the N bits SAR ADC carrying out the additional operation in Y cycles of the conversion time, in which the Y is a positive integer and the test value is related to the bit error rate of the N bits SAR ADC.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Xuan Huang, Liang-Huan Lei, Shih-Hsiung Huang, Liang-Wei Huang
  • Patent number: 10447304
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 15, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10447312
    Abstract: A method of performing interleaving, which is performed by a communication apparatus using a low-density parity-check code (LDPC), includes outputting LDPC encoded bits to a block interleaver, and performing block interleaving on the LDPC encoded bits inputted to the block interleaver in a unit of a size of one time transport block based on the a position of redundancy version.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 15, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Jinwoo Kim, Jongwoong Shin, Bonghoe Kim, Byounghoon Kim, Kwangseok Noh
  • Patent number: 10439651
    Abstract: Methods and apparatuses are provided for operating a list Viterbi decoder. A path metric difference (PMD) threshold is set based on an input signal level and a PMD limit value. Decoding is performed by using the PMD threshold. Performing the decoding includes determining a PMD of a best path, comparing the determined PMD and the PMD threshold, and declaring a decoding failure and ending performing of the decoding, if the PMD is greater than or equal to the PMD threshold.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Daeson Kim, Mingoo Kim, Chaehag Yi
  • Patent number: 10419159
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 17, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10389389
    Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Goldenberg, Stella Achtenberg, Alexander Bazarsky, Eran Sharon, Karin Inbar, Michael Ionin
  • Patent number: 10355714
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10355908
    Abstract: A radio receiver comprises physical layer circuitry and processor circuitry. The physical layer circuitry receives quadrature amplitude modulation (QAM) symbols via a plurality of subcarriers included in a broadcast radio signal. Each received QAM symbol is a complex symbol comprising multiple bits of encoded source information. The processing circuitry demodulates the received data symbols, generates a constellation sample for each received QAM symbol, generates a soft metric for each bit of encoded information of the received QAM symbols using the constellation sample, and multiplies the soft metric by a channel state information (CSI) weight to produce a Log-likelihood Ratio (LLR) approximation for each bit of encoded information of the received QAM symbols.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 16, 2019
    Assignee: Ibiquity Digital Corporation
    Inventors: Paul J. Peyla, Brian W. Kroeger
  • Patent number: 10305632
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 10270463
    Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 23, 2019
    Assignee: NEWRACOM, INC.
    Inventors: Dae Won Lee, Yujin Noh, Sungho Moon, Young Hoon Kwon
  • Patent number: 10205470
    Abstract: A method and system for decoding a signal are provided. The method includes receiving a signal, where the signal includes at least one symbol; decoding the signal in stages, where each at least one symbol is decoded into at least one bit per stage, wherein a Log-Likelihood Ratio (LLR) and a path metric are determined for each possible path for each at least one bit at each stage; determining the magnitudes of the LLRs; identifying K bits of the signal with the smallest corresponding LLR magnitudes; identifying, for each of the K bits, L possible paths with the largest path metrics at each decoder stage for a user-definable number of decoder stages; performing forward and backward traces, for each of the L possible paths, to determine candidate codewords; performing a Cyclic Redundancy Check (CRC) on the candidate codewords, and stopping after a first candidate codeword passes the CRC.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mostafa El-Khamy, Jinhong Wu, Jungwon Lee, Inyup Kang
  • Patent number: 10193568
    Abstract: It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: January 29, 2019
    Assignee: Alcatel Lucent
    Inventors: Luca Razzetti, Giancarlo Gavioli, Carlo Constantini, Marianna Pepe
  • Patent number: 10116333
    Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ran Zamir, Alexander Bazarsky, Stella Achtenberg, Omer Fainzilber, Eran Sharon
  • Patent number: 10038576
    Abstract: Methods and apparatuses are provided for transmitting data. A codeword is generated by encoding an information word. Parity bits of the codeword are grouped into a plurality of groups. The parity bits are interleaved according to a predetermined order. One or more of the interleaved parity bits are punctured to generate a punctured codeword. A frame including a portion of the punctured codeword is transmitted.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: July 31, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sil Jeong, Sung-Ryul Yun, Jae-Yoel Kim, Hyun-Koo Yang, Hak-Ju Lee, Se-Ho Myung, Jin-Hee Jeong
  • Patent number: 9991907
    Abstract: A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 5, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventor: Dariush Dabiri
  • Patent number: 9954643
    Abstract: A communication system includes: a validation module configured to transmit a repeat request corresponding to a preceding data including a communication content; an inter-block processing module, coupled to the validation module, configured to determine a previous communication value based on the preceding data; a detection module, coupled to the inter-block processing module, configured to identify a repeat data corresponding to the repeat request from a receiver signal; an accumulator module, coupled to the detection module, configured to generate an accumulation output based on the preceding data and the repeat data; and a decoding module, coupled to the accumulator module, configured to determine the communication content using the previous communication value and the accumulation output across instances of transmission blocks for communicating with a device.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mostafa El-Khamy, Jungwon Lee, Inyup Kang
  • Patent number: 9907039
    Abstract: A sensor information processing apparatus according to one embodiment of the present invention is a sensor information processing apparatus 251 for processing measured result from a plurality of sensors 202, and it includes a sensing information obtaining section 12 for obtaining sensing information including the measured results in the sensors 202 from radio signals received from the sensors 202, and a time synchronizing section 13 for temporally relate the measured results included in the sensing information obtained by the sensing information obtaining section 12 to each other.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 27, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hirotsugu Yamamoto, Yoshizo Tanaka
  • Patent number: 9847849
    Abstract: This disclosure describes methods, apparatus, and systems related to a modulation and coding scheme (MCS) system. The device may determine a wireless communications channel with a first device in accordance with a wireless communications standard. The device may generate a header in accordance with a communication standard, the header including, at least in part, a modulation and coding scheme (MCS) index value. The device may determine a code rate associated with the MCS index value based at least in part on the wireless communications channel. The device may cause to send the header to the first device over the wireless communications channel based at least in part on the MCS index value.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel IP Corporation
    Inventors: Maxim Greenberg, Assaf Kasher, Michael Genossar, Igor Gutman
  • Patent number: 9837156
    Abstract: The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changkyu Seol, Junjin Kong, JongHa Kim, Hyejeong So, Hong Rak Son, Seonghyeog Choi
  • Patent number: 9742433
    Abstract: A wireless device generates a High Efficiency Signal B (HE-SIG-B) field by Block Convolution Code (BCC) encoding and rate-matching a BCC block of the HE-SIG-B field, generates a Physical Layer Protocol Data Unit (PPDU) including the HE-SIG-B field, and transmits the PPDU. A total number N is a total number of bits of the HE-SIG-B field that precede the BCC block, and is greater than 0. The BCC block has a puncturing pattern depending on the total number N. A wireless device receives a PPDU. The PPDU includes an HE-SIG-B field that includes an encoded BCC block. The wireless device de-rate-matches the encoded BCC block having a puncturing pattern depending on a total number N. The total number N is a total number of decoded bits of the HE-SIG-B field that preceded the BCC block, and the total number N is greater than 0.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 22, 2017
    Assignee: NEWRACOM, INC.
    Inventors: Dae Won Lee, Yujin Noh, Sungho Moon, Young Hoon Kwon
  • Patent number: 9686681
    Abstract: Methods and systems for providing efficient communications between two mobile stations served by the same base station or relay station are provided. A base station maintains information identifying which mobile stations it is serving. When a connection is set up between two mobile stations, if they are both being served by the same base station, the base station forwards traffic directly between the two mobile stations without forwarding it on to higher level network entities.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 20, 2017
    Assignee: Apple Inc.
    Inventors: Hang Zhang, Peiying Zhu, Wen Tong, Nimal Gamini Senarath, Derek Yu
  • Patent number: 9647798
    Abstract: A decoding method applied to a convolutionally coded signal is provided. The method includes: adjusting first input information according to a first scaling factor to generate first a-priori information; b) decoding the convolutionally coded signal according to systematic information and the first a-priori information to generate first extrinsic information; c) adjusting second input information according to a second scaling factor to generate second a-priori information, wherein the second scaling factor is generated according to the first extrinsic information and the first a-priori information; and d) decoding the convolutionally coded signal according to the systematic information and the second a-priori information to generate second extrinsic information. One of step (b) and step (d) further generates a-posteriori information as a decoding result.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 9, 2017
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: Yu-Hsien Ku
  • Patent number: 9621385
    Abstract: System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Timothy Mowry Hollis
  • Patent number: 9577677
    Abstract: A method for transmitting data using a convolutional turbo code (CTC) encoder. Specifically, the method comprises: encoding input data bits, which have been input through two input ports of the CTC encoder; interleaving the input data bits using four CTC interleaver parameters P0, P1, P2 and P3 corresponding to sizes of the input data bits; encoding the interleaved data bits; and selectively transmitting the input data bits, the first encoded bits and the second encoded bits, in accordance with a predetermined coding rate. Here, P0 is a relative prime number to N, which is ½ of the size of each of the input data bits, P2 has a value of N?1, and an absolute value of a difference between P1 and P3 is 1.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 21, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Seunghyun Kang, Jinsam Kwak
  • Patent number: 9490846
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 8, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9485792
    Abstract: Methods and systems for providing efficient communications between two mobile stations served by the same base station or relay station are provided. A base station maintains information identifying which mobile stations it is serving. When a connection is set up between two mobile stations, if they are both being served by the same base station, the base station forwards traffic directly between the two mobile stations without forwarding it on to higher level network entities.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: November 1, 2016
    Assignee: Apple Inc.
    Inventors: Hang Zhang, Peiying Zhu, Wen Tong, Nimal Gamini Senarath, Derek Yu
  • Patent number: 9450611
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: September 20, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9313779
    Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for transmitting periodic channel state information having large payload sizes. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: April 12, 2016
    Assignee: Intel Corporation
    Inventors: Seunghee Han, Hong He, Shafi Bashar, Jong-Kae Fwu, Yuan Zhu
  • Patent number: 9236887
    Abstract: A method of encoding data operates on an ordered set of input symbols and includes generating redundant symbols from the input symbols, and includes generating output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols. The redundant symbols are generated from an ordered set of input symbols in a deterministic process such that a first set of static symbols calculated using a first input symbol has a low common membership with a second set of static symbols calculated using a second input symbol distinct from the first input symbol.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 12, 2016
    Assignee: Digital Fountain, Inc.
    Inventors: Michael G. Luby, M. Amin Shokrollahi, Mark Watson
  • Patent number: 9232287
    Abstract: Disclosed in the present invention are a method and apparatus for processing downlink frame synchronization in a Gigabit-capable passive optical network (GPON) system, wherein the method comprises: carrying out forward error correction (FEC) encoding on data in a synchronization domain of a downlink frame of the GPON system, wherein the synchronization domain includes a physical synchronization (Psync) domain and an identifier (Ident) domain; filling the FEC encoded data into an FEC check domain provided in the downlink frame; and sending the downlink frame. By virtue of the present invention, the effect of improving the reliability of GPON downlink frame synchronization is achieved.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: January 5, 2016
    Assignee: ZTE CORPORATION
    Inventor: Jun Jin
  • Patent number: 9219503
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. Some embodiments include one or both of a multi-algorithm data encoder circuit and/or a multi-algorithm data decoder circuit. In some cases, a first algorithm encoding is applied on a first section by section basis to a user data set yield an encoded portion; and a second algorithm encoding is applied on a second section by section basis to a data set derived from a subset of the encoded portion.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 22, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shu Li, Fan Zhang, Bruce A. Wilson, Jun Xiao
  • Patent number: 9203443
    Abstract: Optimal period rate matching for turbo coding. A means is provided herein by which a nearly optimal (e.g., optimal for one block size and sub-optimal for others) periodic puncturing pattern that depends on a mother code. Any desired rate matching can be achieved using the means and approaches presented herein to ensure an appropriate rate of an encoded block output from a turbo encoder so that the subsequently modulated signal generated there from has the appropriate rate. In addition, some embodiments can also employ shifting for another design level available in accordance with puncturing employed to provide for periodic rate matching. Selectivity can also be employed, such that, a first periodic puncturing pattern can be applied at a first time to ensure a first rate, and a second periodic puncturing pattern can be applied at a second time to ensure a second rate.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: December 1, 2015
    Assignee: BROADCOM CORPORATION
    Inventors: Ba-Zhong Shen, Tak K. Lee
  • Patent number: 9184536
    Abstract: A port of a computing system includes a connector movable between a recessed position and an extended position. The connector is extended from the recessed position to the extended position in response to a plug.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: November 10, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Mark David Senatori
  • Patent number: 9178663
    Abstract: The present invention relates to a method and apparatus in which a base station transmits a physical ARQ channel (PHICH) in a wireless communication system. More particularly, the present invention relates to a method and apparatus for transmitting a PHICH, wherein the method comprises the following steps: generating a plurality of hybrid of ARQ (HARQ) indicators: channel-coding the plurality of HARQ indicators into a single HARQ codeword; and transmitting the HARQ codeword via the PHICH, wherein the value of a portion of the HARQ codeword indicates individual value of each of HARQ indicators, and the value of the rest of the HARQ codeword indicators a value of joint operation of the plurality of HARQ indicators.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 3, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Seung Hee Han, Jae Hoon Chung, Ji Woong Jang, Moon Il Lee
  • Patent number: 9160370
    Abstract: A memory system is described that provides error detection and correction after a failure of a memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-2 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and an inner check bit column including X inner check bits. The inner check bits are defined to cover bits in the array according to a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system. Moreover, each column is stored in a different memory component, and the check bits are generated from the data bits to provide block-level detection and correction for both memory errors and a failed memory component.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: October 13, 2015
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Paul N. Loewenstein
  • Patent number: 9136874
    Abstract: A method of transmitting digital information includes: receiving a plurality of information bits representing audio information and/or data; encoding the information bits using complementary low density parity check coding to produce a composite codeword and a plurality of independently decodable semi-codewords; modulating at least one carrier signal with the forward error corrected bits; and transmitting the carrier signal(s). Transmitters that implement the method, and receivers that receive signals produced by the method, are also provided.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: iBiquity Digital Corporation
    Inventors: Brian W. Kroeger, Paul J. Peyla
  • Patent number: 9136880
    Abstract: The present document discloses a method for stopping iteration in an iterative Turbo decoder and an iterative Turbo decoder. Hard decisions from the two convolutional decoders of the iterative Turbo decoder are used simultaneously to determining when to stop the iteration in the iterative Turbo decoder.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: September 15, 2015
    Assignee: ZTE WISTRON TELECOM AB
    Inventor: Hans Grubeck
  • Patent number: 9071471
    Abstract: Disclosed are methods and structures for soft symbol and variance estimation for QAM constellations including a big-flipping framework and efficient methods for soft symbol estimation and variance estimation for QAM. Disclosed are efficient Gray mapping which provides a much lower complexity, i.e., log N for N-QAM for both squared and non-squared QAM constellations. Also disclosed is an approximation method that avoids multiplications completely while exhibiting only a slight performance degradation. Finally, a low complexity method for variance estimations, particularly second moment estimations for both squared and non-squared QAM constellations with Gray mapping are disclosed. Advantageously—using the disclosed methods—the complexity of the second moment estimation is reduced to O((log N)^2) for an N-QAM symbol for both squared and non-squared QAM.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 30, 2015
    Inventors: Guosen Yue, Sampath Rangarajan
  • Patent number: 9071401
    Abstract: Presented herein are pilot-less noise estimation techniques that utilize a correlation between attributes of a received signal and the noise to generate signal-to-noise ratio (SNR) estimate for the signal. More specifically, an interval of a digital signal is received a log-likelihood ratio (LLR) value is calculated for a plurality of bits in the interval of the signal. A scalar value that relates to a distribution of the calculated LLR values is computed. The SNR for the interval of the signal is determined based on a predetermined correlation between the scalar value and noise within the received interval of the signal.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: June 30, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Hang Jin, Koen Van Renterghem, Richard Meller, Denis Downey
  • Patent number: 9043686
    Abstract: A method for decoding and checking a tail-biting convolutional code is provided. The method fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 26, 2015
    Assignee: ZTE Corporation
    Inventor: Ming Gong
  • Publication number: 20150143207
    Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 21, 2015
    Inventor: Jung-Fu Cheng
  • Patent number: 9032271
    Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
  • Patent number: RE46740
    Abstract: A transmitting system and a method for processing data are disclosed herein. The transmitting system includes a service multiplexer and at least one transmitter located in a remote position from the service multiplexer. Herein, the service multiplexer generates an RS frame having the size of N (row)×187 (column) bytes including at least one type of mobile service data, packetizes the RS frame into a plurality of mobile service data packets, and multiplexes the packetized mobile service data packets with a main service data packet at a predetermined data rate, thereby transmitting the multiplexed data packets. Herein, each mobile service data packet is configured of a TS header and a data region, and the data region is configured of at least one of a payload region and an adaptation field region.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: February 27, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Chul Soo Lee, Sang Kil Park, In Hwan Choi