Abstract: Embodiments of the present disclosure disclose an encoding method. The method includes: obtaining a corresponding index value from an index module based on values in Z to-be-encoded bits that are obtained and a state space value in a state space module, performing an operation based on the index value and the state space value to obtain a new state space value, encoding the Z to-be-encoded bits that are obtained, and obtaining a value from the new state space value and assigning the value to an auxiliary bit.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

Abstract: Methods, systems, and devices for wireless communication are described. In a new radio (NR) system, a wireless device may identify a candidate codeword for a channel employing polar coding. The wireless device may perform a decoding operation on the candidate codeword to determine candidate decoding paths corresponding to encoded information bits. The decoding operation may include multiple decoding path candidates, each of which is associated with a path metric. The wireless device may evaluate a spread metric to determine if a decoding hypothesis is incorrect or if the received codeword is too corrupted for decoding. The spread metric may be based on the path metrics of the decoding paths or soft metrics of the decoding paths determined based on a subset of bit channels of the polar code. The wireless device may normalize the spread metric to compensate for signal-to-noise ratio (SNR) variation.

Abstract: There is provided a disk-type recording medium, a recording apparatus, a recording method, a reproducing apparatus, and a reproducing method, which are capable of recording, for example, data with high density and reproducing data recorded with high density robustly. In the disk-type recording medium, synchronization patterns for synchronization are recorded in two adjacent tracks with a shift in a track direction so that positions in the track direction do not overlap. The present technology can be applied to, for example, optical discs, other disk-type recording mediums, and the like.

Abstract: A system can include a well tool operable to transmit a fluid through an interior of the well tool. The system can also include a transmitter coupled to the well tool. The transmitter can select a parameter of a pressure waveform using a Gray code that corresponds to the parameter and generate the pressure waveform in the fluid.

Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Abstract: An apparatus and method for synchronization of a decoding unit to a received data bit stream, DBS, encoded according to a data protocol, DP, said apparatus comprising a sampling unit adapted to sample a bit sequence, BSEQ, having a predetermined bit sequence length, BSEQL, from the received data bit stream, DBS, and a checking unit configured to check whether at least one specific bit of the sampled bit sequence, BSEQ, fulfills a predetermined error detection condition, EDC, defined by said data protocol, DP, and further configured to synchronize the decoding unit to the received data bit stream, DBS, if the checking result is positive.

Abstract: A communication system includes an antenna. A signal transmission and reception unit for cellular CDMA communication and a signal transmission and reception unit for PCS COMA communication are coupled to the antenna.

Abstract: A performance screen ring oscillator (PSRO) formed from paired scan chains is disclosed. A circuit structure comprises scan chains each having scan chain elements. A scan chain link is configured to pair at least one scan chain element from a first scan chain with at least one scan chain element of a second scan chain to form a PSRO. A forward path associated with data flow through the at least one scan chain element of the first scan chain becomes a backward path of the at least one scan chain element of the second scan chain, and a forward path associated with data flow through the at least one scan chain element of the second scan chain becomes a backward path of the at least one scan chain element of the first scan chain.

Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.

Abstract: A method and apparatus are provided for adapting the data blocks to be supplied to a turbo coder, wherein the adaptation of the block length of the data blocks to the minimum required block length of the turbo coder is insured without the disadvantage of the suboptimum termination of the turbo coder.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting may be performed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization may be effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: Abstract: Disclosed in the present application is a method for transmitting data from a transmitting side in a mobile communication system. Specifically, the method comprises: a first encoding to output first encoded bits by encoding input data bits, which have been input through two input ports of the CTC encoder; interleaving the input data bits using four CTC interleaver parameters P0, P1, P2 and P3 corresponding to sizes of the input data bits; a second encoding to output second encoded bits by encoding the interleaved data bits; and selectively transmitting, to a receiving side, the input data bits, the first encoded bits and the second encoded bits, in accordance with a predetermined coding rate.

Abstract: A method of producing a mainly carbonate bonded article includes a step of providing an alkaline granular material having one or more alkaline earth metal silicate phases. The method includes a step of compacting the granular material to obtain a compact of the granular material. The porosity of the compact is smaller than or equal to 37% by volume. The intrinsic permeability of the compact is at least 1·10?12 cm2. The method also includes a reacting step arranged to form at least 5% by weight of carbonates (CO32?), by reacting the granular material with carbon dioxide in the presence of water, thus transforming the compact into the article. In the reacting step, the compact, being unsaturated with moisture at the beginning of the reacting step, is brought in an atmosphere having carbon dioxide. The atmosphere is at a temperature of at least 70° C. and at a pressure of at least 0.5 MPa. The pressure is also higher than the saturated vapor pressure of water at the temperature.

Abstract: A method for protecting signalling information in a frame to be transmitted to a receiver in a communication system, comprising: encoding frame signalling information of the frame to protect the frame signalling information; and encoding Forward Error Correction FEC block signalling information of FEC blocks in the frame by using Reed-Muller codes to protect the FEC block signaling information.

Abstract: A method for protecting signalling information in a frame to be transmitted to a receiver in a communication system, comprising: encoding frame signalling information of the frame to protect the frame signalling information; and encoding Forward Error Correction FEC block signalling information of FEC blocks in the frame by using Reed-Muller codes to protect the FEC block signaling information.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.

Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

Abstract: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder.

Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.

Abstract: A method of recovering data in a line signal which is predicted to be subjected to repetitive noise impulses, the line signal comprising a series of data frames, the method comprising the steps of: predicting a group comprising one or more frames in said line signal which are expected to be corrupted by a noise signal; blanking said group of one or more frames which are predicted to be corrupted; determining the preceding and succeeding frames adjacent to said group; and including in each said group of one or more frames one or more parity blocks wherein if said noise signal deviates from its predicted timing interval or duration and corrupts the data carried in one or more of said frames adjacent to said group, the corrupted data is recovered using one or more of said parity blocks of said group of blanked frames and the other one of said adjacent frames.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: A system and method are provided for accelerating forward error correction (FEC) synchronization in a communicating receiver. On the transmitter side, the method accepts an energy waveform representing a packet of data symbols, encodes the packet, and creates an FEC block. Prior to transmitting the FEC block, an electromagnetic waveform is transmitted representing an FEC flag character. Then, an electromagnetic waveform representing the FEC block is transmitted a predetermined first period of time after the transmission of the FEC flag character. For example, the first time period may be immediately following the FEC flag character transmission or a predetermined number of idle characters following the transmission of the FEC flag character.

Abstract: A video receiving apparatus includes a receiving unit, a detecting unit, a determining unit, and a control unit. The receiving unit receives a video stream transmitted from a video distribution apparatus and to be reproduced by a video reproducing unit. The detecting unit detects an error occurrence position on the video stream in response to an error occurring during receiving of the video stream. The determining unit determines a reproduction start time based on the error occurrence position detected by the detecting unit and a position of a predetermined synchronization code in the video stream so that reproduction of the video stream is started before the error occurrence position. The control unit transmits a reproduction request including the determined reproduction start time to the video distribution apparatus.

Abstract: Systems and methods for encoding user information and decoding signal vectors using fractional encoding/decoding and set partitioning. A fractional encoder can select a coset for transmitting or storing user information based on one or more deterministic bits and on encoded user information. The deterministic bits limit the encoder to using only a subset of the available signal vectors in a modulation scheme. A fractional decoder can receive a signal vector, and can find at least two nearest neighbors in each dimension. The fractional decoder can form a set of potential signal vectors using only the at least two nearest neighbors. The decoder may determine which of these potential signal vectors are valid within the fractional signaling scheme, and can decode the received signal vector based on the valid potential signal vectors.

Abstract: Convolutional encoding throughput is increased by partitioning input information bits into a plurality of blocks that are convolutionally encoded in parallel. A plurality of convolutional encoding operations which have respective initial encode states that are mutually different from one another are applied in parallel to one of the blocks to produce a respectively corresponding plurality of convolutional encoding results. One of the convolutional encoding results is selected based on a convolutional encoding operation applied to another of the blocks.

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract: An iterative decoding device for a communication receiver includes a decoder for decoding received encoded data blocks by a next iteration initialization, a controller to choose one of the first and second hard decision bits in order for the validity of a CRC field, associated to this received data block, to be checked, and a first memory. The controller, when the CRC field of a block is invalid, orders the decoder to store the final stakes associated to the block in the first memory to require the transmission of a redundant version of the block, and when the redundant version is received, to initialize the decoder with the stored final stakes before it applies the next iteration initialization mechanism to the received redundant version.

Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.

Abstract: A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string.

Abstract: Systems and methods for synchronizing redundant data in a storage array are disclosed. In accordance with a method, a pointer indicating the amount of data synchronized between a first storage resource to a second storage resource may be maintained and a power event may be detected. In response to the detection of the power event, an attempt may be made to flush a write cache associated with the second storage resource to transfer data from the write cache to a non-volatile storage area of the second storage resource. A determination may be made whether the attempt to flush the write cache is successful. In response to determining that the attempt to flush the write cache is successful, a flag may be set to indicate that the pointer accurately indicates the amount of data mirrored from the first storage resource to the non-volatile storage area of the second storage resource.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: The present invention provides a method and apparatus for correcting symbol timing of a receiver. The receiver receives a signal transmitted by a transmitter based on a symbol period. The method includes: sampling the signal with a sampling period to generate N sampled data in series, wherein the sampling period is half the symbol period; from Kth data of the N sampled data, getting M data to serve as a first data set; performing a timing recovery algorithm upon the first data set to generate a first timing metric; from (Kth+1) data of the N sampled data, getting M data to serve as a second data set; performing the timing recovery algorithm upon the second data set to generate a second timing metric; and correcting the symbol timing according to the first and second timing metrics.

Abstract: First, a yield is calculated by employing conventional SSTA. Next, an independent LL set is determined, the independent LL set being a subset having sets of delay element sets that only include gates and nets not being shared by two or more paths. Next, a yield is calculated by employing SSTA while using only the independent LL set. Thereby, it is understood that the actual yield is between the yield obtained by employing the conventional SSTA and the yield obtained by employing the SSTA using only the independent LL set.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: This invention relates to a turbo decoding apparatus and method for a communication system. A high-rate memory buffer operating at the same frequency as a turbo decoder is arranged between a memory buffer of a receiver and the turbo decoder. The decoding apparatus reads data bits stored in the memory buffer of the receiver via the high-rate memory buffer, delays the read data bits for a time required in the turbo decoder, and then applies the delayed data bits to a Soft-In Soft-Out (SISO) decoder of the turbo decoder. The memory buffer of the receiver outputs data bits at an operating frequency or clock of the turbo decoder.

Abstract: A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream. The best-fit bit analysis block is operative to find a pattern of data bits that best matches the data bits in the incoming data stream. The bit engine further includes a missing bit insertion block to insert a dummy bit for each data bit where the best-fit bit analysis block cannot find a pattern match. An error correction block performs forward error correction on the decoded data stream, including the dummy bits, to generate a corrected outgoing data stream.

Abstract: A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The second device includes a Reed Solomon (RS) decoder having a RS lock indicator and a Moving Picture Experts Group (MPEG) Protocol Interface (MPI) having a MPI lock indicator, wherein the RS and MPI lock indicators are monitored. Four different states, defined by the values of the RS and MPI lock indicators, determine whether the data communication system will wait for the RS decoded and the MPI hardware block to resynchronize, whether an intermediate-subset of the channel acquisition algorithm is performed or whether the entire channel acquisition algorithm is performed. The method of resynchronization described herein recovers synchronization within a predetermined time without the layers above the physical link layer having knowledge.

Abstract: An embodiment is a circuit including 2n?1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n?1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n?2 second comparators generate a second result by comparing signals output from some of the 2n?1 first switching circuits. N may be a natural number greater than or equal to three.

Abstract: A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.

Abstract: A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates a bulk packet (or a control packet) which is a USB packet and has a predetermined structure including a first data area by describing data which is taken as an object of transfer in the first data area. The isochronous packet transmission unit generates an isochronous packet which is a packet in USB isochronous transfer and has a predetermined structure including a second data area by incorporating at least one bulk packet into the second data area, and isochronously transfers the isochronous packet to the mobile telephone over the USB interface.

Abstract: A signal transmitted from a radio tag is received, and an I-signal and a Q-signal are generated from the received signal. The I-signal and Q-signal are decoded, and a decoding error of the decoded data to be detected is detected and a decoded data error of the decoded data is detected based on an error detection code included in the decoded data to be detected. When no error more than a predetermined level exists in the detection results, the decoded data is stored as normal decoded data.

Abstract: In order to carry out in a communication system (1) a temporal synchronization of clocks in a particularly rapid and efficient manner, a method is proposed which has the following steps: acquiring state values which are dependent on a time base (10); filing each acquired state value at a position in a first list L comprising (k+1) positions, if the acquired state value is smaller than or equal to the (k+1) smallest element of the list L, where k is a predefinable error tolerance; filing the acquired state value at a position in a second list H comprising (k+1) positions, if the acquired state value is greater than or equal to the (k+1) greatest element of the list H; forming a mean value from the (k+1) smallest element of the list L and the (k+1) greatest element of the list H, if the number of acquired state values is greater than or equal to (2k+2); determining a correction value as a function of the mean value; and correcting a current state value of the clocks that are to be synchronized.

Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.