Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.

Abstract: A method performed at a data storage device includes adjusting a first read voltage and a second read voltage to form sets of read voltages. First representations of data are read from a logical page in the non-volatile memory according to the sets of read voltages. The first representations of the data correspond to multiple values of the first read voltage and the second read voltage. The first representations of the data are stored in a memory and second representations of the data are generated based on the first representations. A value of the first read voltage is selected based on syndrome weights corresponding to the second representations.

Abstract: An image pickup device includes a pixel unit which generates pixel signals for image and pixel signals for focus detection, a first memory unit which stores the pixel signals for image, a second memory unit which stores the pixel signals for focus detection, a pixel signal synthesizing unit which synthesizes the pixel signals for image from a plurality of pixel signals, and an image signal outputting unit which outputs the pixel signals for image synthesized by the pixel signal synthesizing unit and the pixel signals for focus detection stored in the second memory.

Abstract: The present application includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Abstract: Methods and systems are provided for encoding and/or decoding data based on a constrained code and an error correction code (ECC). The data is encoded to generate combined LDPC-constrained codewords that may substantially satisfy both an ECC structure condition and a constrained code condition. A first plurality of sequences may be generated from input data to satisfy the constrained code condition. The first plurality of sequences may then be mapped to a second plurality of sequences that satisfies the ECC condition while preserving the constrained code condition.

Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.

Abstract: A digital broadcast communication system includes an upload system further comprising digital transceivers that upload a plurality of voice sources from any one of announcers, players, referees, coaches, and sportscasters from a broadcast booth utilizing a synchronized multicast communication protocol. At least one access point is configured to communicate with the digital transceivers using synchronized multicast communication protocol. The system utilizes error control coding and decoding that is based upon a quasi-orthogonal maximal sequence code.

Abstract: Systems and methods are provided for decoding data. A decoder includes a syndrome memory, a state memory, and decoding circuitry communicatively coupled to the syndrome memory and the state memory. The decoding circuitry retrieves data related to a symbol from the syndrome memory. The decoding circuitry also retrieves data related to the symbol from the state memory. The decoding circuitry processes the data retrieved from the syndrome memory and the data retrieved from the state memory to determine whether to toggle a value of the symbol. The determination is based at least in part on whether the symbol of the data being decoded was previously toggled from an original state.

Abstract: There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding.

Abstract: A plurality of encrypted packets having common payload data are received, wherein each of the plurality of encrypted packets includes a corresponding parity check field, and wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error. A payload portion of each of the plurality of encrypted packets is decrypted to generate a plurality of decrypted payload portions. At least one chase coding technique is used to generate a corrected decrypted payload, based on at least one candidate bit error position and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets.

Abstract: Circuitry and methods can be provided to correct errors in decision bits. A plurality of error event syndromes can be computed for a first plurality of error events. For each of a plurality of error event syndromes, two best error events can be selected. A cross-syndrome second best error event can be selected from among the first plurality of error events. A global second best error event can be selected from among the cross-syndrome second best error event and the second best per-syndrome error events. A second plurality of error events can be selected from among the global second best error event and the best per-syndrome error events. The second plurality of error events can be used for data post-processing.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power data decoders for use under defects, erasures, and puncturing, with a low density parity check (LDPC) encoder. Systems and methods are disclosed for decoding a vector with punctured, detected defect and/or erased bits. Systems and methods are also disclosed for decoding a vector with undetected defects and/or unknown error patterns. Low power decoding may be performed in an LDPC decoder during the process of decoding an LDPC code in the case of defects, erasures, and puncturing. The low power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes, or the devices that make use of low power LDPC decoders.

Abstract: The present invention is related to systems and methods for defect scanning.

Abstract: A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.

Abstract: A method for enhancing error correction capability of a controller of a memory device without need to increase a basic error correction bit count of an Error Correction Code (ECC) engine includes: according to an error correction magnification factor, respectively obtaining a plurality of portions of data, where the portions are partial data to be encoded/decoded; and regarding the portions that are the partial data to be encoded/decoded, respectively performing encoding/decoding corresponding to the error correction magnification factor, in order to generate encoded/decoded data corresponding to a predetermined error correction bit count, where a ratio of the predetermined error correction bit count to the basic error correction bit count is equal to the error correction magnification factor. An associated memory device and the controller thereof are further provided.

Abstract: An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

Abstract: A method for identifying a corrupted received signal that includes symbols is described. Each symbol may have a value of a Galois field associated therewith. The receiver may be configured to store a logarithm of normalized probability mass functions and corresponding Galois field values for each of the symbols. The normalized probability mass functions may be normalized with respect to a greatest probability mass function of a given symbol. The method may include comparing, for each symbol, a logarithm of normalized probability of an n-th best probability value with a respective threshold, counting a number of the logarithms that exceed the respective threshold and generating, for each symbol, a score corresponding to the number. The method may also include calculating a moving average of the scores, and comparing the moving average with an output threshold and flagging a just received symbol as corrupted based upon the comparison.

Abstract: There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding.

Abstract: A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits.

Abstract: An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal.

Abstract: Provided is a transmission device which improves the error rate characteristic upon decoding when performing error correction encoding by using a self-orthogonal code or an LDPC-CC in a communication system using a communication path having a fading fluctuation, multi-value modulation, or MIMO transmission. In the transmission device, the self-orthogonal encoding unit (110) encodes a self-orthogonal code having a constriction length K and an interleave unit (130) rearranges a code word sequence so that the same modulation symbol includes an information bit of a moment i and a non-correlated bit of the information bit of the moment i in a multi-value modulation unit (150).

Abstract: A method for generating a codeword that is insensitive to variations of a channel and easily extensible is provided. The method includes obtaining a primary unit by taking a row vector from an N(E(N?1) simplex code and mapping a control signal to the codeword. The simplex code is obtained by removing a first row from an N(ENorthogonal matrix. The codeword is obtained by combining a plurality of primary units.

Abstract: A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Abstract: Circuitry and methods can be provided to correct errors in decision bits. A plurality of error event syndromes can be computed for a first plurality of error events. For each of a plurality of error event syndromes, two best error events can be selected. A cross-syndrome second best error event can be selected from among the first plurality of error events. A global second best error event can be selected from among the cross-syndrome second best error event and the second best per-syndrome error events. A second plurality of error events can be selected from among the global second best error event and the best per-syndrome error events. The second plurality of error events can be used for data post-processing.

Abstract: An approximated lower-triangle structure for the parity-check matrix of low-density parity-check (LDPC) codes which allows linear-time-encoding complexity of the codes is disclosed, and the parity part of the parity-check matrix is semi-deterministic which allows high flexibility when designing the LDPC codes in order to provide higher error-correction capabilities than a typical dual-diagonal structure.

Abstract: A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

Abstract: A data processing method includes the steps of: initializing a syndrome vector to be an (n?1)th symbol; finding a corresponding mask based on the syndrome vector, wherein the mask is zero when the (n?1)th symbol is zero; correcting a known constant, which is zero when the syndrome vector is zero, based on the mask; inputting the syndrome vector to a log look-up table to correspondingly find log data; performing a modulo addition operation corresponding to log maximum data to find a log sum based on the log data and a log known constant; and inputting the log sum to an anti-log look-up table to correspondingly find operational data.

Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.

Abstract: A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have a first parallel data width. At least one of the syndromes is produced based on a corresponding at least one of the sets that has a second parallel data width that is less than the first parallel data width. The last syndrome of the sequence of syndromes corresponds to all of the data in the received sequence of sets.

Abstract: The present invention provides an LDPC encoder, a channel encoder of a portable internet system including the LDPC encoder, and an encoding method thereof. The LDPC encoder according to the present invention generates a Costas array, shifts it, generates an analogous circulation parity check matrix having a repeated pattern from the shifted Costas array, and performs encoding by using the parity check matrix. With this LDPC encoder, complexity of encoding system may be reduced.

Abstract: A pseudo-orthogonal code generator is provided. The pseudo-orthogonal code generator simplifies overall configuration and provides a more efficient operating speed by implementing a pseudo-orthogonal code generator using combined circuits instead of using a read only memory (ROM) circuit. The pseudo-orthogonal code generator reduces its overall size by reducing gate area.

Abstract: A transmitter for broadcasting an AM compatible digital audio broadcasting signal includes an analog modulator for producing an analog modulated carrier signal centrally positioned in a radio channel, wherein the analog modulated carrier signal is modulated by an analog signal, and a digital modulator for producing a plurality of digitally modulated subcarrier signals in the radio channel, wherein the digitally modulated subcarrier signals are modulated using complementary pattern-mapped trellis code modulation including a code mapped to overlapping partitions. In a first operating mode the analog modulated carrier signal and the plurality of digitally modulated subcarrier signals are in a 20 kHz channel and in a second operating mode the analog modulated carrier signal and the plurality of digitally modulated subcarrier signals are in a 30 kHz channel.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel characterized by intersymbol interference. Each of the one or more codewords incorporates one or encodes one or more parity bits. The codewords are processed by a Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Meta-Viterbi detector receives an output generated from a Viterbi detector having 2s states and processes the received output using a trellis diagram having 2t states.

Abstract: A method for correcting both erasures and errors of Reed-Solomon codes in a digital communication system is provided. The method comprises the steps of: calculating a syndrome; calculating a set of erasure locations; replacing errata evaluator polynomial by a function having a difference value; and replacing errata locator polynomial by a function having the difference value.

Abstract: Method of, and arrangement and device for, decoding a communications signal in a digital communications system, where the communications signal is modulated according to a modulation scheme including amplitude information; generating a likelihood value for a received communications signal, decoding the communications signal based on at least the generated likelihood value, providing a reliability indication of the amplitude information conveyed by the received communications signal wherein the step of generating the likelihood value further comprises generating the likelihood value on the basis of the provided reliability indication of the amplitude information.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: In an error detection method of the present invention, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arrangement are subjected to a first error detection code operation while correcting the inter-data continuity by skipping the data so that the arrangement of the code strings have continuity. Then, error data positions and error data numerical values of the target code strings are calculated on the basis of a syndrome obtained in the syndrome operation, and only the error data position among the target code strings are subjected to a second error detection code operation again on the basis of the error data positions and the error data numerical values.

Abstract: An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM transmitter and an OFDM receiver. The OFDM transmitter converts a digital signal to be transmitted to a plurality of sub-signals, each corresponding to a respective sub-carrier frequency. The signal is a packet including a preamble field having a known data pattern. The transmitter pre-codes the preamble data pattern, maps the data to corresponding phase information, converts the sub-signals to the time domain, and converts the sub-signals to analog form for subsequent transmission. The OFDM receiver receives the transmitted sub-signals, converts the sub-signals to digital form, converts the sub-signals to the frequency domain, and subjects the sub-signals to preamble detection processing to detect the signals' presence.

Abstract: Iterative decoder comprising a plurality of servers which perform the iterative decoding of a data block each, an input buffer memory and a control unit which performs a statistical multiplexing of the data at input, which are firstly stored in the input buffer memory and successively processed by one of the servers. The input buffer memory comprises N+L memory locations, where N is the number of servers and L is the number of so-called additional locations. Each block to be decoded which is received while all the servers are busy is stored in one of the L additional locations possibly available, or it is lost if the input buffer memory is entirely filled. The number L of additional locations and the number N of servers are such that the probability PB of a block being lost, calculated on the basis of a queuing model of D/G/N/N+L type, satisfies the condition PB??·FER*, where FER* is the error rate in the blocks allowed and ?<1; typically ? is of the order of 0.01.

Abstract: The present invention describes direct decoding of Error Correction Codes (ECC) such as, for example, FIRE and similar codes, and detecting and correcting errors occurring in burst, without requiring any pattern shift or sequential logic. According to the present invention, the syndrome of a code generated with a degree-d polynomial is split into sub-syndromes that are combined to form at least one kind of error pattern from which an error pattern is picked. If the picked error pattern does not correspond to an uncorrectable error and errors are not confined within first d bits, one of the sub-syndromes is selected according to the correction mode. The ranks of this selected sub-syndrome and picked error pattern in the Galois field generated by a factor of the degree-d polynomial are determined.

Abstract: An apparatus for branch metric computation and add-compare-select operation in a rate 1/n Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a measure between a currently received data symbol and a corresponding branch label. The add-compare-select unit can generate respective decision bits for a pair of odd and even states at next instant with a novel pre-computational architecture. Further, a local winner between the odd and even states is predetermined in a manner providing reduction of the activity required by the computation. Thus the add-compare-select unit outputs a path metric of the local winner, whereby a saving of half the output number of path metrics is achieved.

Abstract: The exclusive OR (XOR) of user data (sector) 0, user data (sector) 1 and user data (sector) 2 is taken to have the virtual user data, thereby giving rise to a correlation of the sectors 0 to 2, and its virtual user data is appended with C2 having a greater error correction capability than C1, whereby an error uncorrectable with C1 is correctable with C2.

Abstract: A phase synchronizer may operate, for example, to establish synchronization with a phase of a received codeword. The phase synchronizer may include, for example, an input shift register, a first syndrome computing module, a first error detection module, a second syndrome computing module, a second error detection module and a comparator arrangement. The first syndrome computing module may compute syndromes relating to a first potential phase of the codeword. The first error detection module may determine, based upon the first syndromes, a first number of errors associated with the first potential phase of the codeword. The second syndrome computing module may compute syndromes relating to a second potential phase of the codeword. The second error detection module may determine, based upon the second syndromes, a second number of errors associated with the second potential phase of the codeword.

Abstract: The present invention provides a decoding system and method for an optical disk storage device to receive and decode the data of the disk. The present invention does not need to increase the clock frequency and the bus width of the decoding system, it can effectively decrease the access times to the data buffer and the system response time by changing the structure of the conventional decoding system, in this way the present invention increases the parallel processing capability and the decoding speed of the system, thus, it can enhance the entire device to become a high speed optical storage device.

Abstract: A method, device, and computer program to generate operation codes having a maximum hamming distance between them. Utilizing these operation codes it is possible to detect errors immediately upon receipt of a first byte of data in a packet to allow the receiver to immediately act on the received data. This reduces the need for buffer space on both the transmitting and receiving devices. Further, this method reduces the latency for the receiver acting on the incoming data.

Abstract: A self orthogonal decoding circuit and a method thereof, can be realized with simple circuit construction and can significantly improve error correction performance. The self orthogonal decoding circuit performing decoding for self orthogonal code repeats decoding for the self orthogonal code for a plurality of times.