Abstract: Method and apparatus for communication in an Integrated Access and Backhaul (IAB) system with buffer status report (BSR) are disclosed. The apparatus include a receiver that receives a BSR indicating that data is expected to be received; a processor that calculates a first type of buffer size based on the received BSR indicating that data is expected to be received and/or a second type of buffer size based on data presently stored in a buffer; and a transmitter that transmits a buffer status comprising the first type of buffer size and/or the second type of buffer size.

Abstract: Devices, methods, and systems for hands free facility status alerts are described herein. One system includes a computing device for hands free building automation notifications, comprising a memory and a processor to execute executable instructions stored in the memory to: receive a notification of an event from a building automation system, modify the notification to include only pre-defined attributes of the notification that are displayable on a user interface of a wearable device, and transmit the modified notification to the wearable device.

Abstract: Devices, systems, and methods for maintenance prediction for devices of a fire system are described herein. In some examples, one or more embodiments include a computing device comprising a memory and a processor to execute instructions stored in the memory to receive fire system device data of a fire device in a fire system and generate a fire device analysis based on the fire system device data, where the fire device analysis includes a predicted behavior of the fire device and a predicted timeline for the predicted behavior of the fire device.

Abstract: A method for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error correcting code (ECC) as first encoded data, wherein the ECC is configured to have a minimum Hamming distance of at least 4t+1 in order to correct up to t bit errors and detect up to 3t bit errors where t?1; determining a Hamming weight of the first encoded data; encoding the determined Hamming weight, wherein for all higher Hamming weights the encoding should have at least 2t+1 bit-positions that change from 1 to 0 per Hamming weight; concatenating the first encoded data and the encoded Hamming weight as concatenated data; and storing the concatenated data in the memory.

Abstract: Encoding and decoding devices, methods and programs are disclosed. In one example, decoding is provided by dividing input data into data strings of N bits, the data strings including a first data string, calculating a running disparity for the data strings, determining whether the first data string is to be inverted based upon the calculated running disparity, setting a flag for the first data string to a first value when it is determined that the first data string is not to be inverted, and setting the flag for the first data string to a second value and inverting the first data string when it is determined that the first data string is to be inverted, and outputting the first data string. The technology is, for example, applicable to a device communicating in an SLVS-EC specification.

Abstract: Devices, methods, and systems for hands free facility status alerts are described herein. One system includes a computing device for hands free building automation notifications, comprising a memory and a processor to execute executable instructions stored in the memory to: receive a notification of an event from a building automation system, modify the notification to include only pre-defined attributes of the notification that are displayable on a user interface of a wearable device, and transmit the modified notification to the wearable device.

Abstract: Various embodiments relate to a method and system for encoding data to be stored in a memory, including: encoding the data to be stored in memory with an error detection code (EDC), that can detect up to 4 bit errors, as first encoded data; determining the Hamming weight of the first encoded data; inverting the determined Hamming weight; concatenating the first encoded data and three copies of the inverted Hamming weight as concatenated data; encoding the concatenated data with an error correcting code (ECC), that can correct 1 bit error, as second encoded data; and storing the second encoded data in the memory.

Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Abstract: A method of processing customer feedback is provided. The method comprises, associating a plurality of short codes to a plurality of portable electronic devices, each different short code associated with at least one different feedback value, wherein the short codes comprise a first short code and a second short code, and receiving a plurality of messages from a first sub-set of the portable electronic devices addressed to the first short code. The method further comprises receiving a plurality of message from a second sub-set of portable electronic devices addressed to the second short code. The method further comprises automatically analyzing the messages based on the first short code and the second short code. The method further comprises allocating customer care resources to respond to the messages based on the analysis.

Abstract: Provided is a signal quality evaluation apparatus, including an error pattern detection unit to which binarized data obtained by performing a PRML decoding process on a reproduced signal of bit information by partial response equalization and maximum likelihood decoding is input, the error pattern detection unit configured to detect at least one specific error pattern that is a bit pattern that is longer than a constraint length of the PRML decoding process, a metric difference calculation unit configured to calculate a metric difference of the at least one specific error pattern that has been detected by the error pattern detection unit, and an index value generation unit configured to generate an index value of a reproduced signal quality by using a distribution of the metric difference obtained by the metric difference calculation unit.

Abstract: A system and method is disclosed to estimate both, the time and number of resources required to execute a test suite or a subset of test suite in parallel, with the objective of providing a balanced workload distribution. The present invention partitions test suite for parallelization, given the dependencies that exists between test cases and test execution time.

Abstract: Techniques for reconfiguring an integrated circuit (IC) are provided. The techniques may improve error detection in the partially reconfigurable IC. A cyclic redundancy check (CRC) value for a first configuration data is received by the IC and a second configuration data is generated based on the first configuration data and a prior configuration data stored in the IC. The first configuration data may be a partial reconfiguration data that is used to reconfigure at least a portion of the IC. A third configuration data is then generated based on the first and second configuration data and the prior configuration data. A second CRC value is calculated based on the third configuration data. The second CRC value, together with the first CRC value and a prior CRC value stored in the IC, is used to calculate an updated CRC value. The updated CRC value is stored in the IC.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: A method and apparatus for handling fuzziness in sensitive keywords from data loss prevention (DLP) policies. In one embodiment, the method includes identifying a keyword included in a DLP policy, generating multiple permutations of the keyword, and adding the multiple permutations to the DLP policy. The method further includes causing information content to be searched for the keyword permutations to detect a violation of the DLP policy in the information content.

Abstract: A method for configuring a biometric template protected authentication system wherein the desired classification threshold is first selected to optimize the trade-off between a false accept (FAR) and a false non match or reject rate (FRR) of the system, and then an error correcting code (ECC) used in the authentication process is chosen such that the number of errors which can be corrected is equal to or greater than the selected classification threshold. During authentication, the number of errors in a first codeword derived from biometric data associated with a physical object is determined and used in the decision process to accept or reject authentication.

Abstract: A method of communicating a bitstream having a characteristic Hamming weight to a destination via a channel comprises determining the characteristic Hamming weight of the bitstream, inverting each bit in the bitstream if the characteristic Hamming weight of the bitstream is below a threshold value and developing an indication of whether the bits in the bitstream are inverted, delivering the bitstream and the indication of whether the bits in the bitstream are inverted to the destination via the channel, and inverting each bit in the bitstream at the destination if the indication indicates that the bits are inverted.

Abstract: A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

Abstract: A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.

Abstract: Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.

Abstract: A system and method for MIMO communications is provided. A method includes receiving a data block of P matrices from a transmitter, and determining if operating conditions are met. The method also includes if operating conditions are not met, computing a test position, selecting a codeword based on the test position, and computing a metric. The metric may then be compared with an error radius to determine a validity of the codeword. If the codeword is invalid, another codeword is selected. If the codeword is valid, then the codeword is stored if all matrices have been evaluated, else another matrix is selected for evaluation. If matrices earlier in the data block have untested codewords while all codewords for a matrix being evaluated have been tested, backtracking may be performed. After the codewords for the data block have been found, the stored data may be outputted and processed.

Abstract: A method and apparatus for handling fuzziness in sensitive keywords from data loss prevention (DLP) policies. In one embodiment, the method includes identifying a keyword included in a DLP policy, generating multiple permutations of the keyword, and adding the multiple permutations to the DLP policy. The method further includes causing information content to be searched for the keyword permutations to detect a violation of the DLP policy in the information content.

Abstract: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

Abstract: A data dependent descrambler for a communications channel that receives a scrambling seed and a scrambled user data sequence with N symbols each with M bits comprises a first decoder that analyzes adjacent symbols of the scrambled user data sequence, that performs G-constraint decoding on the adjacent symbols when a first of the adjacent symbols is an all-one symbol and that does not perform G-constraint encoding when the first of the adjacent symbols is not an all-one symbol. A first descrambler communicates with the first decoder and generates a user data sequence based on the scrambled user data sequence and the scrambling seed.

Abstract: A Post-Viterbi processor generates a plurality of candidate codewords based on a plurality of dominant error patterns for a particular communication channel. The Post-Viterbi processor selects one among the candidate codewords as a corrected codeword upon determining that the candidate codeword is error free.

Abstract: Proposed is a user cooperative terminal device. The user cooperative device includes: a signal detector to receive a signal transmitted from a source node and detect a received signal; and a message generator to cancel interference caused by a neighboring user in the received signal, using a neighboring user message, and to generate a user message. The neighboring user may decode a received signal of the neighboring user to transfer the neighboring user message.

Abstract: A communication decoding method comprises receiving processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted and inverting each bit of the binary code word if the indication indicates that the bits are inverted.

Abstract: A method comprises obtaining a first sequence of binary digits that collectively have a characteristic Hamming weight, inverting each of the binary digits in the first sequence of binary digits if the Hamming weight of the first sequence of binary digits is below a predetermined threshold Hamming weight value, and providing an indication of whether the binary digits in the first sequence of binary digits have been inverted.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

Abstract: In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.

Abstract: Systems and methodologies are described that facilitate utilizing timers in conjunction with transmitting buffer status reports (BSR). A prohibit timer can be utilized to determine when BSRs can be transmitted to an eNB. The prohibit timer can be initialized or restarted upon transmitting a BSR to an eNB. A BSR retransmit timer can be used to determine when to retransmit a BSR. The BSR retransmit timer can be initialized upon transmitting a BSR to an eNB and restarted each time an uplink resource allocation is received from the eNB. Once the timer expires, if an uplink transmission buffer contains data (e.g., size>0), the BSR can be retransmitted to the eNB. Control data feedback can additionally be used to determine when to retransmit the BSR. In addition, in either case, the timer duration values can be provided by the eNB.

Abstract: When configuring a network system (10) in a user's residence, a patient to receive home healthcare assistance or other user receives an encoded configuration message. One type of configuration message includes a sequence of code words, each of which corresponds to one or more numerical digits, which the user receives via voice or text message on a mobile phone (28), as an email message, etc., and the user enters the codewords into a set top box (STB) (12). The user enters the codewords by selecting the codewords and/or images representing the codewords displayed on a GUI (18). The STB (12) uses a translation table (40, 42) to decode the codewords to determine the numerical sequences. The complete sequence represents a configuration information sequence, such as a user ID, an IP address, or the like, and is employed by the STB (12) to configure itself and/or other components in the network system (10).

Abstract: When a plurality of data blocks are divided into a plurality of frames and the divided frames are transmitted, every time a frame is received, a interim calculation result of a check code is updated using a transitional calculation result of the check code of the data block corresponding to the frame received and the data included in the frame. When a final calculation result of the check code of a data block is obtained, the calculation result is compared with the check code included in the data block.

Abstract: A method and an apparatus for encoding and decoding a modulation code are provided. The method includes: adding an error detection bit(s) to source information; performing k-constraint coding by inserting an error pattern that can be detected using an error detection code into a data stream that violates a k-constraint for a run length limited (RLL) code in a data stream comprising the error detection bit(s) and the source information, and recording the data stream after being k-constraint coded onto a recording medium; and reading the data stream recorded onto the recording medium and determining whether an error is present in the data stream.

Abstract: A method and a circuit of automatic control of the execution of a program by a microprocessor, including: assigning a digital decrement or increment to at least one function of the program; assigning a digital increment, respectively decrement, to at least one section considered as critical as to the program execution and called by the function; setting a counter to a first value; decrementing, respectively incrementing, the counter once per function before a call to a critical section; incrementing, respectively decrementing, the counter on each correct execution of a section; and comparing the current value of the counter with a predetermined critical threshold.

Abstract: A data-recording/reproducing apparatus and method, that determine a reproduction position with high degree of reliability for data recorded on an information-recording medium even after the data is edited. From a process to edit an AV stream file, a DV data recording/reproducing apparatus splits a DVF-sequence into sequences including consecutive frames. When data is deleted in sector units in the edit process, pieces of data included in deleted frames are left at the beginning and end of each of the sequences. The DV data recording/reproducing apparatus records data representing the length of the data left at the head and the end of the sequences, data representing a frame number assigned to a frame located at the head of the sequences, and data representing the number of frames included in the sequences, on a disc used as the information-recording medium, for example an optical disc.

Abstract: A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract: Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.

Abstract: A demodulator performs bit recovery in an asymmetric data channel, such as an optical recording media, by detecting runlength violations prior to demodulation, and correcting the detected runlength violations prior to the demodulation.

Abstract: An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and zeros are easily suppressed by detecting a prohibited length of ones or zeros, and flipping a bit in the string of ones or zeros. This method and system removes the violation of the ones or zeros bit string requirement by flipping a bit in the string, while the receiving side utilizes the error correction capability of the ECC/FEC to correct the inverted bit.

Abstract: An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Abstract: A Hamming weight encoder includes an input that receives user data including P symbols and a Hamming weight module that determines a Hamming weight of N of said P symbols. N and P are integers greater than one and N is less than or equal to P. The Hamming weight encoder also includes a comparing module that compares the Hamming weight to a Hamming weight threshold and an inverting module that selectively bitwise inverts bits in said N symbols based on said comparison.