Abstract: A memory device including a memory array comprising a plurality of memory cells, respective memory cells each comprising a storage element comprising phase change memory programmable to three unique states; and a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.

Abstract: The present invention is related to systems and methods for data storage compression. As an example, a system is discussed that includes a semiconductor device having a host interface, a compression circuit operable to compress a write data set received via the host interface, and a write channel circuit operable to apply an encoding algorithm to the compressed data set to yield an encoded data set.

Abstract: Systems and methods relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. As an example, a method is discussed that includes: applying a first level encoding on a section by section basis to a first data portion to yield a first encoding data including a first encoded portion; applying a second level encoding on a section by section basis to the first encoded portion to yield a first parity set; applying a third level encoding on a section by section basis to a combination of the first data portion, the second data portion, and a portion derived from the first encoded portion to yield a second encoding data.

Abstract: A low density parity check decoder includes a decoding process divided into two or more processing stages arranged in series. At one time, each processing stage processes a different code block than each other processing stage in the series. The decoder is capable of simultaneously decoding as many code blocks as stages. A controller passes the code blocks between the processing stages at the proper time and in the proper sequence. The controller passes the code blocks through the series of stages in a time-division multiplexed fashion.

Abstract: Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system.

Abstract: Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.

Abstract: The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

Abstract: Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for probability-based multi-level LDPC decoding. For example, in one embodiment an apparatus includes a horizontal updater in a low density parity check decoder operable to iteratively perform row processing to update probabilities of multi-level symbol values, a vertical updater in the low density parity check decoder operable to iteratively perform column processing to update the probabilities of the multi-level symbol values, and a check sum calculation circuit operable to calculate total soft values for the multi-level symbol values.

Abstract: Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

Abstract: A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit determines, for the plurality of encoders, respective times for the encoders to receive a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders according to the determined times for use in respective encoding operations.

Abstract: Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented.

Abstract: A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit receives, from the plurality of encoders, respective requests for a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders at staggered times for use in respective encoding operations.

Abstract: A communication system that performs encoding and decoding for communication includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a turbo encoding unit including a first encoding unit that encodes an input signal and generates a first parity bit by bit-based encoding and n (n=1, 2, 3, . . . ) second encoding units that encode the input signal and generate second parity bits by bit-based encoding, and a symbol mapping unit that maps an output from the turbo encoding unit to a symbol by bit-based mapping operation and modulates the output. And the receiving apparatus includes a demodulating unit that demodulates a transmission signal, and a turbo decoding unit that performs turbo decoding on the demodulated signal by bit-based decoding.

Abstract: A system and method for encoding symbols in a wireless communication is provided. The system and method includes a transmitter configured to encode data transmissions. The transmitter includes a raptor encoder configured to perform a coding operation. The raptor encoder generates intermediate symbols without using a half-code such that the intermediate symbols consist of precoded symbols and parity symbols. Thereafter, the intermediate symbols are encoded using a Luby Transform to produce and output encoded symbols. The transmitter further is configured to transmit one or more of the source symbols, parity symbols or encoded symbols.

Abstract: Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number.

Abstract: A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Abstract: A method of transmitting data that includes controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks; and performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: A transmitting apparatus, that includes a means for generating bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data in a first encoding process, to be equal or closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data in a second encoding process, in regard to first bit positions of the bit sequences generated using bits included in the first and second data blocks and a modulator for performing multi-level modulation for transmission based on the generated bit sequences.

Abstract: A receiver for use in performing open loop MIMO performs parallel interference cancellation to reduce interference caused by other spatial streams. Residual interference within an interference-cancelled signal is mitigated using MMSE filtering. The receiver processes received signals in multiple iterations. On each successive iteration, an MMSE filter assumes a lower interference power level than a previous iteration.

Abstract: A data dependent descrambler for a communications channel that receives a scrambling seed and a scrambled user data sequence with N symbols each with M bits comprises a first decoder that analyzes adjacent symbols of the scrambled user data sequence, that performs G-constraint decoding on the adjacent symbols when a first of the adjacent symbols is an all-one symbol and that does not perform G-constraint encoding when the first of the adjacent symbols is not an all-one symbol. A first descrambler communicates with the first decoder and generates a user data sequence based on the scrambled user data sequence and the scrambling seed.

Abstract: A system and method for navigating a multi-hierarchical menu system using a two-dimensional controller, comprising displaying an Nth level of the multi-hierarchical menu system having a plurality of icons in proximity to a pointer on a portion of a display, scrolling the icons in a first dimension relative to the pointer responsive to operating the controller in the first dimension, and one of either selecting one of the icons in closest proximity to the pointer responsive to operating the controller in a first direction of a second dimension, or displaying a N+1th level of the multi-hierarchical menu system relative to one of the icons in closest proximity to the pointer responsive to operating the controller in an opposite direction of the second dimension.

Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract: Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media.

Abstract: The invention relates to a method for improving the performance of data transmissions over a communications channel, wherein data is coded and modulated for transmission, wherein coding the data results in differently coded bits. In order to allow for a simple way of a more flexible coding, it is proposed that the differently coded bits are mapped for modulation to different modulation symbols of a symbol alphabet, to which modulation symbols different relative reliabilities are assigned, and wherein by mapping the coded bits to the modulated symbols, different reliabilities are associated to differently coded bits depending on the conditions on the communications channel. The invention equally relates to a corresponding communications system and to elements of such a communications system.

Abstract: Mapping of m input bits to 2m modulation symbols of a two-dimensional symbol constellation. A quarter-quadrant constellation of 2m-4 modulation symbols that are located in a first quadrant of the two-dimensional signal plane is formed with each modulation symbol associated with a respective m-4 bit label. A quarter constellation of the two-dimensional symbol constellation is formed by adding to the quarter-quadrant constellation three copies of the quarter-quadrant constellation rotated by ?90 degrees, 180 degrees, and ?270 degrees, respectively, and then displacing the quarter constellation by a shift value ?, with each modulation symbol associated with a respective m-2 bit label. The two-dimensional symbol constellation is then formed by adding to the quarter constellation three copies of the quarter constellation rotated by +90 degrees, 180 degrees, and +270 degrees, respectively. Each symbol of the two dimensional constellation is associated with a respective m bit label of the m input bits.

Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.

Abstract: Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the property that in a relatively simply decoding scheme such as mean square error (MSE) or zero-forcing (ZF) only a small portion of the total symbols are mis-detected. Therefore, an optimality test is performed on the output of a relatively low complexity decoder unit. If the symbol passes the optimality test, it is presumed to be correctly decoded. Otherwise, the symbol is sent for further processing to a relatively higher complexity decoding unit such as a sphere decoder. In this way, processing efficiency is increased, because only those symbols requiring additional processing are processed by the high complexity processing unit.

Abstract: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying the initial symbol erasure threshold using the initial symbol erasure margin to produce a modified symbol erasure threshold. By then periodically modifying the modified symbol erasure threshold adaptive via updating the symbol erasure threshold and/or symbol erasure margin based on various error quantities, the technique can compensate for time-variant considerations, such as drifting noise levels.

Abstract: A communication system includes a lattice interfered channel to transmit data from a transmitter to a receiver. In one embodiment, an encoding-modulation scheme having a rich signal constellation is used to encode data at a total rate of 0.7 bit/dimension or less before transmission into the lattice interfered channel. In another embodiment, decoding metric approximation techniques are used to process signals received from the lattice interfered channel. In still another embodiment, multilevel code (MLC) decoding is used to jointly decode an error correction code component and a lattice/MLC component of a received signal. The error correction code component may then be extracted from the decoded signal.

Abstract: Some embodiments of the present invention include a decoding system in which the decoding system uses iterative decoding techniques to decode signals encoded with lattice codes and/or multilevel coset codes. The decoding techniciucs according to some embodiments of the invention may be less complex than some decoding techniciues such as maximum likelihood decoding techniciues. Other embodiments of the prevent invention are described and claims.

Abstract: Disclosed is a method for providing first and second interleaved bit streams to a modulator in order to transmit the first and second interleaved bit streams through at least two antennas in a mobile communication system. An encoder encodes a transmission data stream into a first bit stream with first priority and a second bit stream with second priority being lower than the first priority. An interleaver interleaves the first and second bit streams into the first and second interleaved bit streams. The modulator modulates the first and second interleaved bit streams.

Abstract: A method for efficient decoding of block product code format signals, using a (22p)QAM signal constellation for mapping of a received signal, with p=2, 3, 4, 5, . . . A received signal value rx, corresponding to an x=I or x=Q coordinate, is converted to a p-tuple (B(p-1)x, . . . , B0x) corresponding to a “closest” I-coordinate or Q-coordinate numerical value, and a p-stage algorithm is applied to the signal values rx and to the p-tuples (B(p-1)x, . . . , B0x) to determine a p-tuple (r(p-1)x, . . . , r0x) representing a decoded p-bit value for the received signal value rx. Depending upon a communication channel parameter Eb/N0 and the bit error ratio BER associated with each of the p bits, the received signal values rx may be suitable for some or all communications activities (e.g., HDTV, SDTV, mobile comm).

Abstract: The invention is a method and apparatus for compression of binary data. The signal is used before modulation to increase the effective transmission rate by compressing it prior to being encoded onto a magnetic tape or other storage media. The transition bits of the data have a bit period no smaller than the smallest bit period without increasing the maximum frequency. However, non-transition bits have a bit period smaller than that of the transitioning bits. Since there is at least one full bit period between any two transitions, the maximum frequency is unaffected and is used for synchronization. Noise in a transmission is masked using bit period information, and since no other transition can be valid until at least the transition bit period has passed, noise occurring before passage of the transition bit period does not result in an error.

Abstract: A modulator, and an associated method, are described for use by a sending station, operable in a communication system, to communicate data to a receiving station upon a communication channel susceptible to fading. The modulator includes a mapper for mapping modulator output symbols to a set of antennas. The modulator ensures that an Orthogonality Condition is satisfied to impart maximum transmission diversity upon the data sent over the fading communication channel.

Abstract: An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.

Abstract: The invention relates to a method for encoding a stream of bits of a signal relating to a binary source into a stream of bits of a signal relating to a binary channel, the binary source comprising a main source and a secondary source, the main source being encoded in a main channel by multi-level coding and the secondary source being encoded in a secondary channel, the secondary channel being embedded in the main channel in order to form the binary channel, wherein the secondary channel is divided in at least a first section comprising user data and a second section comprising non user data.