Abstract: The present application relates to an interconnect system for transmitting a stream of N-symbol data signals, which comprises a parallel data signal line bus, a line scrambler, a line de-scrambler and a defect detector. The defect detector is configured to detect one or more defective data signal lines. The line scrambler 110 is configured to accept an N-symbol data signal d having a sequence of data symbols in a predefined order and to output a permuted sequence d? of data symbols at its N output terminals oj. The line de-scrambler is configured to accept the permuted sequence d? of data symbols at its input terminal i?j, to restore the predefined order of the data symbols from the permuted sequence d? of data symbols; and to output the restored N-symbol data signal d comprising a sequence of data symbols in the predefined order.

Abstract: The present application relates to an interconnect system comprising a video signal transmitter and video signal receiver for transmitting a stream of N-symbol data signals over an error prone wired parallel bus having at least N data signal lines. A line scrambler at the video signal transmitter is configured to accept an N-symbol data signal having a sequence of data symbols in a predefined order and to output a permuted sequence of data symbols in accordance with a permutation. The line de-scrambler at the video signal receiver is configured to accept the permuted sequence of data symbols at its input terminal and to restore the predefined order of data symbols from the permuted sequence of data symbols in accordance with the corresponding reverse permutation.

Abstract: A method for enhancing signal integrity in an interface between a source device and at least one destination device includes: analyzing two or more consecutive data patterns intended to be conveyed by the interface to determine whether data transitions corresponding to the data patterns are likely to introduce coupling noise and/or simultaneous switching output (SSO) effects on the interface; generating a modified data pattern for transmission by the interface, the modified data pattern reducing coupling noise and/or SSO effects on the interface compared to an original data pattern intended to be conveyed by the interface; and transmitting the modified data pattern and information regarding a manner in which the original data pattern was modified to the destination device to thereby reduce coupling noise and/or SSO effects on the interface.

Abstract: In an error correction device, a frame generation section receives pulse signals as temperature information of a power switching element transmitted from a PWM comparator. The frame generation section sets a first correction pulse signal, a second correction pulse signal and the temperature information sequentially into each frame. A pulse width of the first correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 100%. A pulse width of the second correction pulse signal corresponds to a pulse width when a time ratio thereof becomes 50%. A microcomputer receives the temperature information through a photocoupler and corrects the received temperature information. The microcomputer calculates a temperature detection value of the power switching element on the basis of the corrected temperature information.

Abstract: Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.

Abstract: In a data transmission network, such as a passive optical network, the consecutive identical digit (CID) handling requirements may be reduced by providing a CID monitoring module at the transmitter end that monitors the number of CIDs in a transmission stream. Where the CID number exceeds a threshold, an error generation module induces an error in the transmission stream to reduce the CID below the threshold. The modified transmission stream may then be transmitted to a receiver, allowing clock recovery be performed with improved stability at the receiver. Once clock recovery is achieved, the receiver can then process the transmission stream to correct the errors induced at the transmitter end.

Abstract: Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.

Abstract: Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.

Abstract: A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition. Selection circuitry is programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.

Abstract: A method for correcting data signal errors in a meter has been developed. The method includes receiving ordered data signals from the meter. Next, the sequenced of ordered data signals is analyzed to determine whether a data signal is missing. Finally, if a data signal is missing, a predetermined value is added to a sequence counter to compensate for the missing signal.

Abstract: The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block 201 is utilized in tandem with directly accessible fully configurable memory block 207. Arbiter 206 implements the redundant addressing that enables the multiple write cycle NVM functionality. Each block of less configurable memory contains an address segment 203 and a data segment 204. Address segment 203 refers to a specific cell in directly accessible memory 209.

Abstract: An integrated circuit 2 including functional circuits 4, 6 and a diagnostic circuit 10 passes a functional signal and a diagnostic signal to/from the integrated circuit using a shared integrated circuit pin 14. The functional signal and the diagnostic signal have relative forms such that they can be simultaneously communicated and respective independent physical communication channels provided therefore. Examples are the diagnostic signal being used to frequency, phase, amplitude or otherwise modulate a functional signal being passed. A diagnostic interface circuit 18 is provided to recover the diagnostic signal from the combined functional and diagnostic signal or to combine the functional and diagnostic signals.

Abstract: In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined voltage to produce analysis data, and capturing the analysis data at a respective time data point of a plurality of time data points. The method may be implemented as part of integrated circuits, electronic assemblies, or systems.

Abstract: A cable line quality evaluating method for evaluating a quality of a cable line for transmitting a digital modulation signal in a bidirectional manner comprises the steps of extracting a noise signal of an upstream line from one of a cable line connection point for evaluating a head end of the cable line evaluated in the quantity and the cable line evaluated in the quantity and a connection point between a tap-off and the cable line evaluated in the quality, generating a pseudo random signal, modulating a carrier signal of its predetermined frequency by means of the pseudo random signal, and then outputting the modulated signal as a test carrier, outputting an output signal obtained by adding the noise signal of the upstream line and the test carrier, selectively receiving the signal of its predetermined frequency from the output signal, and modulating the selectively received signal, and comparing the modulated signal with the pseudo random signal in bits, and then measuring a bit error rate.

Abstract: A system and method for correcting interference errors in data encoded on storage media comprising position marks disposed on a storage medium, the position marks being configured to encode a plurality of track addresses and at least four track types. A correction module detects and corrects errors in the track addresses by combining each of the track addresses with one of the track types and then recognizing incorrect addresses. The correction module replaces incorrect addresses with correct addresses using a look-up table, wherein each incorrect address is not identical to one of the correct addresses. The plurality of position marks that encode the track types are also used to generate a position error signal for position correction of a head device.

Abstract: An error correction and detection system for a dual-pulse output metering device is provided. The system detects errors in the dual-pulse output of the metering device by comparing the current phase difference it between the pulse streams to a desired or known phase difference and generating an error signal if the current phase difference is different from the desired phase difference. If an error signal is generated, the system additionally accounts for the error and provides a corrected pulse count output by either discarding the extra pulse, or calculating the number of missed pulses, and adding the missing number of pulses to the pulse count output.

Abstract: A system and method for demultiplexing and distributing transport packets, such as MPEG-2 transport packets, by generating and associating a locally-generated header with each of the transport packets to create a self-contained modified packet which incorporates essential distribution information therein. The method for enhancing transport packet demultiplexing and distribution in a digital transport demultiplexing system that inputs a stream of digital multimedia transport packets is provided. Each of the transport packets includes a packet identifier (PID) to identify the digital program or elementary stream to which it corresponds. Local packet information is generated for each of the transport packets, which is used in identifying and distributing the transport packets. A local header is created that includes the generated local packet information, and the local header is linked to its corresponding transport packet to create a modified transport packet.

Abstract: A system and method of controlling an electronic price label (EPL) through infra-red signals instead of push-button signals. The system includes a computer which transmits wireless radio frequency messages containing functions codes and instructions, and a portable terminal which emits infra-red signals containing at least one of the function codes. The EPL receives the radio frequency messages, stores the function codes and corresponding instructions in a memory within the EPL, receives the infra-red signals from the portable terminal, determines the instructions associated with the function codes received from the portable terminal, and executes the determined instructions.

Abstract: An unsafe detection circuit for detecting a kickback signal including an input circuit for inputting a kickback signal, a circuit for detecting the presence or absence of said kickback signal, and a fault detection circuit to respond to said presence or absence of said kickback signal to provide an indication of a fault.

Abstract: A method of detecting the loss-of-signal condition at the input of a transmission line interface when the input signal is coded. The input signal decoding includes an additional procedure allowing the detection of loss-of-signal condition. Since the pseudo-random sequence of the input signal transitions includes sequences of code violations, the additional procedure, over a certain threshold error rate, corresponding to a number of code violations in a unit of time, detects the loss-of-signal condition.

Abstract: A command generator having a single-input multi-out converter is provided. The command generator in a memory device comprises a converter for receiving first and second control signals from external circuit and an input signal having a plurality of pulses to generate binary data denoting a command. The converter comprises an input buffer, in response to the first and the second control signals, for receiving the input signal having a plurality of pulses and outputting an output signal having a number of pulses within a predetermined period; and a pulse counter for counting the number of pulses in the output signal to generate binary data representing the counted number. The command generator counts the number of pulses of a input signal through a pad, that is, performs built-in self-test of the product, thereby product cost can be considerably reduced because of reduction of test time.

Abstract: A data signal peak error detector for monitoring and detecting undesired shifts in the peak levels of a multilevel data signal, such as an MLT3 Ethernet signal. A signal slicing circuit generates two signals: a data peak detection signal identifies occurrences of data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding intermediate and peak (e.g., positive or negative) signal levels; and a data peak error signal identifies occurrences of data signal peak errors and is asserted when the input data signal level has transitioned beyond a value which corresponds to a preceding peak signal level. Assertion of the data peak detection signal initiates a count sequence by a counter. The count sequence is decoded to produce one or more signal pulses, each of which is provided at a respective time after assertion of the first data peak signal and identifies a valid state of the data peak error signal.

Abstract: A remote control device and method for electronic price label (EPL) systems which includes circuitry from EPLs. The remote control device includes a first EPL circuit, a second EPL circuit, and a control circuit coupled between the first and second EPL circuits for enabling transmission of alternating signals to the EPL computer by the first and second EPL circuits. The EPL computer executes a function in response to the alternating signals.

Abstract: A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal.