Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: The present disclosure discloses a display driving device and a display device including the same, which allow transmission data to be converted into a completely random code sequence. The display device may scramble transmission data into a pseudo-random binary sequence (PRBS) using a linear feedback shift register (LFSR), and may change a seed value of the LFSR every time the scrambling is performed.

Abstract: A system and method for dynamic software analysis operable to describe program behavior via instrumentation of virtualization events.

Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.

Abstract: A gesture controlled calculator has a touch screen controlled by a microprocessor. The touch screen receives a multiplication problem input by a user through a virtual keyboard. After the problem is entered, the calculator breaks up the problem into easy multiplication problems and then very easy multiplication problems in response to touch gestures by the user. The very easy multiplication problems are then presented on the graphical user interface of the touch screen as columns of virtual digits cards. The virtual digit cards are added together in response to touch gestures by the user. The solutions to the very easy multiplication problems are then presented as columns of digit cards. These digit cards are then added together in response to touch gestures by the user. The solution to the multiplication problem is then presented in the graphical user interface.

Abstract: A visual prosthesis apparatus and a method for providing artificial vision are disclosed in the present disclosure. The visual prosthesis apparatus comprises a camera for capturing a video image, a video processing unit configured to convert the video image to stimulation patterns, and a retinal stimulation system configured stimulate neural tissue in a subjects eye based on the stimulation patterns. An artificial vision may be provided by capturing a video image, converting the video image to stimulation patterns, and stimulating neural tissue in a subjects eye based on the stimulation patterns.

Abstract: A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.

Abstract: Systems, methods, and apparatuses are disclosed for choosing the modulation mode using packets transmitted by a sender to a receiver, wherein the packets contain data patterns unknown to the receiver. In some embodiments, the sender sends of a data packet in the most robust mode available, such that the packet can be correctly received by the receiver under even the noisiest conditions. The data contained in the packet is demodulated and decoded. A cyclic redundancy check is performed to ensure that the resultant data is error-free. Once the transmitted payload data is known, the original error coding can be re-applied to the payload data to produce the transmitted bit stream. Comparison of the demodulated bit stream to the regenerated transmitted bit stream yields the pattern of errors. The pattern of errors is analyzed and a higher throughput decoding scheme is chosen based on the results of the analysis.

Abstract: Various embodiments provide a method for processing encoded data bits transmitted over a lossy communication channel. In some embodiments, the method receives the encoded data bits over the communication channel, the encoded data bits including redundant data units; decodes the encoded data bits at an error correction decoder, wherein the recovery of lost data is implemented at the error correction decoder using at least one of the redundant data units; determining if at least one data bit is unable to be recovered due to the decoder finding a plurality of candidate bit values for the at least one data bit; receives information relating to the transmitter; analyzing the plurality of candidate bit values to exclude at least one of the candidate bit values for the at least one data bit using information relating to the transmitter; and resolves the at least one data bit based on the analysis.

Abstract: Rating content of a digital file includes analyzing, by a computer, data associated with content of the digital file based on predetermined criteria defining a confidence level in the content of the digital file. Each predetermined criterion includes a range of values and at least one threshold delineating a lower confidence level and a higher confidence level. Different confidence ratings are assigned to different segments of the content based on determining that the different segments correspond to different thresholds of the predetermined criteria. The computer associates the different confidence ratings to the different segments.

Abstract: A device sample is screened for defects using its power spectrum in response to a dynamic stimulus. The device sample receives a time-varying electrical signal. The power spectrum of the device sample is measured at one of the pins of the device sample. A defect in the device sample can be identified based on results of comparing the power spectrum with one or more power spectra of the device that have a known defect status.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.

Abstract: An example method includes encapsulating, by an optical network device, at least a portion of a data packet to form a passive optical network (PON) frame. The method further includes applying, by the optical network device, a scrambling polynomial to at least a portion of the PON frame to generate a scrambled PON frame. The method further includes determining, by the optical network device, that the scrambled PON frame comprises a consecutive identical digit (CID) sequence greater than a threshold length. The method further includes replacing, by the optical network device the determined CID sequence with a correction pattern to generate a modified scrambled PON frame. The method further includes transmitting, by the optical network device, the modified scrambled PON frame.

Abstract: An apparatus and method for assessing image quality in real-time in consideration of both a coding error generated in an image processing process and a packet error generated in an image transmission process are provided. The apparatus for assessing image quality in real-time includes: an image quality measurement unit measuring image degradation generated in processing an image; a packet degradation detection unit detecting a packet error generated in transmitting the image; and final outcome drawing unit finally assessing the quality of the image in consideration of both a degradation degree of the image measured by the image quality measurement unit and the packet error measured by the packet degradation detection unit.

Abstract: An integrated circuit precharges a node 6 to a precharge voltage using precharging circuitry 4. During a discharge phase discharging circuitry 8 selectively discharges that node 6 is to represent a data/signal value. Sensing circuitry 10 detects a discharge characteristic to identify the data/signal value being represented. During the subsequent precharging operation of the node 6 back to the precharge voltage, validating circuitry 12 detects a precharge characteristic, such as the precharge current, the charge transferred, changes in the node voltage or a like, and compares this to the detected discharge characteristic corresponding to the data/signal value sensed by the sensing circuitry. If there is a mismatch, then an operation error signal is generated. The operation error signal may be used to adjust operation parameter, such as the operating voltage/frequency, the timing of the operation of a portion of the integrated circuit or another parameter.

Abstract: In a data transmission network, such as a passive optical network, the consecutive identical digit (CID) handling requirements may be reduced by providing a CID monitoring module at the transmitter end that monitors the number of CIDs in a transmission stream. Where the CID number exceeds a threshold, an error generation module induces an error in the transmission stream to reduce the CID below the threshold. The modified transmission stream may then be transmitted to a receiver, allowing clock recovery be performed with improved stability at the receiver. Once clock recovery is achieved, the receiver can then process the transmission stream to correct the errors induced at the transmitter end.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: Implementations of the present disclosure include methods, systems, and computer readable storage mediums for validating input parameters provided to an application, including executing the application using the one or more processors, collecting one or more validation aspects associated with the application to provide a set of validation aspects, receiving a first input parameter that is associated with a first validation point, extracting a first data type of the first input parameter, and determining that a validation aspect corresponding to the first data type is available in the set of validation aspects and, in response, applying a corresponding validation function to the first input parameter.

Abstract: A signal processor, which includes: a signal receiving section for receiving signals encoded under a predetermined code rule; a rule violation detecting section for detecting code rule violation included in the signals received by the signal receiving section; an error range specifying section for specifying a range in which an error bit is included out of a bit string which constitutes the signals on the basis of a position of the code rule violation detected by the rule violation detecting section; and an error correcting section for correcting one error bit in the range specified by the error range specifying section so that the code rule violation detected by the rule violation detecting section is eliminated.

Abstract: Provided is a signal processing device including a signal receiving unit for receiving a multilevel signal having a signal waveform that is obtained by synchronously adding an encoded signal generated based on a specific coding rule and a clock which has an amplitude larger than the encoded signal and for which the transmission speed is half that of the encoded signal, an amplitude level detection unit for detecting an amplitude level of the multilevel signal received by the signal receiving unit, a violation detection unit for detecting a bit position at which rule violation of the specific coding rule occurred, based on a change pattern of the amplitude level detected by the amplitude level detection unit, and an error correction unit for correcting a detection value of the amplitude level corresponding to the bit position detected by the violation detection unit so that the rule violation is resolved.

Abstract: A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit values may be removed from the possible decoding paths to consider, and decoding the encoded data bits by selecting a decoding path from remaining decoding paths of the possible decoding paths that were not removed. A-priori bit values may be extracted from various messages, such as DL-MAP, UL-MAP, RNG-REQ, and BW-REQ messages.

Abstract: Methods, systems and computer readable media for controlling an instrument in communication with a host computer are provided. Operations of an instrument that must be completed on schedule are controlled via an embedded controller embedded in the instrument. A complete status packet is sent to a host computer from the embedded controller. Periodically, the embedded controller repeats the sending of a complete status packet to the host computer, wherein status values in the complete status packet are updated with each iteration of sending a complete status packet.

Abstract: A decoder provided according to an aspect of the present invention determines a type of each network abstraction layer (NAL) unit, and discards a NAL unit when the size of the NAL unit is inconsistent with the size according to the determined type. According to another aspect, a decoder corrects for errors in the non-pay load portions and uses the corrected non-pay load portions to recover the original data contained in the payload portions of the data stream. In an embodiment, various global parameters (which are applicable to the data stream unless changed further in the data stream) and the values in the slice headers are examined to correct the parameters in the slice headers. According to one more aspect, an end of frame is reliably detected by using an expected number of macro-blocks in a frame and a set of logical conditions of slice header parameters.

Abstract: A signal judgement circuit making a judgement on a signal includes: an error signal generation circuit receiving signals via at least four signal lines and outputting an error signal when, of all the received signals, the number of signals taking on a same value does not exceed half of the number of the received signals; and an output selection circuit selecting any one of the received signals and outputting the selected signal.

Abstract: A wireless communication system includes a first communication station configured to operate according to a first communication protocol, and a second communication station capable of operating according to both the first communication protocol and a second communication protocol. When the second communication station transmits a packet according to the second communication protocol, at least a first signal field compliant with the first communication protocol and a second signal field compliant with the second communication protocol are attached to a header of the packet, and the first signal field includes a parity bit. When the second communication station receives a packet from another communication station, the second communication station performs a parity check on the first signal field of the packet, and when no parity error is detected, the second communication station further checks whether content of the first signal field is compliant with the first communication protocol.

Abstract: An apparatus, system, and method for providing error protection for data-masking bits in a memory device of a memory system are provided. The memory device includes a memory core to store data, and a data interface to receive the data and data-masking bits associated with a write command. The memory device also includes a gating block to control writing the data to the memory core, where the writing of the data to the memory core is inhibited upon detecting an error with one or more of the data-masking bits.

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A device for inputting digital values includes a digital keyboard configured to be actuated by an operator for inputting figures of a particular digital value, display unit that displays at least the input figures, a validating unit configured to be actuated by the operator for validating a displayed digital value, and an input-aid system having an acquisition unit that acquires the input figures as they are being input and a processing unit that, knowing the digital values which are valid, determines at each input of one figure based on the valid digital values at least one auxiliary figure, which the processing unit associates with a set of already input figures to form a proposed value, and transmits the proposed value to the display unit.

Abstract: Computer communications that are to be recorded are visible to a network interface on a recording computer. The network interface receives the packets to be recorded. The network layer of the recording computer implements a subset of the normal IP module in the network layer. The IP module in the network layer assumes that most IP datagrams are correctly addressed, internally consistent and of the expected protocol type. The recording computer allocates the received datagrams to a recording session based upon at least a first value of a field that is at a fixed position within the datagram. The datagrams for a session are ordered into an ordered recording stream based upon a timestamp within the datagram. The datagrams are also checked for criteria that indicate an error condition. The allocated and ordered datagrams are recorded or associated with other datagrams that have been allocated to the same session.

Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

Abstract: A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.

Abstract: Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding to a set of possible data transmission intervals. A preamble of the header contains timing information for development of a first set of time ranges to decode a synchronization word of the header. The synchronization word contains both data information and timing information to develop the second set of time ranges. The data information included in the header is used validate the data stream for the receiving device. The second set of time ranges is used to decode a data payload portion of the data stream.

Abstract: Various methods for written mathematical expression analysis are provided. One method may include receiving written input where the written input is representative of a mathematical expression. The method may also include analyzing the written input to identify at least one operator and at least one operand and constructing an expression tree based at least in part on predefined symbol relationships, the at least one operator, and the at least one operand. Similar apparatuses and computer program products are also provided.

Abstract: A method and apparatus for detecting and remediating damaged files as well as files containing proscribed code content, involving locating damage or proscribed code within a file, recording an identity of said file in which damage or proscribed code has been located, removing the damage or proscribed code by destroying the file that contains the damage or proscribed code, utilizing a search utility to locate a copy of the destroyed file according to one or more locations which are designated, and when located, copying the file to the original location of the destroyed file.

Abstract: A facsimile machine receives image data from a facsimile machine of another end. A Random Access Memory (RAM) stores a measured average value and fluctuation of an Eye Quality Monitor (EQM) value of the image data, and a number of error lines of the image data as an EQM data table. In past facsimile communication, a main control unit receives a training signal from the facsimile machine of the other end, and executes a training process. The main control unit measures an average value and fluctuation of an EQM value of the training signal, and compares the measured average value and the fluctuation of the EQM value with the average value and the fluctuation of the EQM value stored in the EQM data table. When there is no match, the main control unit executes the training process again.

Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.

Abstract: Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.

Abstract: A device-specific value is reliably generated in a device. In a first component of the device, a first digital value is generated that is substantially dependent fabrication variation among like device. Redundancy information is computed based on the first digital value. A subsequent digital value is later generated in the first component of the device. The first digital value is then determined in a second component of the device from the subsequent digital value and the redundancy information.

Abstract: The invention concerns a device (1) comprising a digital keyboard (2) capable of being actuated by an operator for inputting figures of a particular digital value, display means (3) for displaying at least the input figures, validating means (5) capable of being actuated by an operator for validating a displayed digital value, and an input-aid system (6) comprising acquisition means (9) for acquiring the input figures as they are being input, and processing means (10) knowing the digital values which are valid, determining at each input of one figure based on said valid digital values at least one auxiliary figure which it associates with the set of already input figures to form therewith a proposed value, and transmitting said proposed value to the display means (2) for display.

Abstract: A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.

Abstract: Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Abstract: A method for correcting data signal errors in a meter has been developed. The method includes receiving ordered data signals from the meter. Next, the sequenced of ordered data signals is analyzed to determine whether a data signal is missing. Finally, if a data signal is missing, a predetermined value is added to a sequence counter to compensate for the missing signal.

Abstract: A method of validating a bitstream loaded into a circuit having a programmable circuit is disclosed. According to one embodiment, the method comprises steps of loading a configuration bitstream comprising an error detection command at an input of the circuit; decoding the bitstream; providing a signal indicating that an error detection should be performed to a state machine when an error detection command has been decoded; and restarting the loading of the configuration bitstream if the signal has not been received. A device having a programmable circuit is also disclosed.