Abstract: A method for primary-backup server switching. A control server monitors whether a primary server fails. The control server is in communication connection with the primary server and a backup server. The primary server is provided with a primary memory database. The primary memory database is configured to save in real time state information of the primary server each time after an operation is executed, and the state information is read and saved in real time by a backup memory database in a backup server. In response to a failure of the primary server, the control server sends a primary-backup switching command to the backup server. The primary-backup switching command is configured to instruct the backup server to upgrade itself to become a new primary server according to the state information saved in the backup memory database.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

Abstract: A method, and associated system and computer program product, for dynamically modifying rules in a firewall infrastructure. A unit of deployment is received at a requestor module at a server. The unit of deployment includes the application code and a signed passport. The passport includes a firewall rule and a first application hash value. The received passport is authenticated, the received application code is hashed resulting in a second application hash value, and it is validated that the received first application hash value and the generated application hash value are equal. In response to the validation, the passport is received by a border control agent of the firewall from the server, a firewall is modified in the firewall infrastructure according to the received firewall rule, and communicating with the application is enabled through the modified firewall.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A suspicious person determination unit determines whether the face image of a matching target person is registered in a biological information DB by a matching result of a matching unit. When the face image of the matching target person is registered, area storage stores a specified area while correlating the specified area with a personal ID. A provisional registration unit makes a provisional registration of a suspicious person flag while correlating the suspicious person flag with the personal ID when a pattern of the specified area is a behavioral pattern of a suspicious person. A definitive registration unit makes a definitive registration of the suspicious person flag while correlating with the personal ID, when the provisional registration of the suspicious person flag is made for the face image of the matching target person, and when the face image of the matching target person is captured at a premium exchange counter.

Abstract: An ultraviolet laser generates a coherent beam, which is downconverted to produce pairs of frequency-entangled photons. For each entangled pair, a first photon is sent along a first path and a second photon is sent along a second path. A first detector detects those photons sent along the first path, and a second detector detects those photons sent along the second path. The detection is performed in a single photon regime. Coincidence counting is performed on outputs of the detectors, including comparing leading edges on outputs of the first and second detectors within a time window.

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

Abstract: Gaps in performance data are corrected for through data transformations and conversion. A raw sequence is transformed by correction logic into an interval sequence by partitioning a performance monitoring period into equal intervals and assigning values based on the raw sequence. Locality sequence entries can indicate whether the interval sequence relies on estimation. The interval sequence is converted into an absence length sequence whose entries indicate null value periods in performance data. Conversion includes generating a presence sequence from the interval sequence, and deriving the absence length sequence from the presence sequence, by using a set-based algorithm or other mechanism. Excessive absence length values support treating intervals as downtime for the machine. Correction logic may include a stored procedure residing in a database, for example, which produces the absence length sequence without using a procedural language.

Abstract: A method for fast and efficient data downloading in wireless communications. The method includes ways to download file data of a large size from a server (access point) to a user's client (mobile device) at high speed and efficiency by using both mmWave wireless communication and conventional wireless communication (WiFi, 3G, etc.). A server transmits packetized file data to a client. The file data is transmitted as data packets via mmWave. In parallel, the server transmits check packets (roll-call packets) corresponding to the data packets. As a test at the time of establishing links, the latency for each communication line is measured. The receiver side, upon completion of receiving the check packets, checks whether their corresponding mmWave packets have arrived. If any corresponding mmWave packet has not arrived, it is determined that the mmWave packet has been lost and a retransmission request is immediately returned to the server via WiFi.

Abstract: Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor ?C (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6?) one after the other through at least one error line (3, 4).

Abstract: An image forming apparatus includes: a hard disk storage unit for storing user registered data; a display unit for displaying the user registered data in a user selectable state; a power supply unit for supplying power to the hard disk storage unit; a power supply control unit for interrupting or starting power supply to the hard disk storage unit; a switch memory for storing at least a part of the user registered data stored in the hard disk storage unit; and an access switching unit for displaying the user registered data stored in the switch memory on the display unit in a user selectable state when the power supply from the power supply unit to the hard disk storage unit is started.

Abstract: A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal (I) and a data signal that is output from another semiconductor circuit for testing.

Abstract: A method for correcting the prediction of values of signal with time variation, in particular for navigation messages sent by the global satellite navigation systems, includes the following steps for the correction of the predictions of a parameter included in a received signal and varying in time: estimation of the prediction error based on a first batch of values estimated during a determined time period by comparing these values to the values previously predicted for the same determined time period, analysis of the predicted time-oriented series of prediction errors by a method for processing the signal and isolating the contributions of the systematic effects, and extrapolation of the behavior of the contributions of the systematic effects during the time period concerned and correction of the predictions using the duly extrapolated values.

Abstract: Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A system and method communicates commands from a command originator to receiving devices, yet the receiving devices do not confirm receipt of the command. The most current command (e.g. the one with the highest sequence number) is rebroadcast by the command originator and the receiving devices, tending to be more frequent upon detection of an event indicating that the most current command was not received by at least one other device, and less frequently upon detection of an event indicating that the most current command was provided with sufficient duplication that if another device could receive it, the device likely did receive it, subject to a maximum and minimum rate.

Abstract: A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.

Abstract: A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

Abstract: Computer communications that are to be recorded are visible to a network interface on a recording computer. The network interface receives the packets to be recorded. The network layer of the recording computer implements a subset of the normal IP module in the network layer. The IP module in the network layer assumes that most IP datagrams are correctly addressed, internally consistent and of the expected protocol type. The recording computer allocates the received datagrams to a recording session based upon at least a first value of a field that is at a fixed position within the datagram. The datagrams for a session are ordered into an ordered recording stream based upon a timestamp within the datagram. The datagrams are also checked for criteria that indicate an error condition. The allocated and ordered datagrams are recorded or associated with other datagrams that have been allocated to the same session.

Abstract: A system and method communicates commands from a command originator to receiving devices, yet the receiving devices do not confirm receipt of the command. The most current command (e.g. the one with the highest sequence number) is rebroadcast by the command originator and the receiving devices, tending to be more frequent upon detection of an event indicating that the most current command was not received by at least one other device, and less frequently upon detection of an event indicating that the most current command was provided with sufficient duplication that if another device could receive it, the device likely did receive it, subject to a maximum and minimum rate.

Abstract: The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.

Abstract: A delay measuring device according to the present invention comprises a memory cell, a delay element and a selector. The memory cell is provided with a non-inversion output terminal and an inversion output terminal, and the memory cell fetches a data value inputted from outside in synchronization with a clock, retains the fetched data value and outputs the retained data value from the non-inversion output terminal and the inversion output terminal. The delay element is connected to the inversion output terminal. The selector selects one of the data value and a delayed data value outputted from the delay element and supplies the selected data value to the memory cell. In the present invention, a comparison result of making a comparison between a delay amount generated in the delayed data value and a time length defined based on the clock is outputted from the non-inversion output terminal.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate the lockout time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.

Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.

Abstract: A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part.

Abstract: The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, among other things, pulse density/width variation and jitter control.

Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: Method and system for repairing memory failure in a computer system in one aspect determines one or more test patterns and time duration for testing the new memory unit that replaced a failed memory unit. The test pattern is written to the new memory unit and read from the new memory unit. The read pattern is compared to the test pattern that was used to write. If the read test pattern and the written test pattern doe not match, a further repair action is taken. If they match, writing and reading of the test pattern repeats until the time duration for testing expires. The new memory unit may be configured as available for use when the write and read test completes successfully for the testing time duration.

Abstract: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.

Abstract: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.

Abstract: A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A method of validating a bitstream loaded into a circuit having a programmable circuit is disclosed. According to one embodiment, the method comprises steps of loading a configuration bitstream comprising an error detection command at an input of the circuit; decoding the bitstream; providing a signal indicating that an error detection should be performed to a state machine when an error detection command has been decoded; and restarting the loading of the configuration bitstream if the signal has not been received. A device having a programmable circuit is also disclosed.

Abstract: A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal.

Abstract: Methods, system, and computer programs for compensating for introducing data dependent jitter into a test signal using a testing instrument are disclosed. The method includes generating a test pattern that comprises a plurality of intervals. Each of the intervals includes a number of redundant samples that correspond to a sample in a test source pattern. The test pattern is digitally modified to generate a modified test pattern that includes data dependent jitter.

Abstract: A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

Abstract: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop event, such as a packet trailer, a specified digital event, a time interval or the like, is identified to generate a disable signal. The enable and disable signals are combined to produce a qualification signal that allows a trigger circuit to trigger on a specified anomaly within the portion of the serial data stream defined by the qualification signal.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user. The length of the delays inserted into a data transfer may be determined dynamically using an iterative search technique to more rapidly converge on time-gap defects. Both bisection and Fibonacci search methods are examples that may be used.

Abstract: Health of a high-speed interface link, such as a PCI Express link, is measured. In one embodiment, counter data representing data sent and errors occurring in a high-speed interface link is read. Health statistics based on the counter data are computed. The health statistics may be displayed as a graphical representation. Various statistics representing bus utilization, error rates, efficiency and/or other measures of link health may be computed and displayed.

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.

Abstract: A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these refresh request pulses are produced. Next, a control unit for the information memory is supplied with refresh test pulses produced outside of the information memory instead of being supplied with the refresh request pulses. Then, the refresh test pulses are used to check a refresh device situated on the information memory.

Abstract: Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated.