Abstract: Technologies are generally described herein to detect unidirectional resistance drift errors in a multilevel cell of a phase change memory. The resistance levels of the multilevel cell of the phase change memory may be encoded to detect unidirectional resistance drift errors. In some examples, Berger Code-compatible encoding may be used. When a word is written to the multilevel cell, a write check code may be generated. The write check code may be a binary representation of the number of zeroes contained in the word as written. When the word is read from the multilevel cell, a read check code may be generated. The read check code may be a binary representation of the number of zeroes contained in the word as read. An error can be detected if a comparison indicates that the write check code and the read check code are different.

Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Abstract: An intrinsically safe digital circuit has at least two output signals and at least four input signals for detecting a potential error in the circuit and/or in one of its input signals, the at least four input signals forming two input signal pairs inverted in a double-track manner, and the at least two output signals forming an output signal pair inverted in a double-track manner. The output signal pair transmits a piece of information which is identical to the one of an input signal pair, when the error is not present.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: According to an embodiment, an information processing apparatus includes: a receiving unit that receives a fragment packet; an extracting unit that extracts checksum information of which packet has not been subjected to the fragmentation process, and causes the checksum information to be stored in a checksum storage unit; a calculating unit that performs a checksum calculation on each of the plurality of received fragment packets, integrates a calculation result of each fragment packet, and causes an integrated calculation result to be stored in a calculation result storage unit; and a determining unit that determines whether or not there is an error in a packet obtained as a result of combining based on the integrated calculation result stored and the checksum information stored.

Abstract: Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided.

Abstract: The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x?[1](t), . . . , x?[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function.

Abstract: A method and a configuration produce a fault signal that is suitable for identifying transmission faults when using differential signaling. A first mid-level signal whose potential is in the area of the mid-point between the signal level on a first signal line and a signal level on a second signal line, when a logic “1” is transmitted is compared with a second mid-level signal formed when a logic “0” is transmitted. The fault signal is produced if the discrepancy between the two mid-level signals is greater than a predetermined threshold value.

Abstract: The invention relates to a method of synchronizing two digital data streams with the same content, the method comprising the steps of: a) generating at given intervals for each of the two digital data streams S1 and S2 at least two characteristic numbers expressing at least one parameter characteristic of their content; b) generating from said numbers points D1 and D2 for each of the two streams S1 and S2 representing at least one of said characteristic parameters in a space of at least two dimensions, the points D1 corresponding to the stream S1 and the points D2 corresponding to the stream S2 that are situated in a time period T defining trajectories representative of the data streams S1 and S2 to be synchronized; c) shifting the time periods of duration T assigned to the digital data streams S1 and S2 relative to each other by calculating a criterion of superposition of said trajectories having an optimum value representing the required synchronization; d) choosing the shift between the time periods corres

Abstract: A method and device for detecting faults in an electronic circuit, such as a multiplexed latch includes n control inputs, p data inputs, and at least one output. The method involves trying to cause the electronic circuit to function to modify the state of the output with respect to a start state, knowing that if the state of the output effectively changes while the control inputs are inhibited, this means that at least one control input is stuck at logic 1.

Abstract: A method processes the outputs of a discrete sensor in a computer system. An initial value mask is applied to each one of the offset bits in the output of the discrete sensor. An initial value is obtained for each one of the offset bits in the output of the discrete sensor according to the initial value mask. It is next determined whether or not the offset bits in the output of the discrete sensor includes both initialization offset bits and transition offset bits. If the offset bits include both initialization offset bits and transition bits, only the initialization bits of an incoming mask corresponding to the output of the discrete sensor are reset.

Abstract: Error checking for an electric data transmission system for differential transmission of binary data pulses using two lines, in which the signals on both lines are differentiated each, the resulting differential signals and a reference signal are summed up to form a sum signal, the sum signal is compared with the reference signal on the one hand and the two differential signals are compared with the sum signal on the other hand, and error signals are produced from the result of these comparisons when line errors of a specific kind are present.