Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A decoding apparatus acquires, from encoded data, a piece of additional bits that have been partly cut off, acquires, from the piece of the additional bits, the number of bits that are missing due to the cutting off as the number of missing bits, and restores the additional bits by reproducing the missing bits.

Abstract: A method includes writing data to a bit-patterned media at times determined by a clock having a period that is offset from a bit island period by a fixed offset to create one insertion or one deletion approximately within a predetermined number of bit islands, reading the data, and correcting the read data using error correction. An apparatus that implements the method is also provided.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: A printer prints a print job having a plurality of blocks each of which has a block size section and corresponding data that should be printed. A receiving section receives the print job from an external apparatus. A comparing section compares a content of the block size section with a threshold value. When the content of the block size section exceeds the threshold value, a discarding section discards a subsequent portion of the data. The threshold value is set to a user's desired value.

Abstract: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.

Abstract: A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output terminal. The flip-flop unit has a second input terminal coupled to the first output terminal, a clock signal input terminal for receiving a reference clock signal, and a second output terminal outputting an output data. The first buffer is coupled to the flip-flop unit to convert the output data to a high voltage data, and outputs the high voltage data. The second buffer is coupled to the first buffer to convert high voltage data to low voltage data and transmit the low voltage data to the feedback input terminal.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.

Abstract: A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

Abstract: A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: Drop-outs in a data read channel having one or more controllable elements are managed. A data read channel derives a signal having at least one drop-out characterising parameter from which data are to be recovered. The signal from the data read channel is tapped and compared with at least one drop-out characterising parameter of the tapped signal with two or more thresholds to categorise the drop-out. One or more elements of the data read channel is controlled in response to the category of the drop-out.

Abstract: A method for detecting dropouts in digital data transferred over a bus from a digital data source to a computer system. Each address in the computer system buffer memory is initialized to a selected code value known not to exist in the data to be transferred. After sequential transfer of data to the buffer memory, the presence of the selected code value in the buffer memory indicates that a dropout occured.