Abstract: At least one value of abnormal metrics is identified as being an abnormal dimension value. A dominant dimension related to the anomaly is identified based on the identified abnormal dimension value.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: Methods, systems, and computer-readable media with executable instructions stored thereon for determining root cause are provided. A method for determining root cause can include receiving values for at least one performance metric for each of a plurality of components of an IT system to establish a normal value for each of the performance metrics, receiving an abnormal value that differs from the normal value for at least one of the plurality of components of the IT system, and determining a probability that the at least one of the plurality of components of the IT system is a root cause of the abnormal value.

Abstract: In one embodiment, a user interface includes at least one instance of each of at least one widget. Recording a plurality of widget interaction instances (WIIs) for the user interface, each WII resulting from a user interaction applied to a particular instance of a particular widget. Clustering the plurality of WIIs based on a text value and a path value of each WII, such that each cluster of WIIs is associated with a particular widget. Determining, for each of at least one cluster of WIIs, whether the particular widget associated with the cluster of WIIs is erroneous based on whether user interactions corresponding to the WIIs in the cluster have produced responses from a software application that includes the user interface.

Abstract: In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.

Abstract: High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40 G/100 G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.

Abstract: The invention relates to an electrical or electronic system, and more specifically, to a system with a bus, and a method to transmit data, in particular error data over a bus system. According to an embodiment, a method to transmit error data over a bus system that connects a plurality of modules/components/elements of an electronic system in a chain-like structure comprises in a first phase, transmitting information regarding what kinds of errors have occurred in the system, and in a second phase, transmitting information regarding where in the system an error has occurred.

Abstract: The failure of a specific link of a specific node of a cluster is detected, for example through the operating system of the specific node. A notification of the failure of the specific link is disseminated to the nodes of the cluster, such that the nodes receive the notification prior to learning of the link-down event from the expiration of corresponding heartbeats, and process the event in parallel. The notification of the link failure can be disseminated by broadcasting a message notifying the nodes of the failure of the specific link. The notification of the link failure can also be disseminated by transmitting the notification to a centralized computing device which is polled by the nodes of the cluster at a specific frequency for notifications of link failures.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system.

Abstract: Provided herein are a method, apparatus and computer program product for interpreting user input and mitigating erroneous inputs on a device. In particular, methods may include receiving an indication of a first touch event, determining, by a touch mediation function, if the first touch event is an erroneous touch event, causing the first touch event to be sent to an application in response to the touch mediation function determining that the touch event is not erroneous; and causing the first touch event to not be sent to the application in response to the touch mediation function determining that the first touch event is erroneous. The first touch event may occur proximate a first capture area for the user interface and the method may further include causing the first capture area for the user interface to be adjusted in response to the first touch event.

Abstract: A control system according to the principles of the present disclosure includes an operation control module, a fault detection module, a remedial action module, and a reset module. The operation control module controls operation of a vehicle system. The fault detection module detects a fault in the operation control module when the operation control module fails an integrity test. The remedial action module takes a remedial action when the fault is detected. The reset module resets the operation control module when the fault is detected and the remedial action is not taken.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: There is provided a method and system for determining an impact of failures in a data center network. The method includes identifying failures for the data center network based on data about the data center network and grouping the failures into failure event groups, wherein each failure event group includes related failures for a network element. The method also includes estimating the impact of the failures for each of the failure event groups by correlating the failures with traffic for the data center network.

Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices.

Abstract: A computing device adapted to receive at least one JavaScript, the computing device comprising a processor type and one or more architectural features. The at least one JavaScript comprises one or more first sections of the JavaScript and one or more second sections of the JavaScript. The one or more first sections of the JavaScript may be pre-compiled using the processor type or the one or more architectural features. The one or more second sections of the JavaScript may be sent to a JavaScript Compiler in source format. A JavaScript Engine may be adapted to execute the one or more first sections of the JavaScript and the subsequently compiled one or more second sections of the JavaScript, keeping elements of the scripting code proprietary, with the pre-compilation of the one or more first sections of the JavaScript eliminating run-time compilation and therefore providing performance benefits.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.

Abstract: Various embodiments provide a method and apparatus of providing a rapid disaster recovery preparation in cloud networks that proactively detects disaster events and rapidly allocates cloud resources. Rapid disaster recovery preparation may shorten the recovery time objective (RTO) by proactively growing capacity on the recovery application(s)/resource(s) before the surge of recovery traffic hits the recovery application(s)/resource(s). Furthermore, rapid disaster recovery preparation may shorten RTO by growing capacity more rapidly than during “normal operation” where the capacity is increased by modest growth after the load has exceeded a utilization threshold for a period of time.

Abstract: Embodiments are directed to establishing the integrity of a portion of data on at least one level of a plurality of network stack levels and automatically continuing an established federation relationship between at least two federation computer systems. In an embodiment, a first federation computer system receives a digital signature corresponding to a computer system signed by a digital signature which includes the computer system's identity and other federation relationship information configured to establish a trusted federation relationship between a first federation computer system and a second federation computer system. The first federation computer system attempts to validate the received digital signature at a first level of a network stack and determines that the validation at the first network stack layer was unsuccessful. The first federation computer system then validates the received digital signature at a second, different level of the network stack.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: A control channel may be used to transmit control information, such as Downlink Control Information (DCI), to a mobile device from a network component, such as a base station or a base node. The mobile device may use a blind decoding scheme to detect DCIs. A DCI may be falsely detected by the mobile device. According to some embodiments, data that has been decoded by a blind decoder, from buffer data for a candidate control channel, is re-encoded. The re-encoded data is compared to buffer data for the control channel. The decoded data is treated as control information dependent on the comparison of the re-encoded data with the buffer data. In some embodiments, comparing the re-encoded data to the buffer data includes generating a metric as a function of a degree of similarity between the re-encoded data and the buffer data. The metric may be compared to a threshold.

Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: Devices, methods and instructions encoded on computer readable medium for implementation of a dual-adjacency between edge devices of a network site. A first edge device comprises one or more local interfaces configured for communication, via a local network, with one or more network devices co-located in a first network site. The first edge device also comprises one or more overlay interfaces configured for communication, via a core network, with one or more network devices located in one or more other network sites connected to the core network. The first edge device comprises a processor configured to establish, via at least one of the local interfaces, a site communication channel with a second edge device co-located in the first network site. The processor is further configured to establish an overlay communication channel, via at least one of the overlay interfaces, with the second edge device.

Abstract: A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.

Abstract: A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.

Abstract: Techniques are described for detecting the occurrence of error scenarios occurring across a plurality of nodes. Embodiments retrieve a plurality of error scenario profiles. Each of the error scenario profiles specifies prerequisite criteria, the prerequisite criteria including at least one of (i) one or more errors and (ii) one or more conditions. The plurality of nodes is monitored to detect errors occurring on nodes within the plurality of nodes. Embodiments then detect the occurrence of an error scenario, when at least a portion the monitored errors match the prerequisite criteria specified in a first one of the error profiles and when the one or more conditions specified in the first error profile are satisfied.

Abstract: A network-enabled controller for a bathing unit is provided. The controller includes a network interface and a memory storing operational setting information associated with the bathing unit. Through the network interface, the controller connects to a home network and registers and maintains an active communication link with a gateway accessed over a network external to the home network. In response to receipt of a status request originating from a remote client, the controller processes the status request and selectively transmits operational setting information stored in the memory to the remote client. A system for facilitating remote control and monitoring of network-enabled controllers for bathing units is also provided.

Abstract: Provided is a semiconductor device including: a first memory that stores multiple instructions; a second memory that stores multiple data items; first and second buses; a microprocessor that fetches, through the first bus, an instruction at a specified address among the multiple instructions stored in the first memory, executes the instruction, and accesses the second memory through the second bus based on a result of the execution; and a trace information output unit that acquires, when a branch instruction is generated in the microprocessor, address information of the first memory specified before branching, and outputs the information as trace information. The trace information output from the trace information output unit is written into the second memory through the second bus in a period in which the microprocessor does not access the second memory during execution of the branch instruction.

Abstract: Mechanisms for preventing a distribution of a failure caused by a sequence of instructions in a distributed client server environment are provided. These mechanisms comprise executing the sequence of instructions on a first client, the instructions being provided by a management control server and being indicative of maintenance actions. These mechanisms may further comprise determining by the first client a failure caused by the sequence of instructions, and generating a warning message by the first client based on the determined failure. The warning message may comprise an indicator for the sequence of instructions. In addition, these mechanisms may comprise sending the warning message for informing a second client about the sequence of instructions causing the failure in order to prevent a distribution of the failure.

Abstract: An exemplary computer error detection device for detecting the warning sounds emitted by a malfunctioning computer is provided. The computer error detection device includes a storage unit, a display unit, a detection unit, and a processing unit. The storage unit includes a look-up table (LUT). The LUT includes a plurality of solution plans each corresponding to a predetermined warning sound. The display unit displays a selecting interface thereon for a user to input a basic input output system (BIOS) type or a computer model of the computer. The detection unit records a warning sound emitted from the malfunctioning computer and generates an electronic sample of the warning sound. The processing unit searches the LUT to determine a solution plan corresponding to the sample, and controls the display unit to display the determined solution plan.

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: The subject disclosure is directed towards a technology by which the accuracy of context-based information provided by at least one data source for received context data is increased. Correctness information received in association with usage of looked up context-based information is logged. The correctness information may be processed to increase the overall accuracy by correcting a data source, and/or by creating a blended data source that includes the most likely accurate portions (segments) from among multiple data sources as determined via the correctness information.

Abstract: A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change.

Abstract: A method and system for controller level identification and isolation of a degraded physical link (PHY) in a serial attached small computer system interface (SA-SCSI) or SAS domain. The method and system uses computer readable code embodied within the controller level of an SAS domain to monitor a plurality of PHY pairs associated as connecting through a wide port. The invention compares a history of PHY pair errors to a tunable timer to determine if PHY errors reach a threshold. Should the threshold be exceeded, the controller disables the error prone PHY pair and delivers a notification. The controller may then re-enable the disabled PHY after user action or port power up.

Abstract: A method of providing synchronization and integrity checking in a high integrity processing system having at least two redundant processing lanes, with each lane having an application processor, with the application processors running the same application software in a non-lockstep configuration, and outputting transactions requiring access to an addressable space.

Abstract: Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data.

Abstract: Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security Association that the packet is faulty; incrementing a count corresponding to previous faulty packets received; determining that the count exceeds a threshold; and disabling IPSec accelerator hardware in response to the determining that the count exceeds the threshold.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.

Abstract: According to one embodiment, a method for detecting a periodic error, the method detecting a periodic processing error of a module controlled by a processor, the processor controlling a periodic processing by booting a peripheral module, the peripheral module outputting periodic triggers with a predetermined interval includes storing a first count value acquired from a counter, a second count value when the processing is started, and a third count value when the processing is completed, calculating a processing time on a basis of the three count values, and comparing the processing time with the predetermined interval to determine whether the periodic processing error occurs.

Abstract: Implementations of the present disclosure include methods, systems, and computer readable storage mediums for validating input parameters provided to an application, including executing the application using the one or more processors, collecting one or more validation aspects associated with the application to provide a set of validation aspects, receiving a first input parameter that is associated with a first validation point, extracting a first data type of the first input parameter, and determining that a validation aspect corresponding to the first data type is available in the set of validation aspects and, in response, applying a corresponding validation function to the first input parameter.

Abstract: A receiver can include a sampler module for sampling a data-bearing input signal to extract data encoded in the data-bearing analog input signal. The sampling results in data-symbol sequences. The data-symbol sequences can be used to identify error events. The identified error events can be used as a basis for adjusting tap coefficients. The tap coefficients can be used in setting reference levels for the sampler module.

Abstract: A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.

Abstract: A method is provided for managing changes to a computer system. The method includes generating a database configured with fields identifying one or more component changes and potential problems associated with each one or more component changes; populating the fields of the database with information as a change is made to a computer system; monitoring the computer system for issuance of error alerts; comparing issued error alerts against entries of potential problems in the database; and identifying a set of at least one of the component changes as a potential cause of the issued error alert based on the result of the comparing step. The method executes a corrective process in response to the identification of the potential cause of the issued error and updates the database entry of the set of at least one of the component changes to reflect the issued error as a confirmed error thereof.

Abstract: Maintaining bandwidth in links betweens servers and storage arrays comprising a device. The device establishes the links. The device identifies a first link from the links. The first link has a high response time. The device transmits a plurality of data packets on the first link. Each data packet is associated with a corresponding acknowledgment (ACK). The transmission is performed without waiting for the corresponding ACK to be received. The device tracks the ACK received in response to each of the transmitted data packets. The device detects a failure of the first link. In response to the detection, the device identifies invalid data packets. The invalid data packets comprise data packets transmitted on the first link after the detected failure.

Abstract: In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed.