Abstract: Control apparatus having pre-defined error-states and related methods are described. An example method of controlling a field control device described herein includes receiving, via a controller coupled to the fluid control device, a communication from a control system remotely located from the controller to operate the field control device during a non-error condition, detecting whether an error condition has occurred, and operating the field control device based on a pre-determined error-state instruction stored in the controller when the error condition is detected.

Abstract: A method for distributed diagnostic reasoning is provided. The method includes establishing a computing node monitoring the operation of a component of a complex system and populating at least one of a processor and the memory of the computing node with one or more standardized executable application modules (SEAMs) and a workflow service. The method further includes creating a configuration file in combination with several SEAMS to create a distributed diagnostic reasoner (DDR) associated with the component. The method also comprises installing the configuration file in the computing node for execution by the processor; and initializing the one or more SEAMS, the configuration file and the workflow service, wherein the workflow service facilitates data flow between the one or more SEAMS and the static data associated with a fault condition resident in the configuration file.

Abstract: A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails adding an amount of jitter within the CDR to change the receiver phase. The amount of jitter is incrementally increased until a threshold level of bit errors occur. Based on the amount of jitter needed to cause the threshold level of bit errors, timing margin can be calculated.

Abstract: Methods and arrangements for fault localization. Structural clusters for an environment are received, and configuration parameters and dependencies for components in the structural clusters are identified. A configuration map is built, and a configuration fault occurrence is ascertained.

Abstract: A set of workflows are provided for supporting proper user notifications after an action is taken by the user in conjunction with an asynchronous communication service. Timing and/or type of the notifications or an action to be taken by the service is determined based on one or more of a nature of the user action that failed, a time elapsed since the action was taken, multi-action dependencies, device types, and similar characteristics enhancing user experience and reducing confusion.

Abstract: In one embodiment, an apparatus for avoiding packet losses is provided. The apparatus includes a first communication device that is configured to receive packets of data over a network from a second communication device and to store information indicative of a sliding window that corresponds to a predetermined number of packets of data. The first communication device is further configured to determine a number of lost packets of data from within the sliding window in response to receiving the packet of data and to determine a maximum value from the sliding window. The maximum value corresponding to a maximum number of lost packets of data for a number of sliding windows. The first communication device is further configured to control the second communication device to adjust a bandwidth rate at which the packets of data are transmitted over the network based on at least the maximum value.

Abstract: A channel path error correction system includes a processor with one or more channels and a switch operatively coupled to the one or more channels of the processor. The system also includes an I/O device including one or more ports, the I/O device being operatively coupled to the switch by the one or more ports; a plurality of control units. Each control unit includes at least one of the channels and at least one of the ports and a memory operable for storing information relating to detected channel path errors associated with each of the plurality of control units.

Abstract: A storage apparatus includes a storage drive which writes and reads out a block of data with respect to a storage medium loaded on the storage apparatus, a processor which executes access control on a plurality of volumes assigned to the storage medium and a memory which stores a piece of management information that includes a piece of information indicating a usage frequency of each of the volumes. The processor executes a procedure including: determining a reallocation target volume from among a plurality of volumes assigned to the storage medium based on the management information, and moving the data of the reallocation target volume to a reallocation destination storage medium which is different from the storage medium.

Abstract: Storage management systems and methods are presented. In one embodiment, a method comprises: performing a hierarchical configuration information process, including accessing information regarding hierarchical relationships of components associated with a storage environment; performing a storage resource consumption detection process, including detecting consumption of storage resources included in the storage environment; and performing a coordinated consumption analysis process in which at least part of an analysis of the consumption of the storage resources is coordinated across multiple levels of an active spindle hierarchy. In one embodiment, a reaction process is performed. The reaction process can include performing an automated consumption notification process and an automated reclamation process based upon results of the storage resource consumption detection process.

Abstract: The present invention is related to a failure check apparatus for performing a failure check of plural CPUs, wherein the failure check apparatus is configured to predict or detect a process load of the CPUs as a whole based on vehicle information related to processes of the CPUs, and change a way of performing a failure check according to a prediction or detection result of the process load. The CPUs may be CPUs in a multi-core processor. The failure check apparatus may perform the failure check if it is predicted or detected that the process load of the CPUs as a whole is lower than a predetermined reference.

Abstract: A system and method for providing reliable storage are provided. A method for initiator operations includes storing information associated with an access attempt in a store, and accessing a storage system responsive to the access attempt, wherein the storage system includes a first storage node and a second storage node arranged in a sequential loop, and where the first storage node is accessed by an initiator. The method also includes determining if the access attempt completed successfully, deleting the information from the store if the access attempt completed successfully, and indicating an error if the access attempt did not complete successfully.

Abstract: In invariant analysis applied to a plurality of the analyzed systems, delay in detecting a fault is decreased. An operations management system 1 includes a correlation model storing unit 212, an analysis order storing unit 412, an analysis unit 300, and an order control unit 400. The correlation model storing unit 212 stores a correlation model 222 which indicates a correlation among plural types of performance values, for each of plural systems. The analysis order storing unit 412 stores a detection order in the plural systems for carrying out detection of correlation destruction. The analysis unit 300 carries out, in each of plural time periods, detection of whether the correlation destruction of the correlation included in the correlation model of each of the plural systems is caused or not by use of performance values inputted for the each of plural time periods, on the basis of the detection order. The order control unit 400 updates the detection order in the each of plural time periods.

Abstract: A data processing apparatus, comprising processing circuitry, which in use, generates data and debug circuitry arranged to debug operation of the processing circuitry. The processing circuitry includes bus circuitry arranged to pass data at least one of into and out of the processing apparatus over a communication bus. The debug circuitry comprises monitoring circuitry arranged to monitor the data generated, in use, by the processing circuitry and generate a stream of trace elements. An interface unit is arranged to interface, using the bus circuitry, the trace elements generated by the monitoring circuitry onto the communication bus to be output, in use, from the processing apparatus using the communication bus. The interface unit comprises a controller which is arranged to control operation of the interface unit independently of the operation of the processing circuitry.

Abstract: Disclosed herein is a semiconductor integrated circuit capable of detecting an abnormality that can cause a malfunction in signal transmission via an isolation element and of issuing a stop signal to the target to be controlled. The semiconductor integrated circuit includes a transmission circuit generating and outputting a transmission signal reflecting transmission data supplied from outside, a reception circuit reproducing the transmission data based on a reception signal, an isolation element isolating the transmission circuit from the reception circuit and transmitting the transmission signal as the reception signal, an abnormality detection part detecting an abnormality that can cause a malfunction in signal transmission via the isolation element, and a control part outputting a stop signal if the abnormality detection part detects the abnormality, regardless of the transmission data supplied to the transmission circuit from outside.

Abstract: A method for providing independent static and dynamic models in a prediction, control and optimization environment utilizes an independent static model (20) and an independent dynamic model (22). The static model (20) is a rigorous predictive model that is trained over a wide range of data, whereas the dynamic model (22) is trained over a narrow range of data. The gain K of the static model (20) is utilized to scale the gain k of the dynamic model (22). The forced dynamic portion of the model (22) referred to as the bi variables are scaled by the ratio of the gains K and k. Thereafter, the difference between the new value input to the static model (20) and the prior steady-state value is utilized as an input to the dynamic model (22). The predicted dynamic output is then summed with the previous steady-state value to provide a predicted value Y.

Abstract: A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.

Abstract: An input/output processing method includes generating and storing at least one address control word (ACW) including a data check word generation field and/or a data check word save field in local channel memory of a channel subsystem, and generating and forwarding to a network interface an address control structure specifying a location in the local channel memory of a corresponding ACW. The method also includes, responsive to a data transfer request, storing the at least one data check word in the data check word save field and routing the data to a host memory location specified by the corresponding ACW responsive to performing a check of the data and determining that the data has not been corrupted, or retrieving the data based on the corresponding ACW, generating and appending at least one data check word and routing the data and the at least one data check word to the interface.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a media defect detector circuit. The media defect detector circuit is operable to compare a data input derived from a medium against at least a first defect level to yield a first level output, and a second defect level to yield a second level output; and provide a combination of the first level output and the second level output as a defect quality output. A value of the defect quality output corresponds to a likelihood of a defect of the medium.

Abstract: In a controller of a tape drive, when an error recovery section cannot recover an error detected by an error detecting section, an error-report generation section generates an error report, an error-information acquisition section acquires error information of the tape drive and a cartridge loaded in the tape drive, an error-information exchange section acquires pieces of error information of other tape drives and cartridges loaded in these other tape drives, an error-factor judging section judges whether the error is attributable to the tape drive or the cartridge based on these pieces of error information, an error-report update section updates the error report in accordance with the result of this judgment, and an error-report output section outputs the error report thus updated to a host.

Abstract: A method for validating the data defining an executable program prior to loading of the data for program execution is described.

Abstract: To make it possible to easily identify the error location, a communication apparatus includes: a first storage unit; an error detecting unit detecting a bus error caused on a bus of its own PLC; an error counting unit counting the number of times the error detecting unit has detected a bus error and recording a counted value of the bus error in the first storage unit; a transmitting unit transmitting a counted value recorded in the first storage unit and counted by the error counting unit to all of other PLCs belonging to the same PLC system; and a receiving unit receiving a counted value transmitted from the other PLCs belonging to the same PLC system and storing the received counted value in the first storage unit in such a way that a PLC that is a transmission source of the counted value can be identified.

Abstract: A decoding device that performs decoding of data transmitted from each of a plurality of users comprises an iterative decoding section that repeats decoding of the data until no error is detected in a result of decoding, an error detection section that performs error detection on the decoding result each time decoding is performed, and a decoding order control section that estimates with respect to each of the plurality of users a decoding completion time, which is a time period the time period required until no error is detected in the result of decoding of the data transmitted from the user, and that assigns priorities to the users in increasing order of the estimated decoding completion time. The iterative decoding section performs decoding of the data transmitted from the users for the users in descending order of the priorities.

Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

Abstract: An electronic apparatus includes an error detection times acquiring module and a waiting module. The error detection times acquiring module acquires the number of reading error detection times of a program according to a power-ON instruction instructing a power-ON operation, the number of error detection times being stored in a storage module. The waiting module waits for a reception of data capable of recognizing a communication counterpart device when the number of error detection times is more than a predetermined value by comparing the acquired number of error detection times with the predetermined value.

Abstract: A microprocessor includes a central processing unit, at least one call stack, a stack pointer, an address bus, and a data bus. The microprocessor further includes a hardware monitor configured to supply protection codes, insert the protection codes in the stack or let the central processing unit insert them, and then generate an error signal in response to an attempt to modify a protection code present in the stack.

Abstract: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.

Abstract: An information processing apparatus is capable of automatically determining whether an operation log needs to be written to an external device when the external device is connected to the information processing apparatus and saving the operation log into the external device when necessary. A determination is made as to whether or not content for retrieving an operation log is present in an external device upon detection of connection of the external device. The operation log is retrieved from a holding unit if a result of the determination shows that the user interface control unit is in an error condition. The retrieved operation log is saved into a storage unit of the external device.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: Embodiments of the present invention provide a method, system and computer program product for expression evaluation of content instances of multiple different data models. In an embodiment of the invention, a method for expression evaluation of content instances over multiple different data models comprises loading a schema for a content instance in memory of a computer and evaluating an expression against the content instance. In response to a failure during the evaluation of the expression against the content instance to resolve a reference to an element specified by the expression, an alias reference for the element can be identified in the schema and the evaluation can be completed using the alias reference in lieu of the specified reference.

Abstract: A radio device includes a radio section which transmits a digital signal through a digital communication path, and a baseband processing section which performs a baseband processing on the digital signal received from the radio section, wherein the baseband processing section performs error detection of the digital signal before performing the baseband processing, and wherein, when an error is detected in the digital signal, the baseband processing section performs the baseband processing without waiting for reception of a retransmitted signal from the radio section.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.

Abstract: Disclosed are methods and apparatus for detecting mismatch of ciphering parameters, such as Count-C, in a wireless device and recovery therefrom. The methods and apparatus for detection include examining a predefined ciphered field, such as a Length Indicator field, in one or more received Radio Link Control (RLC) Protocol Data Units (PDUs). Next, a determination of when the field is invalid over a predetermined sample number of PDUs is performed. Mismatch of ciphering parameters can then be determined when a predetermined number of samples of the field detected as invalid exceed a predetermined threshold. Additionally, recovery of PDUs after mismatch detections is disclosed using a range of Hyper-Frame Numbers (HFNs) to decipher buffered PDUs, and then check which of the HFNs eliminate the parameter mismatch by again determining if parameter mismatch occurs using the methods and apparatus for detection.

Abstract: A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.

Abstract: A communications system and method for testing components of an aircraft via Ethernet. The communications system may comprise one or more Ethernet links having software and hardware controls for timing, buffering, and messaging, and a dedicated Ethernet line. The Ethernet links may be configured to communicably link sections of a central communication system of the aircraft, each section being part of a separate aircraft component. The Ethernet links may also communicably link the sections with various databases over the Ethernet line. The databases may comprise loadable software, archived testing data, configuration data, and/or diagnostic data. Any of the central communication system sections and the databases may be located at geographically distant locations from each other, such as at separate production sites. The communications system may allow the aircraft components to test each other, or essentially for the aircraft to test itself prior to its components being physically joined together.

Abstract: A field device for determining a process parameter value, comprising a measurement device for determining a process parameter value; circuitry for determining the reliability of the process parameter value; and signaling circuitry for providing the process parameter value and an indication of the reliability of the process parameter value to a host system via a current loop. The signaling circuitry is configurable between a first state in which the indication of the reliability is provided as a digital signal and the process parameter value is provided as an analog DC-value, and a second state in which the indication of the reliability is provided as a predetermined analog DC-value. Hereby, the number of unplanned process interruptions may be reduced when the host system is capable of receiving digital signals.

Abstract: An image processing apparatus includes an image processing unit configured to perform image processing, a storage unit configured to be capable of storing an application program installed in the image processing apparatus, a first determination unit configured to determine whether the application program had ever been installed in the image processing apparatus, and a control unit configured to selectively control the image processing unit to be operable and control the image processing unit not to operate according to the determination by the first determination unit if an error has occurred in the storage unit.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: When a determination is made that a signal transmitted by a voltage sensor, a second voltage sensor, a current sensor, a temperature sensor, a second temperature sensor, a first CPU, a second CPU and a communication circuit is in error, a third CPU of a motor generator ECU determines that the control system is in error. When a determination is made that the control system is in error, the third CPU determines whether each of the voltage sensors, the current sensor, the temperature sensors, the first CPU, the second CPU and the communication circuit is in error or not.

Abstract: Systems and methods are provided for performing a medical procedure with respect to a subject. A data storage location of the system is pre-programmed with a plurality of subject data entries, each having subject-specific information associated with it. A user interface receives an identity input from a subject, which corresponds to the identity of the subject. A controller is associated with the database and the user interface, and is programmed to compare the identity input to the subject data entries. If the identity input corresponds to the subject-specific information of a subject data entry, the controller commands a treatment device to perform a medical procedure with respect to the subject. Otherwise, if the identity input does not correspond to the subject-specific information of any of the subject data entries, the controller generates an error signal which prevents the performance of the medical procedure with respect to the subject.

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.

Abstract: A computer implemented method for automatically for determining errors in concurrent program using lock localization graphs for capturing few relevant lock/unlock statements and function calls required for reasoning about interference at a thread location at hand, responsive to first and second threads of a concurrent program, constructing generalized lock causality graphs and computing cycle signatures, and determining errors in the concurrent program responsive to computing an interference graph and data flow analysis.

Abstract: This invention provides method for detecting advance signs of anomalies, event signals outputted from the facility are used to create a separate mode for each operating state, a normal model is created for each mode, the sufficiency of learning data for each mode is checked, a threshold is set according to the results of said check, and anomaly identification is performed using said threshold. Also, for diagnosis, a frequency matrix is created in advance, with result events on the horizontal axis and cause events on the vertical axis, and the frequency matrix is used to predict malfunctions. Malfunction events are inputted as result events, and quantized sensor signals having anomaly measures over the threshold are inputted as cause events.

Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.

Abstract: A maintenance free storage container includes a plurality of storage servers, wherein the maintenance free storage container allows for multiple storage servers of the plurality of storage servers to be in a failure mode without replacement. The maintenance free storage container further includes a container controller operable to manage failure mode information of the plurality of storage servers, manage mapping of a plurality of virtual storage servers to at least some of the plurality of storage servers based on the failure mode information, communicate storage server access requests with a device external to the maintenance free storage container using addressing of the plurality of virtual storage servers, and communicate the storage server access requests within the maintenance free storage container using addressing of the plurality of storage servers.

Abstract: An object storage system, such as a content addressed storage system, manages replication of objects across network locations to balance storage space and data security. Network locations set a policy of replicating each object at the object's primary network location and a secondary network location. The secondary network location creates a first replica of the object and a virtual unique identifier representing a second replica of the object at the secondary network location. Creation of the second replica is suppressed unless the first replica becomes invalid so that storage space is conserved without substantially increasing the risk of loss of information represented by the object.

Abstract: A system is configured to monitor a received signal. In response to detecting a fault condition associated with the received signal, the system sets a fault status indicator to indicate occurrence of the detected fault condition. The system sets a state of the fault status indicator for at least a predetermined amount of time to indicate occurrence of the detected fault condition. Subsequent to setting the fault status indicator for at least the predetermined amount of time to indicate the occurrence of the detected fault condition, the system monitors integrity of the signal again. After the predetermined amount of time, in response to detecting that there is no longer a fault associated with the monitored signal, the system modifies the fault status indicator to indicate absence of the fault condition.

Abstract: Determining whether or not an instruction execution part that executes an instruction from a processor meets an error generation condition; when an error setting direction that directs to set an error has been input, outputting a determination direction to determine whether or not the instruction execution part meets the error generation condition, and, in a case where the error generation condition is not met when the error setting direction has been input, again outputting, after a predetermined time has elapsed from the output of the determination direction, the determination direction; and outputting an error generation direction to the instruction execution part in a case where the instruction execution part meets the error generation condition by the determination are carried out.

Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.