Abstract: An information processing device includes a memory unit that stores registration data of a search target and error information indicating an error of the registration data in association with each other. The information processing device includes a search unit that searches for registration data from the registration data stored by memory unit, the registration data searched by the search unit being registration data for which a value obtained by subtracting a value of the error information from a value of distance between query data related to a search request and the registration data is within the predetermined neighborhood range.

Abstract: A method for monitoring a heap in real-time to assess the performance of a virtual machine. A mobile agent is created to be preloaded with boundary settings for each heap metric. Boundary settings are thresholds that are used to diagnose the effectiveness of operation of the heap. The mobile agent is deployed onto an application server to monitor the effectiveness of operation of the heap of a virtual machine within the application server. If a boundary setting for one of the heap metrics is exceeded, then the mobile agent determines whether a non-critical, a critical or a fatal error has occurred. An appropriate response is then performed. By monitoring the heap in real-time, undesirable behavior characteristics of the heap can be detected early thereby allowing remedial actions to be enacted to address such problems before those problems escalate into more serious problems.

Abstract: At an instruction pipeline of a data processor, pipeline resource conflicts are detected by setting, for each executing instruction, one or more assignment indicators to indicate which pipeline resources are to be utilized for executing the instruction. The instruction pipeline detects a pipeline resource conflict if an instruction is assigned a pipeline resource for which the assignment indicator is set. In addition, for selected pipeline resources, such as registers in a register file, the instruction pipeline can detect a pipeline resource conflict if more than one instruction attempts to access the pipeline resource when the assignment indicator for the resource is set. In response to detecting a pipeline resource conflict, the instruction pipeline is flushed and returned to a checkpointed state, thereby protecting the instruction pipeline from architectural state errors.

Abstract: The present invention extends to methods, systems, and computer program products for monitoring the health of distributed systems. Embodiments of the invention provide distributed, self-maintained, continuous health monitoring. Using XML and pluggable infrastructure, a logical view of an appliance can be provided. The logical view abstracts physical implementation details of the appliance. Monitoring agents can correlate different distributed system failures and events and reason over collected health information.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A media player may occasionally be unable to play or continue to play a particular item of media. When that occurs, the media player outputs an error indication that is related to the type of media that the problem media item is representative of. For example, if the problem item is a movie, then the media player may display an error indication having the appearance of broken movie film. If the problem media item is music, then the media player may display an error indication having the appearance of a broken compact disc (“CD”). Thus whatever the type of media that is not playing, the media player outputs an error indication that is appropriate for that type of media. The error indications output by the player are therefore context-based or media-appropriate.

Abstract: Detecting a fault in the operation of a computer having a processor and a memory is taught. Instrumentation code is placed within an application program during compilation, and runtime library routines are modified to support detection of invalid memory accesses. Memory space is divided into application, shadow and unmapped memories. When accessing application memory at an original address, an address in shadow memory is computed by shifting the address and adding an offset. If the value stored at the shadow address indicates that the original address is invalid (e.g., not allocated or already freed), then error reporting code is executed that indicates the type of error and the location and optionally halts the computer. Invalid memory references to heap, stack and global objects in application memory can be detected.

Abstract: According to one embodiment, a memory system has a data transfer device which includes a first command generating unit, a second command generating unit, a first storage unit, a second storage unit, and a nonvolatile memory managing unit. The first command generator generates a first command for reading out data from a nonvolatile memory to a host apparatus. The second command generator generates a second command for internal processing of the memory system associated with a temporary memory and the nonvolatile memory. The first memory has a queue structure configured to store the first command. The second memory has a queue structure configured to store the second command. The memory manager is configured to read out the first command stored in the first memory in priority to the second command stored in the second memory and to transmit read-out command to the nonvolatile memory.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Abstract: A system includes at least one monitored device collect data detect and detect an error in the data, a central server, and at least one local server communicatively coupled to the monitored device and the central server. The local server is configured to receive the data and an indication of the error detected from the monitored device, determine a solution for use in resolving the error, transmit instructions to perform the solution to the monitored device, and transmit the error and the solution to the central server for storage.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value.

Abstract: In a storage system, when a recovered error occurred upon access to a storage apparatus, a data redundancy determination unit determines whether data to be accessed has redundancy. When the data is determined to have no redundancy, an anomaly-occurring portion determination unit determines that the storage apparatus is not an anomaly-occurring portion and at the same time, an error history determination unit determines whether a recovered error occurred at the time of the past access to the storage apparatus other than that of the access destination. The anomaly-occurring portion determination unit determines whether a common transmission path is the anomaly-occurring portion based on the determination result of the error history determination unit.

Abstract: A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs and provides accurate performance monitoring information. When a hypervisor signals that a task is being resumed and the application privilege level has been entered, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state, a state due to execution of the operating system or hypervisor, or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects branch information in a current program execution trace.

Abstract: In an embodiment, provided is a communication device connected to time servers via a network with transfer devices. In the communication device: a network controller receives a message containing time information counted by the time server and containing a network identifier, and obtains a receiving timing of the message; a network processing unit, when the network identifier in the message does not match with any network identifier, destroys the message; a protocol processing unit, when the network identifier has a match, calculates a time error by the time information in the message and the receiving timing, detects whether a first time server is malfunctioning, and when detected the first time server malfunctioning, outputs the time error calculated by a network identifier assigned to a second time server; a servo calculates an operation amount by the time error; and a clock varies a clock rate according to the operation amount.

Abstract: A method of detecting errors in road characteristics in a transportation network database includes collecting sequential location measurements from probes traversing between two end points, fitting trace segments having a curved or linear shape between the sequential location measurements collected from the probes to form a probe trace, comparing a position of the probe traces with a position of a calculated path between the two end points, where the calculated path is formed from linked transportation network segments each of the linked transportation segments having a curved or linear shape, where the calculated path follows the road characteristics defined by the attributes associated with the linked transportation segments, and identifying a potential error in the attributes if a probe trace deviating in position from the calculated path is greater than a deviation threshold.

Abstract: According to one embodiment, a method may include generating a first plurality of Service Operation, Administration, and Management (SOAM) flows intended for a working port and a second plurality of SOAM flows intended for a protection port, wherein the working port and the protection port form a link aggregation group, determining whether each of the working port and the protection port is an active port or an inactive port, dropping all of the first plurality of SOAM flows if the working port is the inactive port, communicating all of the first plurality of SOAM flows to the working port if the working port is the active port, dropping all of the second plurality of SOAM flows if the protection port is the inactive port, and communicating all of the second plurality of SOAM flows to the protection port if the protection port is the active port.

Abstract: In a method for intelligently monitoring and dispatching an Information Technology (IT) service alert, a computer receives a service error alert and classifies the service error alert. The computer assigns the service error alert, based on the service error alert class. The computer monitors the progress of the resolution of the service error alert.

Abstract: A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.

Abstract: Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location. A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.

Abstract: A connector assembly comprises a plurality of ports. Each of the plurality of ports is configured to receive a respective connector attached to a respective segment of physical communication media. Each of the plurality of ports comprises a respective media interface configured to receive data from a respective storage device attached to the respective connector. The connector assembly is configured to determine if a first connector attached to a first port included in the plurality of ports is defective by determining if a signal level received on the respective media interface associated with the first port has stabilized after a first predetermined amount of time has elapsed since the first connector was connected to the first port. If the signal level has not stabilized after the first predetermined amount of time has elapsed since the first connector was connected to the first port, the first connector is considered defective.

Abstract: The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

Abstract: A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.

Abstract: A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.

Abstract: Execution behavior for processes within a virtual machine is recorded for subsequent replay. The execution behavior comprises a detailed, low-level recording of state changes for processes within the virtual machine. The low-level recording is processed via replay to produce a sliced recording that conforms to time, abstraction, and security requirements for a specific replay scenario. Multiple stages of replay may be arbitrarily stacked to generate different crosscut versions of a common low-level recording.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.

Abstract: The processing load caused by fault monitoring of software components is reduced. Provided is a computing unit (3) that includes an operating system (32) and that is connected with another computing unit via an information transmitting medium (2) in a mutually communicable manner, wherein availability management middleware (31) that is interposed between a software component and the operating system (32) and that launches the software component as a child process, thus serving as a parent process of the software component; the operating system (32) monitors a running status of the software component and reports abnormality information for the software component to the availability management middleware (31) in the case in which an abnormality is detected in the software component; and, upon acquiring the abnormality information, the availability management middleware (31) reports the abnormality information for the software component to the other computing unit.

Abstract: The described embodiments include a processor with a fault status register (FSR) that executes a Confirm instruction. In these embodiments, when executing the Confirm instruction, the processor receives a predicate vector that includes N elements. For a first set of bit positions in the FSR for which corresponding elements of the predicate vector are active, the processor determines if at least one of the first set of bit positions in the FSR holds a predetermined value. When at least one of the first set of bit positions in the FSR holds the predetermined value, the processor causes a fault in the processor.

Abstract: Methods and apparatus are described for an aircraft network that permits an automatic configuring and/or repairing of the network.

Abstract: An information processing apparatus including a storage area separated into a user space and a kernel space executes, generating a core file of a process existing in the user space, retaining the process with the core file which starts being generated in the user space, and notifying a monitor unit of an identification number of the process with the core file which starts being generated, wherein the monitor unit detects a fault in the process by receiving the identification number allocated to the process.

Abstract: An embodiment of the invention provides a method for managing errors on a bus. Information read from a source is encoded. The encoded information is transmitted on a channel that is part of the bus. The encoded information is evaluated. When no errors are detected, the decoded information is provided to a target. When the decoded information has an error or errors that can not be corrected, the source is asked to present the information to the bus again. When an error or errors can be corrected, the corrected information is sent to the target.

Abstract: A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract: A nonvolatile memory device includes a first storage unit configured to store a plurality of first fault address information provided in a first test operation, a second storage unit configured to store a plurality of second fault address information provided in a second test operation which is performed later than the first test operation; a redundancy operation unit configured to, in performing a redundancy operation, determine the number of operation circuits corresponding to the first fault address information and the number of operation circuits corresponding to the second fault address information among a plurality of redundancy operation circuits based on address number information; and an address providing unit configured to read the plurality of first fault address information and the plurality of second fault address information, and sequentially provide the read information to the redundancy operation unit, wherein the address providing unit is further configured to detect the number of the first f

Abstract: A backup image generator can create a primary image and periodic delta images of all or part of a primary server. The images can be sent to a network attached storage device and a remote storage server. In the event of a failure of the primary server, the failure can be diagnosed to develop a recovery strategy. Based on the diagnosis, at least one delta image may be applied to a copy of the primary image to generate an updated primary image at either the network attached storage or the remote storage server. The updated primary image may be converted to a virtual server in a physical to virtual conversion at either the network attached storage device or remote storage server and users may be redirected to the virtual server. The updated primary image may also be restored to the primary server in a virtual to physical conversion. As a result, the primary data storage may be timely backed-up, recovered and restored with the possibility of providing server and business continuity in the event of a failure.

Abstract: Various embodiments provide a guard mechanism that is configured to prevent transmission of synchronous function calls to hung application components. In at least some embodiments, a hang resistance application layer intercepts a synchronous function call that is intended for an application component. Before permitting the synchronous function call to be transmitted to the application component, the hang resistance application layer determines whether the application component is hung by transmitting a message other than the synchronous function call to the application component that requests that a response be received before transmission of the synchronous function call to the application component is permitted. Responsive to determining that the component is hung, a hung component recovery process is initiated.

Abstract: An apparatus and a method for decoding bits of a received signal in a communication system are provided. The method includes determining path metrics of respective states in a trellis corresponding to the received signal, selecting a start state in the trellis for a traceback in a last window of the trellis, repeating the traceback at least twice within the last window, and when the repeating of the traceback is completed, determining the decoded bits of the received signal using a survived path of a last traceback.

Abstract: A circuit for detecting and recording chip fails according to one embodiment of the present invention comprises a common error bus, a plurality of fail detector modules and a control center. Each of the plurality of fail detector modules is configured to receive at least a data signal to determine an occurrence of a chip fail and to correspondingly broadcast a fail code on the common error bus when the common error bus is not busy. The control center is configured to record a fail code from the common error bus and to report the recorded fail code when required.

Abstract: System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.

Abstract: The disclosure discloses an alarm report method for cascaded equipments, comprises: after receiving link alarm information, a radio equipment determines the source of the link alarm information; the radio equipment selects one link alarm information report mode from multiple predetermined link alarm information report modes according to the result of determining the source; the radio equipment reports the link alarm information to a Radio Equipment Controller (REC) according to the selected link alarm information report mode. The disclosure further discloses an alarm report system and device for cascaded equipments. The disclosure can effectively lower the alarm information processing complexity of an REC and the correlation of alarms.

Abstract: A method and apparatus for backing up user information are disclosed. The method includes: establishing a plurality of selection switch protocol groups between a same port of a standby service node and ports of a plurality of main service nodes respectively; the standby service node regularly receiving user information of access users from the ports of the plurality of main service nodes, and storing the user information to a main control unit of the standby service node; keeping a detection relation between the same port of the standby service node and the ports of the plurality of main service nodes; the standby service node sending to an interface unit of the standby service node the user information of the access user of that port stored in the main control unit, and according to the selection switch protocol, switching the same port of the standby service node to be main.

Abstract: A system and method for manipulation of event data, such as errors, in a networked environment. The method includes receiving event signal data indicative of an event, and associating descriptive data with the event signal data. The descriptive data is then mapped to one or more associated connections. A determination is made whether to post identifier data corresponding to the event signal data. This determination is made as a function of predetermined criteria. If a determination is made to post the identifier data, the particular identifier data is posted. The posted identifier data may be selectively retrieved and output in a specified format. The identifier data may be stored in a memory. Descriptive data may be accumulated for a plurality of events subsequent to the mapping step. An alert condition may be established based on the type of event that has occurred.

Abstract: Techniques for meta-directory control and evaluation of events are provided. Disparate events from heterogeneous processing environments are collected as the events are produced by resources within the processing environments. The events are filtered and organized into taxonomies. Next the filtered and organized events are assigned to nodes of a Meta directory, each node defining a relationship between two or more of the resources and policy is applied. Finally, additional policy is evaluated in view of the events and their node assignments with other events, and one or more automated actions are then taken.

Abstract: Described herein are systems and methods for fast boot from non-volatile (“NV”) memory. The exemplary embodiments relate to systems and methods for significant improvements in performance speed with simple implementations. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to identify a page fault, determine whether the page fault occurred due to a read from a NV memory, copy a page from the NV memory to a random-access memory (“RAM”) storage, and create an identity mapping for the page in the RAM storage.

Abstract: A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory cells are programmed to produce a verification result, determining whether all of the plurality of the memory cells are programmed in response to the verification result to produce a first determination result and determining whether at least a first number of memory cells are programmed among the plurality of the memory cells in response to the first determination result to produce a second determination result.

Abstract: A method for monitoring and controlling, industrial or building automation to detect anomalies in a control network, wherein a technology of an intrusion detection system (IDS) is configured to analyze a time sequence and time intervals of correct messages in the network traffic and to use the messages to train an anomaly detection system. Detecting a time sequence and a rhythm of correct messages allows for the detection of malfunctions or manipulations of devices and attacks that are performed using regular monitoring or control stations that have been taken over by attackers or that are defect, and that cannot be detected using content-based methods or by a considerable increase of data traffic. An additional security barrier is thus provided that can continue monitoring and protecting a technical unit from possible acts of sabotage, even if the control network of the technical unit has already been corrupted.

Abstract: The present invention relates to a home appliance diagnosis system and to a method for operating same, wherein product information is output in a predetermined signal sound by a home appliance product, and the signal sound is transmitted via a communication network connected to a remote service center to enable the service center to easily check the state of the home appliance product. In addition, the product information is encoded into a predetermined format and modulated to enable sound to be outputted by the home appliance product, thereby preventing noise or signal errors. The present invention enables stable signal modulation and accurate sound output, and enables the easy recovery of the sound transmitted to the service center via the communication network.

Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.

Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.

Abstract: Methods, apparatus, and products for visually marking computing components within a computing system are disclosed that include: detecting that a particular computing component has failed, wherein the particular computing component has a physical surface that may be altered with the application of some physical stimulus; and applying a requisite physical stimulus to the physical surface such that the appearance of the physical service is altered, thereby visually identifying that the component has failed.