Abstract: A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.
August 24, 2011
February 28, 2013
ORACLE INTERNATIONAL CORPORATION
Ramaswamy SIVARAMAKRISHNAN, Aaron S. WYNN, Connie Wai Mun CHEUNG, Satarupa BOSE
Abstract: A serial processing method and a parallel processing method of bit rate matching and apparatuses thereof are disclosed in the present invention. The serial processing method includes: receiving a system bit data stream, a check 1 data stream and a check 2 data stream, performing interleaving processing on the system bit data in the received system bit data stream, and caching in a first buffer cache of a storage; simultaneously performing interleaving processing on the corresponding data in the received check 1 data stream and the received check 2 data stream, and caching the data on which the performing interleaving processing is performed in a second buffer of the storage; and reading valid data from the storage and implementing the rate matching.