Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells, and a controller configured to control an operation of the semiconductor memory device and communicate with a host. The controller includes a condition storage, a condition monitor, and a host interface. The condition storage stores at least one condition related to an internal state of the memory system. The condition monitor monitors whether the at least one condition is satisfied, and outputs a confirmation signal when the at least one condition is satisfied. The host interface outputs a condition confirmation message indicating that the at least one condition is satisfied to the host, in response to the confirmation signal.

Abstract: Data storage devices function by communication between a controller and a memory device over a data bus. The memory device can, at times, be busy. Attempting to communicate with the memory device while the memory device is busy causes delays. Holding back communications when the memory device is not busy causes avoidable delays. Correctly predicting the timing of when the memory device is available will reduce delays. An adaptive prediction timer is used that increases the time between communications if a status check of the memory device returns a busy indication, and decreases the time between communications if the status check returns a not busy indication.

Abstract: According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.

Abstract: A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.

Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Abstract: A control system and a control method are provided. The control system provides a first setting signal in response to an abnormal read-write operation performed on at least one storage device. The control system generates a first state signal having a first logic value in response to the first setting signal and latches the first state signal, and disables the at least one storage device on which the abnormal read-write operation is performed in response to the first state signal having the first logic value. The control system includes a restart input module. The restart input module converts the first logic value of the latched first state signal into a second logic value, so that the control system restarts the at least one storage device disabled in response to the first state signal having the second logic value.

Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a system may include components configured for monitoring health or life expectancy of the memory device, such as components that perform comparisons between signals or other operating characteristics resulting from operating at the memory device and one or more threshold values that may be indicative of a life expectancy of the memory device. In various examples, a memory device may perform a subsequent operation based on such a comparison, or may provide an indication of a life expectancy to a host device based on one or more comparisons or determinations about health or life expectancy.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.

Abstract: A memory device to use added known data as part of data written to memory cells with redundant data generated according to an Error Correction Code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.

Abstract: A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Abstract: A storage device having improved operation speed may include a main memory configured to store first to N-th meta data, a cache memory including first to N-th dedicated areas respectively corresponding to areas in which the first to N-th meta data are stored, and a processor configured to store data accessed according to requests provided from a host among the first to N-th meta data in the first to N-th dedicated areas, respectively. A size of the first to N-th dedicated areas may be determined according to the number of times each of the first to N-th meta data is accessed by the requests.

Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.

Abstract: An offset address generator generates a plurality of offset addresses at an interval of a basic processing unit size on the basis of an access destination address from a calculating circuit, partitions an access destination memory region from the calculating circuit to set a plurality of verification address ranges. A determiner sequentially determines whether the plurality of set verification address ranges are matched with a monitoring target address. With this configuration, it is possible to simplify the configuration of a debug function in a processor.

Abstract: A compression engine calculates replacement CRC codes, in predetermined data lengths, for DIF-in cleartext data including cleartext data and multiple CRC codes based on the cleartext data. The compression engine generates headered compressed-text data in which a header including the replacement CRC codes is added to compressed-text data in which the cleartext data is compressed, and generates code-in compressed-text data by calculating multiple CRC codes based on the headered compressed-text data to add the calculated CRC codes to the headered compressed-text data.

Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.

Abstract: Flash memory devices and associated methods are described for controlling data errors in the devices through various forms of decoding, error correction, and wear concentration. To this end, a flash memory device may be partitioned into a plurality of sectors. Data may then be received from, for example, a host processor for storage within the flash memory device. Storage durations of the data are then estimated and the data is stored in the data sectors based on those estimated storage durations.

Abstract: A memory includes cells at intersections of word lines and bit lines, word and bit line selection mechanisms and a programming mechanism. The cells on each bit line are connected in series. Cells of a word line are programmed simultaneously. For low-power reading, only some of the bit lines that intersect the word line at the programmed cells are selected and only the cells at those intersections are sensed. Another type of memory includes a physical page of cells, a sensing mechanism and a selection mechanism. Hard bits are sensed from all the cells of the physical page. Only some of those cells are selected for sensing soft bits. Another memory includes a plurality of cells, a sensing mechanism, an export mechanism and a selection mechanism. Hard and soft bits are sensed from all the cells of the plurality. Only some of the soft bits are selected for export.

Abstract: Multiple copies of firmware code for controlling operation of a non-volatile flash memory system are stored at different suitable locations of the flash memory of a memory system. A map of addresses of these locations is also stored in the flash memory. Upon initialization of the memory system, boot code stored in the memory controller is executed by its microprocessor to reference the address map and load one copy of the firmware from the flash memory into a controller memory, from which it may then be executed by the microprocessor to operate the memory system to store and retrieve user data. An error correction code (ECC) is used to check the data but the best portions of the two or more firmware copies stored in the flash memory are used to reduce the need to use ECC. The firmware code may be stored in the flash memory in two-states when user data is stored in the same memory in more than two-states.