Abstract: A data transmitter includes: a packetization unit receiving primary data from a data processor and packetizing the primary data; a high-speed transmission unit transmitting a data packet obtained from the packetization to a display device in a high-speed mode; and a low-speed transmission unit relaying and transmitting secondary data between the data processor and the display device in a low-speed mode. Accordingly, it is possible to transmit and receive data rapidly and efficiently.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: A semiconductor memory controller, which outputs data to be stored in a memory unit to the memory unit via a bus of N-bit width (N is an even number), executes a duplexing process on the data to generate duplicated data, simultaneously outputs the respective duplicated data to two different sections of the memory unit using N/2 bit width for each duplicated data, and stores the duplicated data in the two sections of the memory unit, respectively.

Abstract: A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed.

Abstract: An apparatus and method for hybrid automatic repeat request (HARQ) encoding comprising re-encoding a subpacket from a plurality of subpackets to obtain a codeword; maintaining a set of state variables for each of the plurality of subpackets; initializing the set of state variables at HARQ transmit start; updating the set of state variables at HARQ transmit end; and using the set of updated state variables to determine a portion of the codeword to be transmitted.

Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Abstract: Evaluating the operating safety of a complex software and or hardware system such as a system for displaying flight information on an instrument panel of an aircraft. The evaluation method includes construction of a first architecture of the system, divided into several blocks each comprising data inputs/outputs, the inputs of a block being connected to the outputs of other blocks in the first architecture; identification of failures of the outputs of the blocks of the architecture; construction of first boolean expressions expressing the states of the outputs of the blocks of the first architecture as a function of the states of the identified failures, of the states of the inputs of the blocks; definition of a first feared event to be examined by a second boolean expression constructed based on the first boolean expressions; and reduction of the second boolean expression in a sum of monomials.

Abstract: A stopping rule for Turbo decoding that is applied for both good and bad code blocks is disclosed. If the iteration either converges or diverges, decoding is terminated. In an alternative embodiment, the result of the stopping rule testing may be used for H-ARQ acknowledgement generation: if the iteration converges, an ACK is generated and if the iteration diverges, a NACK is generated. Optionally, the maximum number of decoding iterations may be dynamically selected based on MCS levels.

Abstract: Providing extended or end-to-end data integrity through layers of a system. In one aspect, information is to be transmitted between an application end of the system and a physical storage medium that stores the information for a database of the system, the information to be transmitted via a database server in a database server layer of the system. At least a portion of data protection is provided for the information, the data protection causing the information to be protected from corruption between a system layer and the physical storage medium, where the system layer is a separate layer provided closer to the application end of the system than the database server layer.

Abstract: Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver.

Abstract: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that is subsequently used in decoding a second page.