Removing Defective Units From Operation (epo) Patents (Class 714/E11.085)
  • Patent number: 11809605
    Abstract: An intrusion detection and recovery system includes a copying module that creates a point-in-time copy of a storage level logical unit, the point-in-time copy including a volume copy of the storage level logical unit and signatures of the storage level logical unit, a comparison module that compares at least a portion of the point-in-time copy with a previous copy of the storage level logical unit, a judging module that, based on results of the comparison module, judges if a modification has occurred. A signature of the point-in-time copy is compared with a signature of the previous copy to detect a sign of an intrusion. The signatures of the storage level logical unit include encoded data of files of the storage level logical unit that are monitored in the point-in-time copy.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: November 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, Mohammad Banikazemi, Dan Edward Poff
  • Patent number: 11714752
    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: August 1, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Christopher Haywood
  • Patent number: 11693592
    Abstract: A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 4, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Takahiro Miomo, Prashob Ramachandran Nair, Hajime Yamazaki, Makoto Domon, Yasunori Nakamura
  • Patent number: 11592993
    Abstract: Establishing data reliability groups within a geographically distributed data storage environment is presented herein. A system can comprise a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising: partitioning geographically distributed data storage zones into reliability groups, in which a reliability group of the reliability groups comprises a group of storage zones comprising a defined amount of the geographically distributed data storage zones; and facilitating a replication of data of the group of storage zones using a portion of remaining data of the group of storage zones.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: February 28, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Gregory Skripko
  • Patent number: 11573718
    Abstract: A network device includes at least one control path port and data path ports configured to communicate on a network. A connection request is received from a host via a control path port, and a resource of the network device is allocated to the host. A data path port is determined from among the plurality of data path ports for communication between the host and the allocated resource. An indication of the determined data path port is sent to the host via the control path port for communication on a data path between the host and the allocated resource. In one aspect, a network interface includes at least one control path port and a first plurality of data path ports configured to communicate on a network. A connection request is received from a host via a control path port, and a locally connected device is allocated to the host.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: February 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Qingbo Wang, Martin Lueker-Boden, Dejan Vucinic
  • Publication number: 20140082438
    Abstract: A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Hyunsu YOON, Youncheul Kim, Kwanweon Kim, Jeongtae Hwang
  • Publication number: 20130339785
    Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh
  • Publication number: 20130339808
    Abstract: Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Michael A. Blake, Michael Fee, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill
  • Publication number: 20130311822
    Abstract: In accordance with embodiments of the present disclosure, a system comprising may include a storage controller and a plurality of storage resources communicatively coupled to the storage controller. At least one storage resource of the storage resources may be capable of performing storage resource-level failure protection and configured to disable storage resource-level failure protection in response to a determination that the at least one storage resource is a member of a redundant storage array.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Applicant: Dell Products L.P.
    Inventors: Gary B. Kotzur, Kevin Marks
  • Publication number: 20130232377
    Abstract: In a storage sub-system adopting a redundant configuration for preventing data loss and continuing processing during failure, when failure occurs, a controller unit in which failure has occurred is blocked so as not to affect the normal controller unit, so that the performance of the storage sub-system is deteriorated and the redundancy thereof is lost until maintenance and component replacement is performed. According to the present invention, self diagnosis of the blocked area is executed and a failure area is isolated. Then, the blocked area is reconnected to the storage sub-system, so as to prevent deterioration of performance and overload of the device until maintenance and replacement is performed, and to reduce the time of failure analysis during maintenance by specifying the detailed failure area via self diagnosis.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: HITACHI, LTD.
    Inventors: Shinobu Kakihara, Makoto Masuda, Mitsuhide Sato
  • Publication number: 20130138995
    Abstract: A method for managing multiple nodes hosting multiple memory segments, including: identifying a failure of a first node hosting a first memory segment storing a hypervisor; identifying a second memory segment storing a shadow of the hypervisor and hosted by a second node; intercepting, after the failure, a hypervisor access request (HAR) generated by a core of a third node and comprising a physical memory address comprising multiple node identification (ID) bits identifying the first node; modifying the multiple node ID bits of the physical memory address to identify the second node; and accessing a location in the shadow of the hypervisor specified by the physical address of the HAR after the multiple node ID bits are modified.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: Oracle International Corporation
    Inventors: Ramaswamy Sivaramakrishnan, Jiejun Lu, Aaron S. Wynn
  • Publication number: 20130086417
    Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Inventors: Ramaswamy Sivaramakrishnan, Ali Vahidsafa, Aaron S. Wynn, Connie W. Cheung
  • Publication number: 20130080826
    Abstract: Disclosed herein is a semiconductor device that includes a verification circuit and an error processing circuit. the verification circuit verifies second bits of an external command to generate the verification result signal. The error processing circuit supplies a follow-up signal to a bank control circuit after a lapse of a first period and a second period when the verification result signal indicates a fail state during a write operation. The first period corresponds to a write latency indicating a period between when a write command is generated and when a data associated with the write command is supplied from outside. The second period corresponds to a write recovery latency indicating a period between when the bank control circuit issues a write execution signal to start writing the data to memory cells and when the write operation is completed.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 28, 2013
    Applicant: Elpida Memory, INC.
    Inventor: Elpida Memory, INC.
  • Publication number: 20130073898
    Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.
    Type: Application
    Filed: November 13, 2012
    Publication date: March 21, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Micron Technology, Inc.
  • Publication number: 20130036327
    Abstract: An apparatus, system, and method are disclosed for reconfiguring an array of solid-state storage elements. The method includes determining that one or more storage elements are unavailable to store data. The storage elements are configured in an array of N storage elements that each store a portion of a first ECC chunk and P storage elements that store first parity data corresponding to the first ECC chunk. The method includes generating a second ECC chunk comprising at least a portion of the data of the first ECC chunk. The method includes storing the second ECC chunk and associated second parity data across (N+P)?Z storage elements where 1?Z?P.
    Type: Application
    Filed: October 4, 2012
    Publication date: February 7, 2013
    Applicant: FUSION-IO, INC.
    Inventor: Fusion-io, Inc.
  • Publication number: 20120304000
    Abstract: A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.
    Type: Application
    Filed: October 13, 2011
    Publication date: November 29, 2012
    Applicants: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS S.R.L.
    Inventors: Sudeep BISWAS, Angelo DI SENA, Domenico MANNA
  • Publication number: 20120266016
    Abstract: A memory address remapping architecture is applied to execute an address remapping method for repairing a main memory. A valid flag and an essential flag in a TCAM corresponding to at least one subcube address in a spare memory are initialized, and the main memory is checked to find out some faulty cell addresses. The Hamming distance between the subcube address and the faulty cell address is calculated, and the faulty cell address is merged into the subcube address by a masked bits concentrator when the Hamming distance is not larger than an address-width degree of the subcube address and the merged number of the subcube address is not larger than a threshold value.
    Type: Application
    Filed: October 7, 2011
    Publication date: October 18, 2012
    Applicant: NATIONAL CHANGHUA UNIVERSITY OF EDUCATION
    Inventor: Tsung-Chu HUANG
  • Publication number: 20120159094
    Abstract: Techniques are provided for assigning read requests to storage devices in a manner that reduces the likelihood that any storage device will become overloaded or underutilized. Specifically, a read-request handler assigns read requests that are directed to each particular item among the storage devices that have copies of the item based on how busy each of those storage devices is. Consequently, even though certain storage devices may have copies of the same item, there may be times during which one storage device is assigned a disproportionate number of the reads of the item because the other storage device is busy with read requests for other items, and there may be other times during which other storage device is assigned a disproportionate number of the reads of the item because the one storage device is busy with read request for other items.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Willliam H. Bridge, JR., Prasad Bagal, Lavina Jain, Rajiv Wickremesinghe, Darshan Nagarajappa, Richard L. Long
  • Publication number: 20120151254
    Abstract: Redundant “parity” RAID (5, 6, 50, 60) is a well-known technique for increasing data reliability beyond the failure rate of an individual storage device. In many implementations of redundant RAID, when a storage element is lost, a replacement or spare element is required to restore redundancy. A typical solid state storage device is over-provisioned with more storage media than is required to satisfy the specified user capacity. Embodiments of the present invention utilize the additional over-provisioned capacity and potentially modify the stripe size to restore RAID redundancy when a storage element or path (i.e., page, block, plane, die, channel, etc.) has failed. In some cases, this may also involve reducing the RAID stripe size.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: ROBERT L. HORN
  • Publication number: 20120137169
    Abstract: A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a method comprises: seeking a defect entry whose state information indicates that a defect block or a replacement block has been re-initialized without certification from a defect list for managing an information storage medium and including state information of the defect block and state information of the replacement block, wherein the medium includes a spare area for recording the replacement block to replace the defect block occurring in a user data area on the medium; and certifying the defect block or the replacement block registered in the sought defect entry. As a result, defect information can be effectively rearranged for quick re-initialization without certification in order to improve the performance of a drive system.
    Type: Application
    Filed: February 8, 2012
    Publication date: May 31, 2012
    Inventors: Sung-hee HWANG, Jung-wan KO, Hyo-lin SUNG
  • Publication number: 20120131382
    Abstract: A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.
    Type: Application
    Filed: September 7, 2011
    Publication date: May 24, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Masanori HIGETA
  • Publication number: 20120072767
    Abstract: A disk recovery system and method is provided for recovering data from a redundant array of independent (or inexpensive) disks. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The computer readable storage medium is operable to: determine input/output (I/O) characteristics of one or more disks in an array; monitor the one or more disks in the array to determine when any of the one or more of the disks have failed in the array; and automatically rebuild the failed disk from a standby pool by nominating a disk in the standby pool based on the I/O characteristics of the one or more failed disks prior to failure.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhinay R. NAGPAL, Sandeep R. PATIL, Sri RAMANATHAN, Matthew B. TREVATHAN
  • Publication number: 20120054539
    Abstract: A restarting method restarts a computing device when the computing device has a memory error. The computer device include a central processing unit (CPU) comprising a memory controller, a baseboard management controller (BMC) comprising a storage module, and a basic input output system (BIOS). The memory controller records error information of the memory module. A BMC reads the error information of the memory module from the memory controller of the CPU and saves the error information into a storage module of the BMC. The BIOS reads the error information from the storage of the BMC to determine a first memory module from the one or more memory modules that has a memory error. The BIOS sets a command in the CPU to avoid the memory controller to access the first memory module when the computing device is restarted.
    Type: Application
    Filed: August 5, 2011
    Publication date: March 1, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: YU-GANG ZHANG
  • Publication number: 20120054541
    Abstract: Systems and methods are provided for handling errors during device bootup from a non-volatile memory (“NVM”). A NVM interface of an electronic device can be configured to detect errors and maintain an error log in volatile memory while the device is being booted up. Once device bootup has completed, a NVM driver of the electronic device can be configured to correct the detected errors using the error log. For example, the electronic device can move data to more reliable blocks and/or retire blocks that are close to failure, thereby improving overall device reliability.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 1, 2012
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Kenneth Herman, Nir J. Wakrat, Daniel J. Post
  • Publication number: 20120042203
    Abstract: A storage system includes plural storage devices, a controller configured to transmit an access request for controlling an access to at least one of the storage devices, a switching part configured to receive the access request from the controller to select the one of the storage devices based on the access request received from the controller, and a proxy response part configured to transmit, if the selected storage device has failed, a response to the access request instead of the failed storage device responding.
    Type: Application
    Filed: May 26, 2011
    Publication date: February 16, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Daiya NAKAMURA
  • Publication number: 20110302445
    Abstract: Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.
    Type: Application
    Filed: July 23, 2010
    Publication date: December 8, 2011
    Applicant: Apple Inc.
    Inventors: Matthew Byom, Daniel Post, Vadim Khmelnitsky
  • Publication number: 20110289347
    Abstract: A copy export application implemented in a computational device receives a request to perform a copy export operation of data and metadata to a selected tape in a tape library coupled to the computational device. The copy export application copies the data from the computational device to the selected tape. The copy export application determines a medium error on the selected tape while copying the metadata from the computational device to the selected tape, subsequent to completion of the copying of the data from the computational device to the selected tape. The copy export application sends a request to a tape control application to replace the selected tape by a new tape and copy the data from the selected tape to the new tape. The copy export application copies the metadata to the new tape.
    Type: Application
    Filed: May 18, 2010
    Publication date: November 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Norie Iwasaki, David Michael Morton, Yun Mou, Laura Jean Ostasiewski, Takeshi Sohda
  • Publication number: 20110246818
    Abstract: A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting.
    Type: Application
    Filed: May 13, 2011
    Publication date: October 6, 2011
    Applicant: Hitachi, Ltd.
    Inventors: Masanori Takada, Shuji Nakamura, Kentaro Shimada
  • Publication number: 20110239040
    Abstract: A method for controlling a system includes receiving an indication that an operation has failed in a secondary storage device, suspending data operations sent to the secondary data storage device from a primary storage device, determining a failure policy set by a user, and initiating a first policy responsive to determining that the first policy is active, the first policy including sending a status query to the secondary storage device, determining whether a response has been received from the secondary storage device, determining whether the response indicates a failure of the secondary storage device responsive to determining that the response has been received from the secondary storage device, and continuing processing tasks on the server and data operations on the primary storage device responsive to determining that the response indicates a failure of the secondary storage device.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David B. Petersen, Gail A. Spear
  • Publication number: 20110185226
    Abstract: A RAID group is configured and operated by using multiple storage drives 171 and expanders 112 and 121 connected with the storage drives 171. If a failure related to any storage drive 171 is detected, a storage system 10 which issues a broadcast and a discover command to the communication path of the storage drive 171 manages a broadcast inhibiting flag for setting the information showing whether to inhibit transmission of broadcast per storage drive 171. If a failure occurs to a storage drive 171 constituting a RAID group whose redundancy is lost, the storage system 10 sets the broadcast inhibiting flag to inhibiting the broadcast transmission, and if a failure related to the storage drive 171 occurs and the broadcast inhibiting flag of the storage drive 171 is being set to inhibiting the transmission, inhibits the transmission of the broadcast.
    Type: Application
    Filed: June 2, 2009
    Publication date: July 28, 2011
    Inventors: Yusuke Douchi, Hiroshi Izuta
  • Publication number: 20110161728
    Abstract: A disk array apparatus capable of reducing a disk drive fault rate where a time-out failure has occurred. The disk array apparatus includes a plurality of disk drives, and a control unit for performing data input/output processing of the disk drives in response to a data input/output request from a host system. The control unit includes: a memory for storing control information for specifying a failure of at least one of the disk drives, and failure information of the faulty disk drive, a circuit for specifying, from the failure information, the disk drive in which a time-out failure has occurred, and issuing an instruction to retry a control command to the disk drive, and a circuit for outputting a control signal to the faulty disk drive in order to hard reset the disk drive if the disk drive does not recover from the failure.
    Type: Application
    Filed: March 7, 2011
    Publication date: June 30, 2011
    Inventors: Azuma KANO, Xiaoming Jiang
  • Publication number: 20110107020
    Abstract: An embedded device is hibernated by storing state data of the embedded device to a non-volatile data storage medium, and powering off the embedded device. The embedded device is later woken up in response to the detection of a wakeup event from a wakeup source. The state data stored in the RAM of the embedded device comprises data in one or more registers of a Central Processing Unit (CPU) of the embedded device, one or more registers of a system-on-chip (SOC) of the embedded device, and the system and applications code and data. Waking the embedded device comprises loading, from the non-volatile data storage medium, initial memory sections that are used to run a kernel of the embedded device. State data that is stored in the RAM of a system may be compressed by dividing the RAM into a plurality of sections and independently choosing, for each section in the plurality of sections, a corresponding compression arithmetic.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Inventor: Binghua DUAN
  • Publication number: 20110072302
    Abstract: A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.
    Type: Application
    Filed: September 24, 2009
    Publication date: March 24, 2011
    Applicant: AgigA Tech Inc.
    Inventor: Ronald H. Sartore
  • Publication number: 20110066881
    Abstract: Method and computer program product for identifying a primary disk storage medium that is higher in a boot order than a secondary disk storage medium in a software RAID, and testing for a hardware failure of the primary disk storage medium during the BIOS power-on self test. The boot order of the disk storage mediums in the software RAID is automatically changed to position the secondary disk storage medium in the RAID higher in the boot order than the primary disk storage medium in response to detecting a hardware failure in the primary disk storage medium. The operating system is then booted from the disk storage medium that is highest in the boot order. A hardware failure may be detected by reading and verifying a predetermined portion of the boot partition of the disk storage medium.
    Type: Application
    Filed: September 14, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Justin Pierce, David Steiner, Richard W. Vanderpool, III
  • Publication number: 20110035635
    Abstract: An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Masayoshi Nomura
  • Publication number: 20110004784
    Abstract: A data accessing method applied to a data accessing system, comprising: (a) performing a logic operation to a plurality of data units to generate at least one logic operation data unit; (b) performing an anti logic operation to the logic operation data unit and an other data unit to obtain a recovery data unit wherein the other data unit comprises the data units except a specific data unit in the data units; and (c) replacing the specific data unit with the recovery data unit, when the specific data unit is read and is found having an error.
    Type: Application
    Filed: April 5, 2010
    Publication date: January 6, 2011
    Inventors: Shih-Hung Lan, Sheng-I Hsu
  • Publication number: 20100306582
    Abstract: A method of operating a nonvolatile memory device includes performing a program operation on memory cells included in a selected page, checking whether a verification operation for the programmed memory cells is passed or failed by performing the verification operation, counting a number of error bits for the selected page, if the verification operation is failed, performing an error checking and correction (ECC) algorithm using an error correction circuit, if the counted number of error bits is less than or equal to a number of correctable bits, and storing the counted number of error bits in a specific one of a plurality of memory blocks.
    Type: Application
    Filed: May 13, 2010
    Publication date: December 2, 2010
    Inventors: Jung Chul Han, Byoung Kwan Jeong
  • Publication number: 20100281297
    Abstract: A system comprising a first memory, a second memory, and a controller. The first memory may be configured to store a first firmware. The second memory may be configured to store a second firmware similar to the first firmware stored on the first memory. The controller may be configured to (i) operate the first firmware stored on the first memory, (ii) discontinue operating the first firmware in response to a failure of the first firmware, and (iii) begin operating the second firmware after discontinuing operation of the first firmware.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Inventors: Mahmoud K. Jibbe, Rajasekaran Jeevanandham, Uma K
  • Publication number: 20100251013
    Abstract: A method for processing a bad block in a redundant array of independent disks (RAID) is presented, which is characterized by a software RAID constructed by a scale computer interface disk, and adapted to backup data in a bad block in the software RAID. The method includes invoking an access error program to intercept an access instruction for a data block in the software RAID when the data block is a bad block; searching a disk number and a logical block address of the data block in the software RAID according to the access instruction; selecting the scale computer interface disk; and mapping data stored in the data block, the disk number, and the logical block address to a reserved local memory of the scale computer interface disk. Through the above steps, the data in the bad block can be mapped to a normal block, thus maintaining the data integrity.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: Inventec Corporation
    Inventors: Hai-Ting Yao, Qing-Xiu Wu, Tom Chen
  • Publication number: 20100251012
    Abstract: A data volume rebuilder reduces the time required to reconstruct lost data in a RAID protected data volume operating with a failed physical disk drive. A data volume rebuilder uses the remaining functioning physical disk drives in the RAID protected data volume operating with the failed disk to regenerate the lost data and populate a virtual hot spare store allocated in a separate RAID protected data volume. The recovered data is distributed across the physical disk drives supporting the virtual hot spare store. Once the virtual hot spare store is populated, the data volume can recover from a subsequent failure of a second physical disk drive in either RAID group. After replacement of the failed physical disk drive, the data volume rebuilder moves the recovered data from the virtual hot spare store to the new physical disk drive.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: LSI CORPORATION
    Inventors: Ross E. Zwisler, Brian D. McKean
  • Publication number: 20100218040
    Abstract: A method and apparatus for of storing data comprising monitoring a plurality of storage units within a mass storage area and detecting when a storage unit within the mass storage area is overloaded. The method further comprising randomly distributing the data on the overloaded storage unit to the other storage units within the mass storage area.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Applicant: VeriSign, Inc.
    Inventors: Brian Bodmer, Eric Bodnar, Mark Tarantino, Jonah Kaj Fleming, Devdutt Sheth
  • Publication number: 20100122115
    Abstract: Realigning storage devices arranged as storage arrays when one of the storage arrays enters a critical state after failure of a storage device is disclosed. The method is particularly useful for RAID groups of storage devices. The method may be used with hard disk drives, solid-state drives, and other storage devices arranged as groups. The method includes identifying when a storage array of a plurality of storage arrays is in a critical condition. A critical condition storage array and a healthy storage array are identified. Both the critical condition storage array and the healthy storage array are rebuilt. The rebuilding includes configuring the critical condition storage array to include a storage device from the healthy storage array and configuring the healthy storage array to function with one less storage device. The method may be implemented in hardware, firmware, software, or a combination thereof.
    Type: Application
    Filed: November 11, 2008
    Publication date: May 13, 2010
    Inventor: Dan Olster
  • Publication number: 20100064164
    Abstract: A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failure that requires service, repair, or replacement, the surviving functions notify the service management software of the state of the independent functions. The service management software then determines the state of the overall component and implements the appropriate service method.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Applicant: International Business Machines Corporation
    Inventors: Linda V. Benhase, Basheer N. Bristow, Robert A. Kubo, Gregg S. Lucas
  • Publication number: 20100050016
    Abstract: A method and related computer program product of preventing write corruption in a redundant array in a computer system, comprising detecting a write failure from a calling application to at least one disk of the redundant array, writing failure information to non-volatile storage; returning an I/O error to the calling application; reading the failure information from the non-volatile storage during the next system reboot; and reconfiguring the array to eliminate the failed disk.
    Type: Application
    Filed: October 28, 2009
    Publication date: February 25, 2010
    Applicant: BROADCOM CORPORATION
    Inventors: Chris R. FRANKLIN, Jeffery T. WONG
  • Publication number: 20100031082
    Abstract: Rebuilding a storage device after failure of a storage device is disclosed. The method is particularly useful for RAID groups of hard disks. The method may also apply to other storage media arranged as a group. The method includes rebuilding a hard disk in a non-linear fashion according to a heuristic analysis of logical units of the failed hard disk. The method may be implemented in hardware, firmware, software, or a combination thereof.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Inventor: Dan Olster
  • Publication number: 20100023804
    Abstract: A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Inventors: John A. Wickeraad, Jonathan E. Greenlaw
  • Publication number: 20090327803
    Abstract: A RAID is configured using plural nonvolatile semiconductor memory devices to enable recovery of data stored in the nonvolatile semiconductor memory devices, and data is read from the nonvolatile semiconductor memory device included in the RAID in response to a data reading request inputted from outside. When an error occurs during the reading, data for which the reading error occurs is recovered, and rewritten into an area of the nonvolatile semiconductor memory device in which the reading error occurs.
    Type: Application
    Filed: March 2, 2009
    Publication date: December 31, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Fukutomi, Hideaki Sato, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20090282285
    Abstract: A semiconductor integrated circuit has a memory circuit having memory cells, a first register, a second register, a register selection circuit having an input to which an output of the first register and an output of the second register are connected, a memory bypass circuit which is located between a first switching circuit and a second switching circuit, and connected to the inputs and the outputs of the memory circuit. The register selection circuit is switched to the output signals of the first register when performing testing by way of the memory circuit, and switched to output signals of the second register when performing testing by way of the memory bypass circuit.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 12, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsu HASEGAWA, Chikako TOKUNAGA
  • Publication number: 20090259882
    Abstract: A RAID controller uses a method to identify a storage device of a redundant array of storage devices that is returning corrupt data to the RAID controller. The method includes reading data from a location of each storage device in the redundant array a first time, and detecting that at least one storage device returned corrupt data. In response to detecting corrupt data, steps are performed for each storage device in the redundant array. The steps include reading data from the location of the storage device a second time without writing to the location in between the first and second reads, comparing the data read the first and second times, and identifying the storage device as a failing storage device if the compared data has a miscompare. Finally, the method includes updating the location of each storage device to a new location and repeating the steps for the new location.
    Type: Application
    Filed: July 31, 2008
    Publication date: October 15, 2009
    Applicant: DOT HILL SYSTEMS CORPORATION
    Inventor: Jeffery Lawrence Shellhamer
  • Publication number: 20090217086
    Abstract: An error table stores information indicating the occurrence of an error. A statistical score addition table stores the number of scores for disk or path according to the error. A control unit adds the first number of scores to the error disk. Also, when the information indicating the occurrence of the error is not stored in the error table, the control unit adds the second number of scores smaller than the first number of scores to the path to the error disk, while when the information is stored, the control unit adds the third number of scores larger than the first number of scores to the path. The control unit separates the path or disk of which the number of scores exceeds a threshold from the disk array apparatus.
    Type: Application
    Filed: October 22, 2008
    Publication date: August 27, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kiyoshi Tanaka, Fumio Hanazawa, Akira Sanpei, Hiroaki Sato, Keiju Takizawa