Abstract: Disclosed herein are techniques for efficiently providing controller data as part of a maintenance or update process. Techniques include receiving, from a first remote computing device, a message associated with at least one controller extracting, based on the received message, an image of software associated with the at least one controller; accessing, based on the extracted image, a delta file; and transmitting the accessed delta file to a second remote computing device.

Abstract: Disclosed herein are techniques for efficiently providing controller data as part of a maintenance or update process. Techniques include receiving, from a first remote computing device, a message associated with at least one controller; extracting, based on the received message, an image of software associated with the at least one controller; accessing, based on the extracted image, a delta file; and transmitting the accessed delta file to a second remote computing device.

Abstract: A method that prepares data for analysis includes displaying a user interface that includes a data a data flow pane that displays a flow diagram having a plurality of nodes, each node specifying a respective primary operation, a change list pane corresponding to a user-selected node in the data flow pane, and a data pane that displays a plurality of rows for an intermediate dataset of the user-selected node. The method also includes, in response to receiving a user input to perform a secondary operation at the user-selected node: (i) displaying, in the change list pane, an ordered list of secondary operations performed at the user-selected node, including displaying the secondary operation, and (ii) updating the data pane in accordance with the secondary operation, including updating the plurality of rows for the intermediate dataset.

Abstract: An example includes accessing multiple configurations stored in a memory, where each configuration is associated with a corresponding circuit function implementable by an electronic device and associated with a corresponding set of resources of the electronic device. The example includes determining that one or more sets of resources of the electronic device are available for use by one or more configurations of the multiple configurations. Based on the determination, an embodiment includes representing a first configuration of the one or more configurations, using a graphical interface, and generating instructions that when executed cause the electronic device to be configured according the first configurations.

Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.

Abstract: A test apparatus for testing peripheral component interconnect express (PCIe) signals transmission of a motherboard includes a printed circuit board including an edge connector, a number of first switches having a same number with the type of the PCIe signals to be test, an encoder, and a microprocessor. The first switches are used to select a type selection signal. The encoder converts signals outputted from the first switches to binary data. The microprocessor outputs clock signals to a PCIe controller according to the binary data to make the PCIe controller transmit the PCIe signal to the PCIe slot.

Abstract: An electronic connection quality test device includes a plurality of test circuits, a hot plug circuit, and a control circuit. The test circuits are respectively electrically connected to a plurality of universal serial bus (USB) interfaces. The hot plug circuit is electrically connected to each of the test circuits and a USB device. The control circuit is electrically connected to each of the test circuits and controls the test circuits to electrically connect selected ones of the USB interfaces with the USB device via the test circuits and the hot plug circuit, thereby forming tested electronic connections between the selected ones of the USB interfaces and the USB device.

Abstract: A computer system and a diagnostic method thereof are provided. The computer system comprises a system management bus (SMBus) switch, a plurality of servers and a remote management controller (RMC). Each server comprises a diagnostic message port, a basic input output system (BIOS) and a logic circuit. The BIOS outputs a diagnostic message to the diagnostic message port. The logic circuit catches the diagnostic message. The RMC comprises a SMBus host controller. The SMBus host controller controls the SMBus switch to connect the SMBus host controller to a corresponding logic circuit according to a request. The logic circuit responds the diagnostic message to the SMBus host controller according to the request.

Abstract: Debug circuitry is operated in a manner that facilitates debugging one or more hardware and/or software components that are included in a system that includes a system memory. The debug circuitry receives information from one of the hardware and/or software components and/or from the system memory, and ascertains whether the received information includes memory address parameters. If the received information includes memory address parameters, then the memory address parameters are used to retrieve data from the system memory. The retrieved data is supplied at an output port of the debug circuitry.

Abstract: The present invention relates to an automatic testing apparatus used for testing a tested device. The automatic testing apparatus is fixed on a first side of a testing platform. The tested device executes a testing program while being tested, and transmits a test signal to a control unit of the testing platform for controlling a driving testing unit or a multimedia testing module to test the tested device and hence testing the tested device automatically. Thereby, testing costs can be saved and artificial factor affecting the test results can be avoided.

Abstract: A debug card for diagnosing a motherboard and a power supply unit (PSU) of a same computer includes a plurality of first nixie tubes, a plurality of second nixie tubes, a first port, a second port, and a control unit. The control unit is electronically connected to the plurality of first nixie tubes, the plurality of second nixie tubes, the first port, and the second port. The first port is electronically connected to the motherboard, and the second port is electronically connected to the PSU. Under the control of the control unit, fault codes of the motherboard are displayed by the plurality of the first nixie tubes, and fault codes of the PSU are displayed by the plurality of the second nixie tubes.

Abstract: A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.

Abstract: Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first memory to store firmware for the processor; and a second memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to read a portion of the firmware from a predetermined location in the first memory; wherein the test interface is enabled only when the portion of the firmware has a predetermined value.

Abstract: A storage device transfer station is provided for transferring storage devices from a human operator to automated machinery for testing. The storage device transfer station includes a plurality of slots each capable of holding a storage device. The plurality of slots is arranged in at least one field, and the field is arranged between two parallel planes. Each slot has a first open end and a second open end, such that each open end is accessible for loading and unloading a storage device. The first open ends are accessible at a first plane of the two parallel planes and the second open ends are accessible at a second plane of the two parallel planes.

Abstract: A system and method of providing driver software to a test controller to facilitate testing by a wireless transceiver tester of a device under test (DUT). Using the wireless transceiver tester, executable tester instructions are accessed from one or more computer readable media and in accordance therewith bi-directional signal communications are established between the wireless transceiver tester and the test controller, and between the wireless transceiver tester and the DUT. Further accessed are executable driver instructions, including a plurality of executable driver program instructions for driving at least one of the wireless transceiver tester and the DUT, which are communicated to the test controller.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: A device includes a first test port coupled to a first test device, a second test port coupled to a second test device, a resource, and a security controller coupled to the first and second test ports. The security controller is operable to authenticate the first test device prior to authenticating the second test device, and, in response to authenticating the first test device, permit the first and second test devices to access the first resource.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group comprises single or plural core circuits. The test control flag register enables a set of test signals to input in one of the test groups, testing the core circuits in the test group.

Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.